gistfile1.txt

module EICG_wrapper(
  output out,
  input en,
  input test_en,
  input in
);

  reg en_latched /*verilator clock_enable*/;

  always @(*) begin
     if (!in) begin
        en_latched = en || test_en;
     end
  end

  assign out = en_latched && in;

endmodule

gistfile2.txt

  hw.module private @EICG_wrapper(out out : i1, in %en : i1, in %test_en : i1, in %in : i1) {
    %0 = llhd.constant_time <0ns, 0d, 1e>
    %true = hw.constant true
    %false = hw.constant false
    %en_latched = llhd.sig %false : i1
    %1 = llhd.prb %en_latched : i1
    %2 = comb.xor %in, %true : i1
    %3 = comb.or %en, %test_en : i1
    %4 = comb.and %2, %3 : i1
    llhd.drv %en_latched, %4 after %0 if %2 : i1
    %5 = comb.and %1, %in : i1
    hw.output %5 : i1
  }