gistfile1.v

module RegisterFile (Read1, Read2, Write, RegWrite, WriteData, Data1, Data2);
	input [2:0] Read1, Read2, Write;
	input [15:0] WriteData;
	input RegWrite;
	output [15:0] Data1, Data2;
	reg [15:0] RegFile [0:2];

	always @(posedge RegWrite) begin
	  if (RegWrite) begin
	    RegFile[Write] = WriteData;
	  end
	end
	assign Data1 = RegFile[Read1];
	assign Data2 = RegFile[Read2];
endmodule