reg v. wire example

gistfile1.v

module add(a, b, out);
    input  [4:0] a, b;
    output [4:0] out;
    
    wire a, b;
    reg out;
    
    always @(a or b)
        out = a + b;
endmodule;

module sub(a, b, out);
    input  [4:0] a, b;
    output [4:0] out;
    
    wire a, b;
    reg out;
    
    always @(a or b)
        out = a - b;
endmodule;

module test();
    wire [4:0] sum, diff;

    add add0(4'b0010, 4'b0011, sum);
    sub sub0(sum, 4'b0001, diff);
endmodule;