ALU start

alu.sv

module alu(input logic [31:0] A, B, input logic [2:0] OPC, output logic [31:0] Y);
    logic [31:0] temp;
    Shifter shift(.A(A), .B(B), .Y(temp));
    always_comb
        case(OPC)
            0: Y = temp;
            default: Y = 32'd0;
        endcase
endmodule

module Shifter(input logic [31:0] A, B, output logic [31:0] Y);
    assign Y = A << B;
endmodule