divide_asm_aarch64_u0-x_report

00000000004005d0 <divide>:
  4005d0:	a9bd7bfd 	stp	x29, x30, [sp,#-48]!
  4005d4:	910003fd 	mov	x29, sp
  4005d8:	b9001fa0 	str	w0, [x29,#28]
  4005dc:	b9001ba1 	str	w1, [x29,#24]
  4005e0:	b9401ba0 	ldr	w0, [x29,#24]
  4005e4:	7100001f 	cmp	w0, #0x0
  4005e8:	54000041 	b.ne	4005f0 <divide+0x20>
  4005ec:	97fffff5 	bl	4005c0 <divide_zero_error>
  4005f0:	b90023bf 	str	wzr, [x29,#32]
  4005f4:	b90027bf 	str	wzr, [x29,#36]
  4005f8:	528003e0 	mov	w0, #0x1f                  	// #31
  4005fc:	b9002fa0 	str	w0, [x29,#44]
  400600:	1400001c 	b	400670 <divide+0xa0>
  400604:	b94027a0 	ldr	w0, [x29,#36]
  400608:	531f7800 	lsl	w0, w0, #1
  40060c:	b90027a0 	str	w0, [x29,#36]
  400610:	b94027a1 	ldr	w1, [x29,#36]
  400614:	b9402fa0 	ldr	w0, [x29,#44]
  400618:	b9401fa2 	ldr	w2, [x29,#28]
  40061c:	1ac02440 	lsr	w0, w2, w0
  400620:	12000000 	and	w0, w0, #0x1
  400624:	2a000020 	orr	w0, w1, w0
  400628:	b90027a0 	str	w0, [x29,#36]
  40062c:	b94027a1 	ldr	w1, [x29,#36]
  400630:	b9401ba0 	ldr	w0, [x29,#24]
  400634:	6b00003f 	cmp	w1, w0
  400638:	54000163 	b.cc	400664 <divide+0x94>
  40063c:	b94027a1 	ldr	w1, [x29,#36]
  400640:	b9401ba0 	ldr	w0, [x29,#24]
  400644:	4b000020 	sub	w0, w1, w0
  400648:	b90027a0 	str	w0, [x29,#36]
  40064c:	b94023a0 	ldr	w0, [x29,#32]
  400650:	b9402fa1 	ldr	w1, [x29,#44]
  400654:	52800022 	mov	w2, #0x1                   	// #1
  400658:	1ac12041 	lsl	w1, w2, w1
  40065c:	2a010000 	orr	w0, w0, w1
  400660:	b90023a0 	str	w0, [x29,#32]
  400664:	b9402fa0 	ldr	w0, [x29,#44]
  400668:	51000400 	sub	w0, w0, #0x1
  40066c:	b9002fa0 	str	w0, [x29,#44]
  400670:	b9402fa0 	ldr	w0, [x29,#44]
  400674:	7100001f 	cmp	w0, #0x0
  400678:	54fffc6a 	b.ge	400604 <divide+0x34>
  40067c:	f94013a0 	ldr	x0, [x29,#32]
  400680:	a8c37bfd 	ldp	x29, x30, [sp],#48
  400684:	d65f03c0 	ret