aw-thermal.diff

diff --git i/sys/arm/allwinner/aw_thermal.c w/sys/arm/allwinner/aw_thermal.c
index 5143cda95fb..f8db25a9443 100644
--- i/sys/arm/allwinner/aw_thermal.c
+++ w/sys/arm/allwinner/aw_thermal.c
@@ -248,9 +248,9 @@ static const struct aw_thermal_config h3_config = {
 };
 
 static struct ofw_compat_data compat_data[] = {
-	{ "allwinner,sun8i-a83t-ts",	(uintptr_t)&a83t_config },
-	{ "allwinner,sun8i-h3-ts",	(uintptr_t)&h3_config },
-	{ "allwinner,sun50i-a64-ts",	(uintptr_t)&a64_config },
+	{ "allwinner,sun8i-a83t-ths",	(uintptr_t)&a83t_config },
+	{ "allwinner,sun8i-h3-ths",	(uintptr_t)&h3_config },
+	{ "allwinner,sun50i-a64-ths",	(uintptr_t)&a64_config },
 	{ NULL,				(uintptr_t)NULL }
 };
 
@@ -514,17 +514,17 @@ aw_thermal_attach(device_t dev)
 		return (ENXIO);
 	}
 
-	if (clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb) == 0) {
+	if (clk_get_by_ofw_name(dev, 0, "bus", &clk_ahb) == 0) {
 		error = clk_enable(clk_ahb);
 		if (error != 0) {
-			device_printf(dev, "cannot enable ahb clock\n");
+			device_printf(dev, "cannot enable ahb (bus) clock\n");
 			goto fail;
 		}
 	}
-	if (clk_get_by_ofw_name(dev, 0, "ths", &clk_ths) == 0) {
+	if (clk_get_by_ofw_name(dev, 0, "mod", &clk_ths) == 0) {
 		error = clk_set_freq(clk_ths, sc->conf->clk_rate, 0);
 		if (error != 0) {
-			device_printf(dev, "cannot set ths clock rate\n");
+			device_printf(dev, "cannot set mod (ths) clock rate\n");
 			goto fail;
 		}
 		error = clk_enable(clk_ths);
@@ -557,8 +557,10 @@ aw_thermal_attach(device_t dev)
 			    sc->conf->sensors[i].init_shut);
 	}
 
-	if (aw_thermal_init(sc) != 0)
+	if (aw_thermal_init(sc) != 0) {
+		device_printf(dev, "cannot initialize\n");
 		goto fail;
+	}
 
 	for (i = 0; i < sc->conf->nsensors; i++)
 		SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
diff --git i/sys/gnu/dts/arm/sun8i-a83t.dtsi w/sys/gnu/dts/arm/sun8i-a83t.dtsi
index 19acae1b408..855c9281c91 100644
--- i/sys/gnu/dts/arm/sun8i-a83t.dtsi
+++ w/sys/gnu/dts/arm/sun8i-a83t.dtsi
@@ -395,6 +395,14 @@
 			clocks = <&osc24M>;
 		};
 
+		ths: thermal-sensor@1f04000 {
+			compatible = "allwinner,sun8i-a83t-ths";
+			reg = <0x01f04000 0x100>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			#thermal-sensor-cells = <1>;
+			#io-channel-cells = <0>;
+		};
+
 		watchdog@1c20ca0 {
 			compatible = "allwinner,sun6i-a31-wdt";
 			reg = <0x01c20ca0 0x20>;
diff --git i/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts w/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts
index d22546df1b8..9cd11b79cf1 100644
--- i/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts
+++ w/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts
@@ -95,7 +95,7 @@
 		"Line Out", "LINEOUT",
 		"MIC1", "Mic",
 		"Mic",  "MBIAS";
-	status = "okay";
+	status = "disabled";
 };
 
 &ehci0 {
diff --git i/sys/gnu/dts/arm/sun8i-h3.dtsi w/sys/gnu/dts/arm/sun8i-h3.dtsi
index b36f9f423c3..d49190d4f95 100644
--- i/sys/gnu/dts/arm/sun8i-h3.dtsi
+++ w/sys/gnu/dts/arm/sun8i-h3.dtsi
@@ -124,3 +124,8 @@
 &pio {
 	compatible = "allwinner,sun8i-h3-pinctrl";
 };
+
+&ths {
+	compatible = "allwinner,sun8i-h3-ths";
+	#thermal-sensor-cells = <0>;
+};
diff --git i/sys/gnu/dts/arm/sunxi-h3-h5.dtsi w/sys/gnu/dts/arm/sunxi-h3-h5.dtsi
index 8d40c00d64b..560b7e0de06 100644
--- i/sys/gnu/dts/arm/sunxi-h3-h5.dtsi
+++ w/sys/gnu/dts/arm/sunxi-h3-h5.dtsi
@@ -388,6 +388,15 @@
 			};
 		};
 
+		ths: thermal-sensor@1c25000 {
+			reg = <0x01c25000 0x400>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_THS>;
+			#io-channel-cells = <0>;
+		};
+
 		timer@1c20c00 {
 			compatible = "allwinner,sun4i-a10-timer";
 			reg = <0x01c20c00 0xa0>;