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Created September 20, 2024 08:49
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AMDGPU bug #672
; ModuleID = 'broken.ll'
source_filename = "start"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:10:11:12:13"
target triple = "amdgcn-amd-amdhsa"
; Function Attrs: nounwind readnone speculatable willreturn
declare i32 @llvm.amdgcn.workitem.id.x() #0
define amdgpu_kernel void @wibble({ i64, i64, i64, i64, i64, i64, i32, i32, i64, i64, i64, i64 } %arg, i64 zeroext %arg1, i64 signext %arg2, i64 signext %arg3) local_unnamed_addr #1 {
bb:
%tmp = call i32 @llvm.amdgcn.workitem.id.x(), !range !7
%tmp4 = icmp ugt i32 %tmp, 9
br i1 %tmp4, label %bb23, label %bb24
bb5: ; preds = %bb30, %bb14
%tmp6 = phi i64 [ %tmp17, %bb14 ], [ %tmp25, %bb30 ]
%tmp7 = phi double [ %tmp15, %bb14 ], [ 0.000000e+00, %bb30 ]
br i1 %tmp35, label %bb14, label %bb8
bb8: ; preds = %bb8, %bb5
%tmp9 = phi double [ %tmp11, %bb8 ], [ %tmp7, %bb5 ]
%tmp10 = phi i64 [ %tmp13, %bb8 ], [ %tmp31, %bb5 ]
%tmp11 = fadd double %tmp9, 1.000000e+00
%tmp12 = icmp eq i64 %tmp10, %tmp34
%tmp13 = add i64 %tmp10, 1
br i1 %tmp12, label %bb14, label %bb8
bb14: ; preds = %bb8, %bb5
%tmp15 = phi double [ %tmp7, %bb5 ], [ %tmp11, %bb8 ]
%tmp16 = icmp eq i64 %tmp6, %tmp28
%tmp17 = add i64 %tmp6, 1
br i1 %tmp16, label %bb18, label %bb5
bb18: ; preds = %bb24, %bb14
%tmp19 = phi double [ 0.000000e+00, %bb24 ], [ %tmp15, %bb14 ]
%tmp20 = zext i32 %tmp to i64
%tmp21 = inttoptr i64 %arg1 to double*
%tmp22 = getelementptr inbounds double, double* %tmp21, i64 %tmp20
store double %tmp19, double* %tmp22, align 1, !tbaa !8, !alias.scope !12, !noalias !15
br label %bb23
bb23: ; preds = %bb18, %bb
ret void
bb24: ; preds = %bb
%tmp25 = sub i64 0, %arg2
%tmp26 = icmp sgt i64 %tmp25, %arg2
%tmp27 = sext i1 %tmp26 to i64
%tmp28 = xor i64 %tmp27, %arg2
%tmp29 = icmp slt i64 %tmp28, %tmp25
br i1 %tmp29, label %bb18, label %bb30
bb30: ; preds = %bb24
%tmp31 = sub i64 0, %arg3
%tmp32 = icmp sgt i64 %tmp31, %arg3
%tmp33 = sext i1 %tmp32 to i64
%tmp34 = xor i64 %tmp33, %arg3
%tmp35 = icmp slt i64 %tmp34, %tmp31
br label %bb5
}
attributes #0 = { nounwind readnone speculatable willreturn }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "target-cpu"="gfx1103" "target-features"="+wavefrontsize32,-wavefrontsize64" }
!llvm.module.flags = !{!0, !1, !2, !3}
!opencl.ocl.version = !{!4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4}
!llvm.ident = !{!5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5}
!julia.kernel = !{!6}
!0 = !{i32 2, !"Dwarf Version", i32 4}
!1 = !{i32 2, !"Debug Info Version", i32 3}
!2 = !{i32 1, !"wchar_size", i32 4}
!3 = !{i32 7, !"PIC Level", i32 1}
!4 = !{i32 2, i32 0}
!5 = !{!"clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"}
!6 = !{void ({ i64, i64, i64, i64, i64, i64, i32, i32, i64, i64, i64, i64 }, i64, i64, i64)* @wibble}
!7 = !{i32 0, i32 1023}
!8 = !{!9, !9, i64 0}
!9 = !{!"jtbaa_data", !10, i64 0}
!10 = !{!"jtbaa", !11, i64 0}
!11 = !{!"jtbaa"}
!12 = !{!13}
!13 = !{!"jnoalias_data", !14}
!14 = !{!"jnoalias"}
!15 = !{!16, !17, !18, !19}
!16 = !{!"jnoalias_gcframe", !14}
!17 = !{!"jnoalias_stack", !14}
!18 = !{!"jnoalias_typemd", !14}
!19 = !{!"jnoalias_const", !14}
; ModuleID = 'broken.ll'
source_filename = "start"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:10:11:12:13"
target triple = "amdgcn-amd-amdhsa"
; Function Attrs: nounwind readnone speculatable willreturn
declare i32 @llvm.amdgcn.workitem.id.x() #0
define amdgpu_kernel void @wibble({ i64, i64, i64, i64, i64, i64, i32, i32, i64, i64, i64, i64 } %arg, i64 zeroext %arg1, i64 signext %arg2, i64 signext %arg3) local_unnamed_addr #1 {
bb:
%tmp = call i32 @llvm.amdgcn.workitem.id.x(), !range !7
%tmp4 = icmp ugt i32 %tmp, 9
br i1 %tmp4, label %bb23, label %bb24
bb24: ; preds = %bb
%tmp25 = sub i64 0, %arg2
%tmp26 = icmp sgt i64 %tmp25, %arg2
%tmp27 = sext i1 %tmp26 to i64
%tmp28 = xor i64 %tmp27, %arg2
%tmp29 = icmp slt i64 %tmp28, %tmp25
br i1 %tmp29, label %bb18, label %bb30
bb30: ; preds = %bb24
%tmp31 = sub i64 0, %arg3
%tmp32 = icmp sgt i64 %tmp31, %arg3
%tmp33 = sext i1 %tmp32 to i64
%tmp34 = xor i64 %tmp33, %arg3
%tmp35 = icmp slt i64 %tmp34, %tmp31
br label %bb5
bb5: ; preds = %bb30, %bb14
%tmp6 = phi i64 [ %tmp17, %bb14 ], [ %tmp25, %bb30 ]
%tmp7 = phi double [ %tmp15, %bb14 ], [ 0.000000e+00, %bb30 ]
br i1 %tmp35, label %bb14, label %bb8
bb8: ; preds = %bb8, %bb5
%tmp9 = phi double [ %tmp11, %bb8 ], [ %tmp7, %bb5 ]
%tmp10 = phi i64 [ %tmp13, %bb8 ], [ %tmp31, %bb5 ]
%tmp11 = fadd double %tmp9, 1.000000e+00
%tmp12 = icmp eq i64 %tmp10, %tmp34
%tmp13 = add i64 %tmp10, 1
br i1 %tmp12, label %bb14, label %bb8
bb14: ; preds = %bb8, %bb5
%tmp15 = phi double [ %tmp7, %bb5 ], [ %tmp11, %bb8 ]
%tmp16 = icmp eq i64 %tmp6, %tmp28
%tmp17 = add i64 %tmp6, 1
br i1 %tmp16, label %bb18, label %bb5
bb18: ; preds = %bb24, %bb14
%tmp19 = phi double [ 0.000000e+00, %bb24 ], [ %tmp15, %bb14 ]
%tmp20 = zext i32 %tmp to i64
%tmp21 = inttoptr i64 %arg1 to double*
%tmp22 = getelementptr inbounds double, double* %tmp21, i64 %tmp20
store double %tmp19, double* %tmp22, align 1, !tbaa !8, !alias.scope !12, !noalias !15
br label %bb23
bb23: ; preds = %bb18, %bb
ret void
}
attributes #0 = { nounwind readnone speculatable willreturn }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "target-cpu"="gfx1103" "target-features"="+wavefrontsize32,-wavefrontsize64" }
!llvm.module.flags = !{!0, !1, !2, !3}
!opencl.ocl.version = !{!4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4, !4}
!llvm.ident = !{!5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5, !5}
!julia.kernel = !{!6}
!0 = !{i32 2, !"Dwarf Version", i32 4}
!1 = !{i32 2, !"Debug Info Version", i32 3}
!2 = !{i32 1, !"wchar_size", i32 4}
!3 = !{i32 7, !"PIC Level", i32 1}
!4 = !{i32 2, i32 0}
!5 = !{!"clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"}
!6 = !{void ({ i64, i64, i64, i64, i64, i64, i32, i32, i64, i64, i64, i64 }, i64, i64, i64)* @wibble}
!7 = !{i32 0, i32 1023}
!8 = !{!9, !9, i64 0}
!9 = !{!"jtbaa_data", !10, i64 0}
!10 = !{!"jtbaa", !11, i64 0}
!11 = !{!"jtbaa"}
!12 = !{!13}
!13 = !{!"jnoalias_data", !14}
!14 = !{!"jnoalias"}
!15 = !{!16, !17, !18, !19}
!16 = !{!"jnoalias_gcframe", !14}
!17 = !{!"jnoalias_stack", !14}
!18 = !{!"jnoalias_typemd", !14}
!19 = !{!"jnoalias_const", !14}
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx700"
.globl wibble ; -- Begin function wibble
.p2align 8
.type wibble,@function
wibble: ; @wibble
; %bb.0: ; %bb
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 10, v0
s_cbranch_execz .LBB0_8
; %bb.1: ; %bb24
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x58
s_load_b64 s[2:3], s[0:1], 0x68
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_sub_u32 s0, 0, s6
s_subb_u32 s1, 0, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s8, s[0:1], s[6:7]
v_cndmask_b32_e64 v2, 0, -1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, s6, v2
v_xor_b32_e32 v2, s7, v2
v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[1:2]
s_cbranch_vccnz .LBB0_7
; %bb.2: ; %bb30
s_sub_u32 s6, 0, s2
s_subb_u32 s7, 0, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s8, s[6:7], s[2:3]
v_cndmask_b32_e64 v3, 0, -1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s8, v3
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[8:9], s[8:9], s[2:3]
s_add_u32 s2, s8, s2
v_cmp_ge_i64_e64 s8, s[8:9], s[6:7]
s_addc_u32 s3, s9, s3
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_branch .LBB0_4
.LBB0_3: ; %bb14
; in Loop: Header=BB0_4 Depth=1
v_cmp_ne_u64_e32 vcc_lo, s[0:1], v[1:2]
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cbranch_vccz .LBB0_7
.LBB0_4: ; %bb5
; =>This Loop Header: Depth=1
; Child Loop BB0_6 Depth 2
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_3
; %bb.5: ; %bb8.preheader
; in Loop: Header=BB0_4 Depth=1
s_mov_b64 s[6:7], s[2:3]
.LBB0_6: ; %bb8
; Parent Loop BB0_4 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[3:4], v[3:4], 1.0
s_add_u32 s6, s6, -1
s_addc_u32 s7, s7, -1
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc1 .LBB0_6
s_branch .LBB0_3
.LBB0_7: ; %bb18
v_lshlrev_b32_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 24, v4
v_lshrrev_b32_e32 v5, 8, v4
v_lshrrev_b32_e32 v6, 24, v3
v_lshrrev_b32_e32 v7, 8, v3
v_add_co_u32 v0, s0, s4, v0
v_add_co_ci_u32_e64 v1, null, s5, 0, s0
s_clause 0x7
flat_store_b8 v[0:1], v2 offset:7
flat_store_d16_hi_b8 v[0:1], v4 offset:6
flat_store_b8 v[0:1], v5 offset:5
flat_store_b8 v[0:1], v4 offset:4
flat_store_b8 v[0:1], v6 offset:3
flat_store_d16_hi_b8 v[0:1], v3 offset:2
flat_store_b8 v[0:1], v7 offset:1
flat_store_b8 v[0:1], v3
.LBB0_8: ; %bb23
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel wibble
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 112
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 0
.amdhsa_memory_ordered 0
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size wibble, .Lfunc_end0-wibble
; -- End function
.section .AMDGPU.csdata
; Kernel info:
; codeLenInByte = 376
; NumSgprs: 12
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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.section ".note.GNU-stack"
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .name: arg
.offset: 0
.size: 88
.value_kind: by_value
- .name: arg1
.offset: 88
.size: 8
.value_kind: by_value
- .name: arg2
.offset: 96
.size: 8
.value_kind: by_value
- .name: arg3
.offset: 104
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 112
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: wibble
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: wibble.kd
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
amdhsa.target: amdgcn-amd-amdhsa--gfx700
amdhsa.version:
- 1
- 1
...
.end_amdgpu_metadata
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx700"
.globl wibble ; -- Begin function wibble
.p2align 8
.type wibble,@function
wibble: ; @wibble
; %bb.0: ; %bb
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 10, v0
s_cbranch_execz .LBB0_8
; %bb.1: ; %bb24
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x58
s_load_b64 s[2:3], s[0:1], 0x68
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_sub_u32 s0, 0, s6
s_subb_u32 s1, 0, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s8, s[0:1], s[6:7]
v_cndmask_b32_e64 v2, 0, -1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, s6, v2
v_xor_b32_e32 v2, s7, v2
v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[1:2]
s_cbranch_vccnz .LBB0_7
; %bb.2: ; %bb30
s_sub_u32 s6, 0, s2
s_subb_u32 s7, 0, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s8, s[6:7], s[2:3]
v_cndmask_b32_e64 v3, 0, -1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s8, v3
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[8:9], s[8:9], s[2:3]
v_cmp_ge_i64_e64 s6, s[8:9], s[6:7]
s_add_u32 s2, s8, s2
s_addc_u32 s3, s9, s3
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_branch .LBB0_4
.LBB0_3: ; %bb14
; in Loop: Header=BB0_4 Depth=1
v_cmp_ne_u64_e32 vcc_lo, s[0:1], v[1:2]
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cbranch_vccz .LBB0_7
.LBB0_4: ; %bb5
; =>This Loop Header: Depth=1
; Child Loop BB0_6 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_3
; %bb.5: ; %bb8.preheader
; in Loop: Header=BB0_4 Depth=1
s_mov_b64 s[6:7], s[2:3]
.LBB0_6: ; %bb8
; Parent Loop BB0_4 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[3:4], v[3:4], 1.0
s_add_u32 s6, s6, -1
s_addc_u32 s7, s7, -1
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc1 .LBB0_6
s_branch .LBB0_3
.LBB0_7: ; %bb18
v_lshlrev_b32_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 24, v4
v_lshrrev_b32_e32 v5, 8, v4
v_lshrrev_b32_e32 v6, 24, v3
v_lshrrev_b32_e32 v7, 8, v3
v_add_co_u32 v0, s0, s4, v0
v_add_co_ci_u32_e64 v1, null, s5, 0, s0
s_clause 0x7
flat_store_b8 v[0:1], v2 offset:7
flat_store_d16_hi_b8 v[0:1], v4 offset:6
flat_store_b8 v[0:1], v5 offset:5
flat_store_b8 v[0:1], v4 offset:4
flat_store_b8 v[0:1], v6 offset:3
flat_store_d16_hi_b8 v[0:1], v3 offset:2
flat_store_b8 v[0:1], v7 offset:1
flat_store_b8 v[0:1], v3
.LBB0_8: ; %bb23
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel wibble
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 112
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 0
.amdhsa_memory_ordered 0
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size wibble, .Lfunc_end0-wibble
; -- End function
.section .AMDGPU.csdata
; Kernel info:
; codeLenInByte = 372
; NumSgprs: 12
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
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.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
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.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
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.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.ident "clang version 15.0.0 (/cache/yggdrasil/downloads/clones/llvm-project.git-974efd367bc513231526d317489c66cb27727ef3caa41108e3819c131a8acf57 f3d695fc2985a8dfdd5f4219d351fdeac3038867)"
.section ".note.GNU-stack"
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .name: arg
.offset: 0
.size: 88
.value_kind: by_value
- .name: arg1
.offset: 88
.size: 8
.value_kind: by_value
- .name: arg2
.offset: 96
.size: 8
.value_kind: by_value
- .name: arg3
.offset: 104
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 112
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: wibble
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: wibble.kd
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
amdhsa.target: amdgcn-amd-amdhsa--gfx700
amdhsa.version:
- 1
- 1
...
.end_amdgpu_metadata
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