Created
August 19, 2013 12:12
-
-
Save venuatu/6268463 to your computer and use it in GitHub Desktop.
apq8084 changes b7ebf8a660dd8ee83ddbf98c352aa670f9b23121 /drivers/video/msm/
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
diff --git a/drivers/video/msm/Kconfig b/drivers/video/msm/Kconfig | |
index e2b5802..a676ed7 100644 | |
--- a/drivers/video/msm/Kconfig | |
+++ b/drivers/video/msm/Kconfig | |
@@ -25,7 +25,7 @@ config FB_MSM_LOGO | |
bool "MSM Frame Buffer Logo" | |
default n | |
---help--- | |
- Show /logo.rle during boot. | |
+ Show /initlogo.rle during boot. | |
config FB_MSM_LCDC_HW | |
bool | |
@@ -361,11 +361,6 @@ config FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT | |
select FB_MSM_MIPI_DSI_RENESAS | |
default n | |
-config FB_MSM_MIPI_RENESAS_VIDEO_SHARP_PT | |
- bool | |
- select FB_MSM_MIPI_DSI_RENESAS | |
- default n | |
- | |
config FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT | |
bool | |
select FB_MSM_MIPI_DSI_RENESAS | |
@@ -457,7 +452,6 @@ config FB_MSM_WRITEBACK_MSM_PANEL | |
Support for MDP4 OVERLAY write back mode | |
choice | |
prompt "LCD Panel" | |
- optional | |
default FB_MSM_MDDI_AUTO_DETECT | |
config FB_MSM_LCDC_PRISM_WVGA_PANEL | |
@@ -568,7 +562,6 @@ config FB_MSM_MIPI_PANEL_DETECT | |
select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT | |
select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA | |
select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT | |
- select FB_MSM_MIPI_RENESAS_VIDEO_SHARP_PT | |
select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT | |
select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT | |
select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT | |
@@ -614,7 +607,6 @@ config FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT | |
select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT | |
select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT | |
select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT | |
- select FB_MSM_MIPI_RENESAS_VIDEO_SHARP_PT | |
select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT | |
select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT | |
select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT | |
@@ -637,7 +629,6 @@ config FB_MSM_LVDS_MIPI_PANEL_DETECT | |
select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT | |
select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA | |
select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT | |
- select FB_MSM_MIPI_RENESAS_VIDEO_SHARP_PT | |
select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT | |
select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT | |
select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT | |
@@ -719,10 +710,6 @@ config FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT_PANEL | |
bool "MIPI Renesas Video FWVGA PT Panel" | |
select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT | |
-config FB_MSM_MIPI_RENESAS_VIDEO_SHARP_PT_LS043K3SX04_PANEL | |
- bool "SHARP LS043K3SX04 Panel" | |
- select FB_MSM_MIPI_RENESAS_VIDEO_SHARP_PT | |
- | |
config FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT_PANEL | |
bool "MIPI Renesas Command FWVGA PT Panel" | |
select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT | |
@@ -803,41 +790,6 @@ config LGIT_VIDEO_WXGA_CABC | |
Enable CABC(Content Apaptive Backlight Control) on LGIT Panel | |
to reduce power consumption | |
-config FB_MSM_MIPI_R63306_SHARP_LS043K3SX04 | |
- bool "SHARP LS043K3SX04 Panel" | |
- select FB_MSM_MIPI_DSI | |
- default n | |
- | |
-config FB_MSM_MIPI_R63311_SHARP_LS050T3SX02 | |
- bool "SHARP LS050T3SX02 Panel" | |
- select FB_MSM_MIPI_DSI | |
- default n | |
- | |
-config FB_MSM_MIPI_R63306_TMD_MDW30 | |
- bool "TMD MDW30 Panel" | |
- select FB_MSM_MIPI_DSI | |
- default n | |
- | |
-config FB_MSM_MIPI_R63311_JDC_MDY70 | |
- bool "JDC MDY70 Panel" | |
- select FB_MSM_MIPI_DSI | |
- default n | |
- | |
-config FB_MSM_MIPI_R63311_JDC_MDY80 | |
- bool "JDC MDY80 Panel" | |
- select FB_MSM_MIPI_DSI | |
- default n | |
- | |
-config FB_MSM_MIPI_R63311_SHARP_LS050T3SX01 | |
- bool "SHARP LS050T3SX01 Panel" | |
- select FB_MSM_MIPI_DSI | |
- default n | |
- | |
-config FB_MSM_MIPI_NT71391_PANASONIC_VVX10F008B00 | |
- bool "PANASONIC VVX10F008B00 Panel" | |
- select FB_MSM_MIPI_DSI | |
- default n | |
- | |
choice | |
prompt "Secondary LCD Panel" | |
depends on FB_MSM_MDP31 | |
@@ -910,7 +862,7 @@ config FB_MSM_HDMI_MSM_PANEL | |
select FB_MSM_DTV | |
select FB_MSM_EXT_INTERFACE_COMMON | |
select FB_MSM_HDMI_COMMON | |
- select FB_MSM_HDMI_3D if !FB_MSM_MHL_SII8334 | |
+ select FB_MSM_HDMI_3D | |
default n | |
---help--- | |
Support for 480p/720p/1080i/1080p output through MSM HDMI | |
@@ -948,17 +900,6 @@ config FB_MSM_HDMI_MHL_8334 | |
MHL (Mobile High-Definition Link) technology | |
uses USB connector to output HDMI content | |
-config FB_MSM_MHL_SII8334 | |
- depends on MHL && FB_MSM_HDMI_MSM_PANEL | |
- bool "SiI8334 MHL Transmitter" | |
- default y | |
- ---help--- | |
- Support for SiI8334 MHL Transmitter | |
- | |
-config FB_MSM_RECOVER_PANEL | |
- bool "Enable Recovery" | |
- default n | |
- | |
choice | |
depends on (FB_MSM_MDP22 || FB_MSM_MDP31 || FB_MSM_MDP40) | |
prompt "TVOut Region" | |
diff --git a/drivers/video/msm/Makefile b/drivers/video/msm/Makefile | |
index 34b0036..ac9d590 100644 | |
--- a/drivers/video/msm/Makefile | |
+++ b/drivers/video/msm/Makefile | |
@@ -3,6 +3,7 @@ obj-y += mdss/ | |
else | |
obj-y := msm_fb.o | |
+obj-$(CONFIG_FB_MSM_LOGO) += logo.o | |
obj-$(CONFIG_FB_BACKLIGHT) += msm_fb_bl.o | |
ifeq ($(CONFIG_FB_MSM_MDP_HW),y) | |
@@ -83,17 +84,6 @@ obj-$(CONFIG_FB_MSM_MIPI_DSI_NT35510) += mipi_NT35510.o | |
obj-$(CONFIG_FB_MSM_MIPI_DSI_NT35516) += mipi_truly_tft540960_1_e.o | |
obj-$(CONFIG_FB_MSM_MIPI_DSI_NT35590) += mipi_NT35590.o | |
obj-$(CONFIG_FB_MSM_MIPI_DSI_SIMULATOR) += mipi_simulator.o | |
-obj-$(CONFIG_FB_MSM_MIPI_DSI) += mipi_dsi_panel_driver.o | |
-ifeq ($(CONFIG_DEBUG_FS),y) | |
-obj-$(CONFIG_FB_MSM_MIPI_DSI) += mipi_dsi_panel_debugfs.o | |
-endif | |
-obj-$(CONFIG_FB_MSM_MIPI_R63306_SHARP_LS043K3SX04) += mipi_dsi_panel_r63306_sharp_ls043k3sx04.o | |
-obj-$(CONFIG_FB_MSM_MIPI_R63311_SHARP_LS050T3SX02) += mipi_dsi_panel_r63311_sharp_ls050t3sx02.o | |
-obj-$(CONFIG_FB_MSM_MIPI_R63306_TMD_MDW30) += mipi_dsi_panel_r63306_tmd_mdw30.o | |
-obj-$(CONFIG_FB_MSM_MIPI_R63311_JDC_MDY70) += mipi_dsi_panel_r63311_jdc_mdy70.o | |
-obj-$(CONFIG_FB_MSM_MIPI_R63311_JDC_MDY80) += mipi_dsi_panel_r63311_jdc_mdy80.o | |
-obj-$(CONFIG_FB_MSM_MIPI_R63311_SHARP_LS050T3SX01) += mipi_dsi_panel_r63311_sharp_ls050t3sx01.o | |
-obj-$(CONFIG_FB_MSM_MIPI_NT71391_PANASONIC_VVX10F008B00) += mipi_dsi_panel_nt71391_panasonic_vvx10f008b00.o | |
# MIPI Bridge | |
obj-$(CONFIG_FB_MSM_MIPI_DSI_TC358764_DSI2LVDS) += mipi_tc358764_dsi2lvds.o | |
@@ -134,7 +124,6 @@ obj-y += mipi_toshiba_video_wvga_pt.o mipi_toshiba_video_wsvga_pt.o mipi_toshiba | |
obj-y += mipi_novatek_video_qhd_pt.o mipi_novatek_cmd_qhd_pt.o | |
obj-y += mipi_orise_video_720p_pt.o mipi_orise_cmd_720p_pt.o | |
obj-y += mipi_renesas_video_fwvga_pt.o mipi_renesas_cmd_fwvga_pt.o | |
-obj-y += mipi_renesas_video_sharp_ls043k3sx04_1a_pt.o | |
obj-y += mipi_NT35510_video_wvga_pt.o mipi_NT35510_cmd_wvga_pt.o | |
obj-y += mipi_truly_tft540960_1_e_video_qhd_pt.o mipi_truly_tft540960_1_e_cmd_qhd_pt.o | |
obj-y += mipi_NT35590_cmd_720p_pt.o mipi_NT35590_video_720p_pt.o | |
@@ -151,6 +140,7 @@ obj-$(CONFIG_FB_MSM_MIPI_ORISE_CMD_720P_PT) += mipi_orise_cmd_720p_pt.o | |
obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT) += mipi_novatek_cmd_qhd_pt.o | |
obj-$(CONFIG_FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT) += mipi_renesas_video_fwvga_pt.o | |
obj-$(CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT) += mipi_renesas_cmd_fwvga_pt.o | |
+obj-$(CONFIG_FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT) += mipi_renesas_video_fwvga_pt.o | |
obj-$(CONFIG_FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT) += mipi_truly_video_wvga_pt.o | |
obj-$(CONFIG_FB_MSM_MIPI_NT35510_CMD_WVGA_PT) += mipi_NT35510_cmd_wvga_pt.o | |
obj-$(CONFIG_FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT) += mipi_NT35510_video_wvga_pt.o | |
@@ -179,10 +169,9 @@ obj-$(CONFIG_FB_MSM_LCDC_AUO_WVGA) += lcdc_auo_wvga.o | |
obj-$(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) += lcdc_samsung_oled_pt.o | |
obj-$(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) += adv7520.o | |
obj-$(CONFIG_FB_MSM_LCDC_ST15_WXGA) += lcdc_st15.o | |
+obj-$(CONFIG_FB_MSM_LVDS_CHIMEI_WXGA) += lvds_chimei_wxga.o | |
obj-$(CONFIG_FB_MSM_LVDS_FRC_FHD) += lvds_frc_fhd.o | |
-obj-$(CONFIG_FB_MSM_LOGO) += logo.o | |
obj-$(CONFIG_FB_MSM_HDMI_MSM_PANEL) += hdmi_msm.o | |
-obj-$(CONFIG_FB_MSM_MHL_SII8334) += mhl_sii8334.o | |
obj-$(CONFIG_FB_MSM_EXT_INTERFACE_COMMON) += external_common.o | |
obj-$(CONFIG_FB_MSM_LCDC_TRULY_HVGA_IPS3P2335) += lcdc_truly_ips3p2335.o | |
diff --git a/drivers/video/msm/external_common.c b/drivers/video/msm/external_common.c | |
index cbc06fe..ef55d05 100644 | |
--- a/drivers/video/msm/external_common.c | |
+++ b/drivers/video/msm/external_common.c | |
@@ -1,5 +1,4 @@ | |
/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
* | |
* This program is free software; you can redistribute it and/or modify | |
* it under the terms of the GNU General Public License version 2 and | |
@@ -19,7 +18,6 @@ | |
/* #define DEBUG */ | |
#define DEV_DBG_PREFIX "EXT_COMMON: " | |
-#define EDID_DUMP | |
/* The start of the data block collection within the CEA Extension Version 3 */ | |
#define DBC_START_OFFSET 4 | |
@@ -85,15 +83,17 @@ const char edid_blk1[0x100] = { | |
#define DMA_E_BASE 0xB0000 | |
void mdp_vid_quant_set(void) | |
{ | |
- if (external_common_state->video_resolution == \ | |
- HDMI_VFRMT_640x480p60_4_3) { | |
- MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x70, 0x00FF0000); | |
- MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x74, 0x00FF0000); | |
- MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x78, 0x00FF0000); | |
- } else { | |
+ if ((external_common_state->video_resolution == \ | |
+ HDMI_VFRMT_720x480p60_4_3) || \ | |
+ (external_common_state->video_resolution == \ | |
+ HDMI_VFRMT_720x480p60_16_9)) { | |
MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x70, 0x00EB0010); | |
MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x74, 0x00EB0010); | |
MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x78, 0x00EB0010); | |
+ } else { | |
+ MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x70, 0x00FF0000); | |
+ MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x74, 0x00FF0000); | |
+ MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x78, 0x00FF0000); | |
} | |
} | |
@@ -1825,26 +1825,6 @@ static void hdmi_edid_get_display_mode(const uint8 *data_buf, | |
HDMI_VFRMT_640x480p60_4_3); | |
} | |
-#ifdef EDID_DUMP | |
-static void hdmi_common_edid_block_dump(int block, uint8 *buf) | |
-{ | |
- int ndx; | |
- | |
- DEV_INFO("EDID BLK=%d\n", block); | |
- for (ndx = 0; ndx < 0x80; ndx += 16) { | |
- DEV_INFO("%02X | %02X %02X %02X %02X %02X %02X %02X %02X " | |
- "%02X %02X %02X %02X %02X %02X %02X %02X\n", | |
- ndx, | |
- buf[ndx], buf[ndx+1], buf[ndx+2], buf[ndx+3], | |
- buf[ndx+4], buf[ndx+5], buf[ndx+6], buf[ndx+7], | |
- buf[ndx+8], buf[ndx+9], buf[ndx+10], buf[ndx+11], | |
- buf[ndx+12], buf[ndx+13], buf[ndx+14], buf[ndx+15]); | |
- } | |
-} | |
-#else | |
-static inline void hdmi_common_edid_block_dump(int block, uint8 *buf) {} | |
-#endif | |
- | |
static int hdmi_common_read_edid_block(int block, uint8 *edid_buf) | |
{ | |
uint32 ndx, check_sum, print_len; | |
@@ -1855,8 +1835,6 @@ static int hdmi_common_read_edid_block(int block, uint8 *edid_buf) | |
if (status) | |
goto error; | |
- hdmi_common_edid_block_dump(block, edid_buf); | |
- | |
/* Calculate checksum */ | |
check_sum = 0; | |
for (ndx = 0; ndx < 0x80; ++ndx) | |
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c | |
index a77d3d1..e2b0791 100644 | |
--- a/drivers/video/msm/hdmi_msm.c | |
+++ b/drivers/video/msm/hdmi_msm.c | |
@@ -1,6 +1,4 @@ | |
-/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved. | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
- * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. | |
+/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. | |
* | |
* This program is free software; you can redistribute it and/or modify | |
* it under the terms of the GNU General Public License version 2 and | |
@@ -30,10 +28,6 @@ | |
#include <mach/msm_iomap.h> | |
#include <mach/socinfo.h> | |
-#ifdef CONFIG_MHL | |
-#include <linux/mhl.h> | |
-#endif | |
- | |
#include "msm_fb.h" | |
#include "hdmi_msm.h" | |
@@ -1282,7 +1276,7 @@ static void msm_hdmi_init_ddc(void) | |
* 0x3: 3/4 of total samples */ | |
/* Configure the Pre-Scale multiplier | |
* Configure the Threshold */ | |
- HDMI_OUTP_ND(0x0220, (5 << 16) | (2 << 0)); | |
+ HDMI_OUTP_ND(0x0220, (10 << 16) | (2 << 0)); | |
/* | |
* 0x0224 HDMI_DDC_SETUP | |
@@ -1298,8 +1292,8 @@ static void msm_hdmi_init_ddc(void) | |
[15:0] REFTIMER Value to set the register in order to generate | |
DDC strobe. This register counts on HDCP application clock */ | |
/* Enable reference timer | |
- * 68 micro-seconds */ | |
- HDMI_OUTP_ND(0x027C, (1 << 16) | (68 << 0)); | |
+ * 27 micro-seconds */ | |
+ HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0)); | |
} | |
static int hdmi_msm_ddc_clear_irq(const char *what) | |
@@ -2514,8 +2508,6 @@ static int hdcp_authentication_part1(void) | |
DEV_DBG("HDCP: Link0-AKSV=%02x%08x\n", | |
link0_aksv_1 & 0xFF, link0_aksv_0); | |
- msleep(50); | |
- | |
/* Read Bksv 5 bytes at 0x00 in HDCP port */ | |
ret = hdmi_msm_ddc_read(0x74, 0x00, bksv, 5, 5, "Bksv", TRUE); | |
if (ret) { | |
@@ -3630,12 +3622,12 @@ static uint8 hdmi_msm_avi_iframe_lut[][17] = { | |
0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, /*00*/ | |
/* Data Byte 02: C1 C0 M1 M0 R3 R2 R1 R0 */ | |
{0x18, 0x18, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, | |
- 0x28, 0x28, 0x28, 0x28, 0x18, 0x28, 0x18}, /*01*/ | |
+ 0x28, 0x28, 0x28, 0x28, 0x18, 0x28, 0x18, 0x08}, /*01*/ | |
/* Data Byte 03: ITC EC2 EC1 EC0 Q1 Q0 SC1 SC0 */ | |
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*02*/ | |
+ {0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, | |
+ 0x04, 0x04, 0x04, 0x04, 0x88, 0x00, 0x04, 0x04}, /*02*/ | |
/* Data Byte 04: 0 VIC6 VIC5 VIC4 VIC3 VIC2 VIC1 VIC0 */ | |
- {0x02, 0x06, 0x11, 0x15, 0x04, 0x13, 0x10, 0x05, 0x1F, | |
+ {0x02, 0x06, 0x12, 0x15, 0x04, 0x13, 0x10, 0x05, 0x1F, | |
0x14, 0x20, 0x22, 0x21, 0x01, 0x03, 0x11, 0x00}, /*03*/ | |
/* Data Byte 05: 0 0 0 0 PR3 PR2 PR1 PR0 */ | |
{0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, | |
@@ -4161,10 +4153,8 @@ static void hdmi_msm_turn_on(void) | |
hdmi_msm_spd_infoframe_packetsetup(); | |
if (hdmi_msm_state->hdcp_enable && hdmi_msm_state->reauth) { | |
+ hdmi_msm_hdcp_enable(); | |
hdmi_msm_state->reauth = FALSE ; | |
- cancel_work_sync(&hdmi_msm_state->hdcp_reauth_work); | |
- del_timer_sync(&hdmi_msm_state->hdcp_timer); | |
- queue_work(hdmi_work_queue, &hdmi_msm_state->hdcp_work); | |
} | |
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT | |
@@ -4794,13 +4784,6 @@ static int hdmi_msm_hpd_feature(int on) | |
DEV_INFO("%s: %d\n", __func__, on); | |
if (on) { | |
rc = hdmi_msm_hpd_on(); | |
-#ifdef CONFIG_MHL | |
- /* MHL full operation start */ | |
- if (hdmi_msm_state->pd->coupled_mhl_device) | |
- mhl_full_operation( | |
- hdmi_msm_state->pd->coupled_mhl_device, | |
- TRUE); | |
-#endif | |
} else { | |
if (external_common_state->hpd_state) { | |
/* Send offline event to switch OFF HDMI and HAL FD */ | |
@@ -4820,13 +4803,6 @@ static int hdmi_msm_hpd_feature(int on) | |
switch_set_state(&external_common_state->sdev, 0); | |
DEV_INFO("%s: hdmi state switched to %d\n", __func__, | |
external_common_state->sdev.state); | |
-#ifdef CONFIG_MHL | |
- /* MHL full operation stop */ | |
- if (hdmi_msm_state->pd->coupled_mhl_device) | |
- mhl_full_operation( | |
- hdmi_msm_state->pd->coupled_mhl_device, | |
- FALSE); | |
-#endif | |
} | |
return rc; | |
@@ -4963,8 +4939,6 @@ static void __exit hdmi_msm_exit(void) | |
platform_driver_unregister(&this_driver); | |
} | |
-/* SoMC: disabled for production due to security reasons */ | |
-#if 0 | |
static int set_hdcp_feature_on(const char *val, const struct kernel_param *kp) | |
{ | |
int rv = param_set_bool(val, kp); | |
@@ -4994,7 +4968,6 @@ static struct kernel_param_ops hdcp_feature_on_param_ops = { | |
module_param_cb(hdcp, &hdcp_feature_on_param_ops, &hdcp_feature_on, | |
S_IRUGO | S_IWUSR); | |
MODULE_PARM_DESC(hdcp, "Enable or Disable HDCP"); | |
-#endif | |
module_init(hdmi_msm_init); | |
module_exit(hdmi_msm_exit); | |
diff --git a/drivers/video/msm/logo.c b/drivers/video/msm/logo.c | |
index eb78f4f..7b3cdef 100644 | |
--- a/drivers/video/msm/logo.c | |
+++ b/drivers/video/msm/logo.c | |
@@ -14,7 +14,6 @@ | |
* GNU General Public License for more details. | |
* | |
*/ | |
-#include <asm/cacheflush.h> | |
#include <linux/module.h> | |
#include <linux/types.h> | |
#include <linux/fb.h> | |
@@ -26,12 +25,8 @@ | |
#include <asm/system.h> | |
#define fb_width(fb) ((fb)->var.xres) | |
-#define fb_linewidth(fb) \ | |
- ((fb)->fix.line_length / (fb_depth(fb) == 2 ? 2 : 4)) | |
#define fb_height(fb) ((fb)->var.yres) | |
-#define fb_depth(fb) ((fb)->var.bits_per_pixel >> 3) | |
-#define fb_size(fb) (fb_width(fb) * fb_height(fb) * fb_depth(fb)) | |
-#define INIT_IMAGE_FILE "/logo.rle" | |
+#define fb_size(fb) ((fb)->var.xres * (fb)->var.yres * 2) | |
static void memset16(void *_ptr, unsigned short val, unsigned count) | |
{ | |
@@ -41,22 +36,13 @@ static void memset16(void *_ptr, unsigned short val, unsigned count) | |
*ptr++ = val; | |
} | |
-static void memset32(void *_ptr, unsigned int val, unsigned count) | |
-{ | |
- unsigned int *ptr = _ptr; | |
- count >>= 2; | |
- while (count--) | |
- *ptr++ = val; | |
-} | |
- | |
/* 565RLE image format: [count(2 bytes), rle(2 bytes)] */ | |
-int load_565rle_image(char *filename) | |
+int load_565rle_image(char *filename, bool bf_supported) | |
{ | |
struct fb_info *info; | |
- int fd, err = 0; | |
- unsigned count, max, width, stride, line_pos = 0; | |
- unsigned short *data, *ptr; | |
- unsigned char *bits; | |
+ int fd, count, err = 0; | |
+ unsigned max; | |
+ unsigned short *data, *bits, *ptr; | |
info = registered_fb[0]; | |
if (!info) { | |
@@ -87,78 +73,33 @@ int load_565rle_image(char *filename) | |
err = -EIO; | |
goto err_logo_free_data; | |
} | |
- width = fb_width(info); | |
- stride = fb_linewidth(info); | |
- max = width * fb_height(info); | |
- ptr = data; | |
- bits = (unsigned char *)(info->screen_base); | |
- while (count > 3) { | |
- int n = ptr[0]; | |
- if (n > max) | |
- break; | |
- max -= n; | |
- while (n > 0) { | |
- unsigned int j = | |
- (line_pos + n > width ? width-line_pos : n); | |
- | |
- if (fb_depth(info) == 2) | |
- memset16(bits, swab16(ptr[1]), j << 1); | |
- else { | |
- unsigned int widepixel = ptr[1]; | |
- /* | |
- * Format is RGBA, but fb is big | |
- * endian so we should make widepixel | |
- * as ABGR. | |
- */ | |
- widepixel = | |
- /* red : f800 -> 000000f8 */ | |
- (widepixel & 0xf800) >> 8 | | |
- /* green : 07e0 -> 0000fc00 */ | |
- (widepixel & 0x07e0) << 5 | | |
- /* blue : 001f -> 00f80000 */ | |
- (widepixel & 0x001f) << 19; | |
- memset32(bits, widepixel, j << 2); | |
- } | |
- bits += j * fb_depth(info); | |
- line_pos += j; | |
- n -= j; | |
- if (line_pos == width) { | |
- bits += (stride-width) * fb_depth(info); | |
- line_pos = 0; | |
- } | |
+ max = fb_width(info) * fb_height(info); | |
+ ptr = data; | |
+ if (bf_supported && (info->node == 1 || info->node == 2)) { | |
+ err = -EPERM; | |
+ pr_err("%s:%d no info->creen_base on fb%d!\n", | |
+ __func__, __LINE__, info->node); | |
+ goto err_logo_free_data; | |
+ } | |
+ if (info->screen_base) { | |
+ bits = (unsigned short *)(info->screen_base); | |
+ while (count > 3) { | |
+ unsigned n = ptr[0]; | |
+ if (n > max) | |
+ break; | |
+ memset16(bits, ptr[1], n << 1); | |
+ bits += n; | |
+ max -= n; | |
+ ptr += 2; | |
+ count -= 4; | |
} | |
- ptr += 2; | |
- count -= 4; | |
} | |
- dmac_flush_range(info->screen_base, info->screen_base + fb_size(info)); | |
err_logo_free_data: | |
kfree(data); | |
err_logo_close_file: | |
sys_close(fd); | |
- | |
return err; | |
} | |
- | |
-static void __init draw_logo(void) | |
-{ | |
- struct fb_info *fb_info; | |
- | |
- fb_info = registered_fb[0]; | |
- if (fb_info && fb_info->fbops->fb_open) { | |
- printk(KERN_INFO "Drawing logo.\n"); | |
- fb_info->fbops->fb_open(fb_info, 0); | |
- fb_info->fbops->fb_pan_display(&fb_info->var, fb_info); | |
- } | |
-} | |
- | |
-int __init logo_init(void) | |
-{ | |
- if (!load_565rle_image(INIT_IMAGE_FILE)) | |
- draw_logo(); | |
- | |
- return 0; | |
-} | |
- | |
-module_init(logo_init); | |
+EXPORT_SYMBOL(load_565rle_image); | |
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c | |
index 384afad..5e1e0d8 100644 | |
--- a/drivers/video/msm/mdp.c | |
+++ b/drivers/video/msm/mdp.c | |
@@ -44,8 +44,6 @@ | |
#endif | |
#include "mipi_dsi.h" | |
-#include <linux/msm_mdp.h> | |
- | |
uint32 mdp4_extn_disp; | |
static struct clk *mdp_clk; | |
@@ -2396,6 +2394,22 @@ static int mdp_on(struct platform_device *pdev) | |
pr_debug("%s:+\n", __func__); | |
+ if (!(mfd->cont_splash_done)) { | |
+ if (mfd->panel.type == MIPI_VIDEO_PANEL) | |
+ mdp4_dsi_video_splash_done(); | |
+ | |
+ /* Clks are enabled in probe. | |
+ Disabling clocks now */ | |
+ mdp_clk_ctrl(0); | |
+ mfd->cont_splash_done = 1; | |
+ } | |
+ | |
+ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); | |
+ | |
+ ret = panel_next_on(pdev); | |
+ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); | |
+ | |
+ | |
if (mdp_rev >= MDP_REV_40) { | |
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); | |
mdp_clk_ctrl(1); | |
@@ -2424,11 +2438,6 @@ static int mdp_on(struct platform_device *pdev) | |
atomic_set(&vsync_cntrl.suspend, 1); | |
} | |
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); | |
- | |
- ret = panel_next_on(pdev); | |
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); | |
- | |
mdp_histogram_ctrl_all(TRUE); | |
if (ret == 0) | |
@@ -2723,7 +2732,6 @@ static int mdp_probe(struct platform_device *pdev) | |
struct msm_fb_panel_data *pdata = NULL; | |
int rc; | |
resource_size_t size ; | |
- struct msm_panel_info *pinfo = NULL; | |
unsigned long flag; | |
u32 frame_rate; | |
#ifdef CONFIG_FB_MSM_MDP40 | |
@@ -2768,8 +2776,6 @@ static int mdp_probe(struct platform_device *pdev) | |
if (rc) | |
return rc; | |
- mdp_clk_ctrl(1); | |
- | |
mdp_hw_version(); | |
/* initializing mdp hw */ | |
@@ -2783,8 +2789,6 @@ static int mdp_probe(struct platform_device *pdev) | |
#ifdef CONFIG_FB_MSM_OVERLAY | |
mdp_hw_cursor_init(); | |
#endif | |
- mdp_clk_ctrl(0); | |
- | |
mdp_resource_initialized = 1; | |
return 0; | |
} | |
@@ -3191,28 +3195,6 @@ static int mdp_probe(struct platform_device *pdev) | |
/* set driver data */ | |
platform_set_drvdata(msm_fb_dev, mfd); | |
- /* panel detection */ | |
- MSM_FB_INFO("mdp_probe: panel_detect function\n"); | |
- if (pdata && pdata->panel_detect && pdata->update_panel) { | |
- rc = panel_next_on(msm_fb_dev); | |
- if (!rc) { | |
- pinfo = pdata->panel_detect(mfd); | |
- if (pdata->get_pcc_data) | |
- pdata->get_pcc_data(mfd); | |
- rc = panel_next_off(msm_fb_dev); | |
- } | |
- if (!rc && pinfo) | |
- mfd->panel_info = *pinfo; | |
- pdata->update_panel(pdev); | |
-#ifdef CONFIG_FB_MSM_MDP40 | |
- if (mfd->panel.type == MIPI_CMD_PANEL) { | |
- mipi = &mfd->panel_info.mipi; | |
- } | |
-#endif | |
- } else { | |
- MSM_FB_INFO("mdp_probe: no panel_detect function\n"); | |
- } | |
- | |
rc = platform_device_add(msm_fb_dev); | |
if (rc) { | |
goto mdp_probe_err; | |
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h | |
index 7facb9f..01cfdcc 100644 | |
--- a/drivers/video/msm/mdp4.h | |
+++ b/drivers/video/msm/mdp4.h | |
@@ -33,8 +33,8 @@ extern u32 mdp_max_clk; | |
extern u64 mdp_max_bw; | |
extern u32 mdp_bw_ab_factor; | |
extern u32 mdp_bw_ib_factor; | |
-#define MDP4_BW_AB_DEFAULT_FACTOR (115) | |
-#define MDP4_BW_IB_DEFAULT_FACTOR (205) | |
+#define MDP4_BW_AB_DEFAULT_FACTOR (115) /* 1.15 */ | |
+#define MDP4_BW_IB_DEFAULT_FACTOR (125) /* 1.25 */ | |
#define MDP_BUS_SCALE_AB_STEP (0x4000000) | |
#define MDP4_OVERLAYPROC0_BASE 0x10000 | |
@@ -794,6 +794,7 @@ int mdp4_dsi_cmd_on(struct platform_device *pdev); | |
int mdp4_dsi_cmd_off(struct platform_device *pdev); | |
int mdp4_dsi_video_off(struct platform_device *pdev); | |
int mdp4_dsi_video_on(struct platform_device *pdev); | |
+int mdp4_dsi_video_splash_done(void); | |
void mdp4_primary_vsync_dsi_video(void); | |
void mdp4_dsi_cmd_base_swap(int cndx, struct mdp4_overlay_pipe *pipe); | |
void mdp4_dsi_cmd_wait4vsync(int cndx); | |
@@ -863,6 +864,10 @@ static inline void mdp4_overlay_dsi_video_start(void) | |
{ | |
/* empty */ | |
} | |
+ | |
+static int mdp4_dsi_video_splash_done(void) | |
+{ | |
+} | |
#endif /* CONFIG_FB_MSM_MIPI_DSI */ | |
void mdp4_dsi_cmd_kickoff_ui(struct msm_fb_data_type *mfd, | |
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c | |
index c75c225..d146fda 100644 | |
--- a/drivers/video/msm/mdp4_overlay.c | |
+++ b/drivers/video/msm/mdp4_overlay.c | |
@@ -41,7 +41,6 @@ | |
#include "mdp.h" | |
#include "msm_fb.h" | |
#include "mdp4.h" | |
-#include "mipi_dsi_panel_driver.h" | |
#define VERSION_KEY_MASK 0xFFFFFF00 | |
@@ -2756,7 +2755,7 @@ static int mdp4_calc_pipe_mdp_clk(struct msm_fb_data_type *mfd, | |
* factor. Ideally this factor is passed from board file. | |
*/ | |
if (rst < pclk) { | |
- rst = ((pclk >> shift) * 30 / 20) << shift; | |
+ rst = ((pclk >> shift) * 23 / 20) << shift; | |
pr_debug("%s calculated mdp clk is less than pclk.\n", | |
__func__); | |
} | |
@@ -2942,10 +2941,10 @@ int mdp4_overlay_mdp_perf_req(struct msm_fb_data_type *mfd) | |
ib_quota_total, perf_req->mdp_ib_bw); | |
if (ab_quota_total > mdp_max_bw) | |
- pr_debug("%s: req ab bw=%llu is larger than max bw=%llu", | |
+ pr_warn("%s: req ab bw=%llu is larger than max bw=%llu", | |
__func__, ab_quota_total, mdp_max_bw); | |
if (ib_quota_total > mdp_max_bw) | |
- pr_debug("%s: req ib bw=%llu is larger than max bw=%llu", | |
+ pr_warn("%s: req ib bw=%llu is larger than max bw=%llu", | |
__func__, ib_quota_total, mdp_max_bw); | |
pr_debug("%s %d: pid %d cnt %d clk %d ov0_blt %d, ov1_blt %d\n", | |
@@ -3649,7 +3648,6 @@ int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req) | |
} | |
end: | |
- mipi_dsi_panel_fps_data_update(mfd); | |
mutex_unlock(&mfd->dma->ov_mutex); | |
return ret; | |
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c | |
index e365099..961a7c6 100644 | |
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c | |
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c | |
@@ -1,5 +1,4 @@ | |
/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. | |
- * Copyright (C) 2013 Sony Mobile Communications AB. | |
* | |
* This program is free software; you can redistribute it and/or modify | |
* it under the terms of the GNU General Public License version 2 and | |
@@ -403,9 +402,7 @@ static void mdp4_dsi_video_wait4dmap(int cndx) | |
if (atomic_read(&vctrl->suspend) > 0) | |
return; | |
- if (!wait_for_completion_timeout( | |
- &vctrl->dmap_comp, msecs_to_jiffies(100))) | |
- pr_err("%s %d TIMEOUT_\n", __func__, __LINE__); | |
+ wait_for_completion(&vctrl->dmap_comp); | |
} | |
@@ -442,9 +439,7 @@ static void mdp4_dsi_video_wait4ov(int cndx) | |
if (atomic_read(&vctrl->suspend) > 0) | |
return; | |
- if (!wait_for_completion_timeout( | |
- &vctrl->ov_comp, msecs_to_jiffies(100))) | |
- pr_err("%s %d TIMEOUT_\n", __func__, __LINE__); | |
+ wait_for_completion(&vctrl->ov_comp); | |
} | |
ssize_t mdp4_dsi_video_show_event(struct device *dev, | |
@@ -566,6 +561,19 @@ static void mdp4_dsi_video_tg_off(struct vsycn_ctrl *vctrl) | |
msleep(20); | |
} | |
+int mdp4_dsi_video_splash_done(void) | |
+{ | |
+ struct vsycn_ctrl *vctrl; | |
+ int cndx = 0; | |
+ | |
+ vctrl = &vsync_ctrl_db[cndx]; | |
+ | |
+ mdp4_dsi_video_tg_off(vctrl); | |
+ mipi_dsi_controller_cfg(0); | |
+ | |
+ return 0; | |
+} | |
+ | |
int mdp4_dsi_video_on(struct platform_device *pdev) | |
{ | |
int dsi_width; | |
@@ -668,15 +676,6 @@ int mdp4_dsi_video_on(struct platform_device *pdev) | |
atomic_set(&vctrl->suspend, 0); | |
- if (!(mfd->cont_splash_done)) { | |
- mfd->cont_splash_done = 1; | |
- mdp4_dsi_video_tg_off(vctrl); | |
- mipi_dsi_controller_cfg(0); | |
- /* Clks are enabled in probe. | |
- Disabling clocks now */ | |
- mdp_clk_ctrl(0); | |
- } | |
- | |
pipe->src_height = fbi->var.yres; | |
pipe->src_width = fbi->var.xres; | |
pipe->src_h = fbi->var.yres; | |
diff --git a/drivers/video/msm/mdp4_util.c b/drivers/video/msm/mdp4_util.c | |
index 5e53e6c..fe32e05 100644 | |
--- a/drivers/video/msm/mdp4_util.c | |
+++ b/drivers/video/msm/mdp4_util.c | |
@@ -1,6 +1,5 @@ | |
/* | |
* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved. | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
* | |
* This program is free software; you can redistribute it and/or modify | |
* it under the terms of the GNU General Public License version 2 and | |
@@ -36,7 +35,6 @@ | |
#include "mdp4.h" | |
struct mdp4_statistic mdp4_stat; | |
-struct mdp_pcc_cfg_data *pcc_cfg_ptr; | |
struct mdp_csc_cfg_data csc_cfg_matrix[CSC_MAX_BLOCKS] = { | |
{ | |
@@ -539,9 +537,6 @@ irqreturn_t mdp4_isr(int irq, void *ptr) | |
continue; | |
mgmt->mdp_is_hist_valid = FALSE; | |
} | |
- | |
- if (pcc_cfg_ptr != NULL) | |
- mdp4_pcc_cfg(pcc_cfg_ptr); | |
} | |
if (isr & INTR_EXTERNAL_INTF_UDERRUN) { | |
diff --git a/drivers/video/msm/mdp_dma.c b/drivers/video/msm/mdp_dma.c | |
index a6cd79e..ffb3257 100644 | |
--- a/drivers/video/msm/mdp_dma.c | |
+++ b/drivers/video/msm/mdp_dma.c | |
@@ -32,7 +32,6 @@ | |
#include "mdp.h" | |
#include "msm_fb.h" | |
#include "mddihost.h" | |
-#include "mipi_dsi_panel_driver.h" | |
static uint32 mdp_last_dma2_update_width; | |
static uint32 mdp_last_dma2_update_height; | |
@@ -613,10 +612,8 @@ void mdp_dma_pan_update(struct fb_info *info) | |
/* waiting for this update to complete */ | |
mfd->pan_waiting = TRUE; | |
wait_for_completion_killable(&mfd->pan_comp); | |
- } else { | |
- mipi_dsi_panel_fps_data_update(mfd); | |
+ } else | |
mfd->dma_fnc(mfd); | |
- } | |
} | |
void mdp_refresh_screen(unsigned long data) | |
diff --git a/drivers/video/msm/mhl_sii8334.c b/drivers/video/msm/mhl_sii8334.c | |
deleted file mode 100644 | |
index 08f4580..0000000 | |
--- a/drivers/video/msm/mhl_sii8334.c | |
+++ /dev/null | |
@@ -1,1359 +0,0 @@ | |
-/* | |
- * Copyright (C) 2011 Sony Ericsson Mobile Communications AB. | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
- * Copyright (C) 2011 Silicon Image Inc. | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2 and | |
- * only version 2 as published by the Free Software Foundation. | |
- * | |
- * This program is distributed in the hope that it will be useful, | |
- * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
- * GNU General Public License for more details. | |
- * | |
- */ | |
- | |
-/* #define DEBUG */ | |
- | |
-#include <linux/module.h> | |
-#include <linux/kernel.h> | |
-#include <linux/bitops.h> | |
-#include <linux/mutex.h> | |
-#include <linux/err.h> | |
-#include <linux/slab.h> | |
-#include <linux/delay.h> | |
-#include <linux/completion.h> | |
-#include <linux/sched.h> | |
- | |
-#include <linux/i2c.h> | |
-#include <linux/gpio.h> | |
- | |
-#include <linux/mhl.h> | |
-#include <linux/mhl_defs.h> | |
-#include <linux/mhl_sii8334.h> | |
- | |
-#include <linux/wakelock.h> | |
-#include <linux/workqueue.h> | |
- | |
-#ifdef DEBUG | |
-#define MHL_DEV_DBG(format, arg...) \ | |
- if (mhl_state->mhl_dev) \ | |
- dev_info(&mhl_state->mhl_dev->dev, format, ##arg) | |
-#else | |
-#define MHL_DEV_DBG(format, arg...) \ | |
- do {} while (0) | |
-#endif | |
- | |
-#define MSC_COMMAND_TIME_OUT 2050 | |
-#define CHARGER_INIT_WAIT 30 | |
-#define CHARGER_INIT_DELAYED_TIME 20 | |
-enum { | |
- POWER_STATE_D0_MHL = 0, | |
- POWER_STATE_D0_NO_MHL = 2, | |
- POWER_STATE_D3 = 3, | |
- POWER_STATE_FIRST_INIT = 0xFF, | |
-}; | |
- | |
-struct mhl_sii_state_struct { | |
- int reset; | |
- int irq; | |
- int hpd_pin_mode; | |
- int int_pin_mode; | |
- struct i2c_client client; | |
- struct mhl_device *mhl_dev; | |
- | |
- int (*low_power_mode)(int enable); | |
- int (*charging_enable)(int enable, int max_curr); | |
- | |
- unsigned int adopter_id; | |
- unsigned int device_id; | |
- | |
- int power_state; | |
- | |
- /* device discovery stuff */ | |
- int mhl_mode; | |
- int notify_plugged; | |
- struct completion rgnd_done; | |
- struct timer_list discovery_timer; | |
- | |
- /* MSC command stuff */ | |
- struct completion msc_command_done; | |
- struct work_struct timer_work; | |
-}; | |
- | |
-static struct mhl_sii_state_struct *mhl_state; | |
-static DEFINE_MUTEX(mhl_state_mutex); | |
-static DEFINE_MUTEX(mhl_hpd_tmds_mutex); | |
-static struct wake_lock mhl_wake_lock; | |
- | |
-static u8 chip_rev_id; | |
- | |
-static void mhl_sii_chip_init(void); | |
-static int mhl_sii_hpd_control(int enable); | |
- | |
-static int mhl_sii_reg_read(u8 addr, u8 off, u8 *buff, u16 len) | |
-{ | |
- int rc; | |
- struct i2c_msg msgs[2]; | |
- | |
- msgs[0].addr = addr >> 1; | |
- msgs[0].buf = &off; | |
- msgs[0].len = 1; | |
- msgs[0].flags = 0; | |
- | |
- msgs[1].addr = addr >> 1; | |
- msgs[1].buf = buff; | |
- msgs[1].len = len; | |
- msgs[1].flags = I2C_M_RD; | |
- | |
- rc = i2c_transfer(mhl_state->client.adapter, msgs, 2); | |
- if (rc < 2) { | |
- pr_err("%s: i2c_transfer failed (%d)\n", | |
- __func__, rc); | |
- goto out_reg_read; | |
- } | |
- | |
- return 0; | |
-out_reg_read: | |
- return rc; | |
-} | |
- | |
-static int mhl_sii_reg_write(u8 addr, u8 off, u8 *buff, u16 len) | |
-{ | |
- int rc; | |
- struct i2c_msg msgs[1]; | |
- u8 *buffer; | |
- | |
- buffer = kmalloc(1 + len, GFP_KERNEL); | |
- if (!buffer) | |
- return -ENOMEM; | |
- *buffer = off; | |
- memcpy(buffer + 1, buff, len); | |
- | |
- msgs[0].addr = addr >> 1; | |
- msgs[0].buf = buffer; | |
- msgs[0].len = 1 + len; | |
- msgs[0].flags = 0; | |
- | |
- rc = i2c_transfer(mhl_state->client.adapter, msgs, 1); | |
- if (rc < 1) { | |
- pr_err("%s: i2c_transfer failed (%d)\n", | |
- __func__, rc); | |
- goto out_reg_write; | |
- } | |
- | |
- kfree(buffer); | |
- return 0; | |
-out_reg_write: | |
- kfree(buffer); | |
- return rc; | |
-} | |
- | |
-static u8 mhl_sii_reg_read_byte(u8 addr, u8 off) | |
-{ | |
- u8 val; | |
- return mhl_sii_reg_read(addr, off, &val, 1) ? (u8) 0xFF : val; | |
-} | |
- | |
-static int mhl_sii_reg_write_byte(u8 addr, u8 off, u8 value) | |
-{ | |
- return mhl_sii_reg_write(addr, off, &value, 1); | |
-} | |
- | |
-#define MHL_SII_I2C_ADDR_PAGE0 0x72 /* TPI */ | |
-#define MHL_SII_I2C_ADDR_PAGE1 0x7A /* AVI */ | |
-#define MHL_SII_I2C_ADDR_PAGE2 0x92 /* Analog */ | |
-#define MHL_SII_I2C_ADDR_PAGE3 0x9A /* Ctrl */ | |
-#define MHL_SII_I2C_ADDR_RSVD 0xC0 /* RFU */ | |
-#define MHL_SII_I2C_ADDR_CBUS 0xC8 /* CBUS */ | |
- | |
-#define MHL_SII_PAGE0_REG_READ(off) \ | |
- mhl_sii_reg_read_byte(MHL_SII_I2C_ADDR_PAGE0, off) | |
-#define MHL_SII_PAGE0_REG_WRITE(off, val) \ | |
- mhl_sii_reg_write_byte(MHL_SII_I2C_ADDR_PAGE0, off, val) | |
- | |
-#define MHL_SII_PAGE1_REG_READ(off) \ | |
- mhl_sii_reg_read_byte(MHL_SII_I2C_ADDR_PAGE1, off) | |
-#define MHL_SII_PAGE1_REG_WRITE(off, val) \ | |
- mhl_sii_reg_write_byte(MHL_SII_I2C_ADDR_PAGE1, off, val) | |
- | |
-#define MHL_SII_PAGE2_REG_READ(off) \ | |
- mhl_sii_reg_read_byte(MHL_SII_I2C_ADDR_PAGE2, off) | |
-#define MHL_SII_PAGE2_REG_WRITE(off, val) \ | |
- mhl_sii_reg_write_byte(MHL_SII_I2C_ADDR_PAGE2, off, val) | |
- | |
-#define MHL_SII_PAGE3_REG_READ(off) \ | |
- mhl_sii_reg_read_byte(MHL_SII_I2C_ADDR_PAGE3, off) | |
-#define MHL_SII_PAGE3_REG_WRITE(off, val) \ | |
- mhl_sii_reg_write_byte(MHL_SII_I2C_ADDR_PAGE3, off, val) | |
- | |
-#define MHL_SII_RSVD_REG_READ(off) \ | |
- mhl_sii_reg_read_byte(MHL_SII_I2C_ADDR_RSVD, off) | |
-#define MHL_SII_RSVD_REG_WRITE(off, val) \ | |
- mhl_sii_reg_write_byte(MHL_SII_I2C_ADDR_RSVD, off, val) | |
- | |
-#define MHL_SII_CBUS_REG_READ(off) \ | |
- mhl_sii_reg_read_byte(MHL_SII_I2C_ADDR_CBUS, off) | |
-#define MHL_SII_CBUS_REG_WRITE(off, val) \ | |
- mhl_sii_reg_write_byte(MHL_SII_I2C_ADDR_CBUS, off, val) | |
- | |
-#define MSC_START_BIT_MSC_CMD (0x01 << 0) | |
-#define MSC_START_BIT_VS_CMD (0x01 << 1) | |
-#define MSC_START_BIT_READ_REG (0x01 << 2) | |
-#define MSC_START_BIT_WRITE_REG (0x01 << 3) | |
-#define MSC_START_BIT_WRITE_BURST (0x01 << 4) | |
- | |
-static int mhl_sii_send_msc_command(struct msc_command_struct *req) | |
-{ | |
- u8 start_bit = 0x00; | |
- u8 *burst_data; | |
- int timeout; | |
- int i; | |
- | |
- if (mhl_state->power_state != POWER_STATE_D0_MHL) { | |
- MHL_DEV_DBG("%s: power_state:%02x CBUS(0x0A):%02x\n", | |
- __func__, | |
- mhl_state->power_state, MHL_SII_CBUS_REG_READ(0x0A)); | |
- return -EFAULT; | |
- } | |
- | |
- if (!req) | |
- return -EFAULT; | |
- | |
- MHL_DEV_DBG("%s: command=0x%02x offset=0x%02x %02x %02x", | |
- __func__, | |
- req->command, | |
- req->offset, | |
- req->payload.data[0], | |
- req->payload.data[1]); | |
- | |
- MHL_SII_CBUS_REG_WRITE(0x13, req->offset); | |
- MHL_SII_CBUS_REG_WRITE(0x14, req->payload.data[0]); | |
- | |
- switch (req->command) { | |
- case MHL_SET_INT: | |
- case MHL_WRITE_STAT: | |
- start_bit = MSC_START_BIT_WRITE_REG; | |
- break; | |
- case MHL_READ_DEVCAP: | |
- start_bit = MSC_START_BIT_READ_REG; | |
- break; | |
- case MHL_GET_STATE: | |
- case MHL_GET_VENDOR_ID: | |
- case MHL_SET_HPD: | |
- case MHL_CLR_HPD: | |
- case MHL_GET_SC1_ERRORCODE: | |
- case MHL_GET_DDC_ERRORCODE: | |
- case MHL_GET_MSC_ERRORCODE: | |
- case MHL_GET_SC3_ERRORCODE: | |
- start_bit = MSC_START_BIT_MSC_CMD; | |
- MHL_SII_CBUS_REG_WRITE(0x13, req->command); | |
- break; | |
- case MHL_MSC_MSG: | |
- start_bit = MSC_START_BIT_VS_CMD; | |
- MHL_SII_CBUS_REG_WRITE(0x15, req->payload.data[1]); | |
- MHL_SII_CBUS_REG_WRITE(0x13, req->command); | |
- break; | |
- case MHL_WRITE_BURST: | |
- start_bit = MSC_START_BIT_WRITE_BURST; | |
- MHL_SII_CBUS_REG_WRITE(0x20, req->length - 1); | |
- if (!(req->payload.burst_data)) { | |
- pr_err("%s: burst data is null!\n", __func__); | |
- goto cbus_command_send_out; | |
- } | |
- burst_data = req->payload.burst_data; | |
- for (i = 0; i < req->length; i++, burst_data++) | |
- MHL_SII_CBUS_REG_WRITE(0xC0 + i, *burst_data); | |
- break; | |
- default: | |
- pr_err("%s: unknown command! (%02x)\n", | |
- __func__, req->command); | |
- goto cbus_command_send_out; | |
- } | |
- | |
- init_completion(&mhl_state->msc_command_done); | |
- MHL_SII_CBUS_REG_WRITE(0x12, start_bit); | |
- timeout = wait_for_completion_interruptible_timeout | |
- (&mhl_state->msc_command_done, | |
- msecs_to_jiffies(MSC_COMMAND_TIME_OUT)); | |
- if (!timeout) { | |
- pr_err("%s: cbus_command_send timed out!\n", __func__); | |
- goto cbus_command_send_out; | |
- } | |
- | |
- /* ok, call back mhl driver with return value */ | |
- switch (req->command) { | |
- case MHL_READ_DEVCAP: | |
- req->retval = MHL_SII_CBUS_REG_READ(0x16); /* devcap */ | |
- break; | |
- case MHL_MSC_MSG: | |
- /* check if MSC_MSG NACKed */ | |
- if (MHL_SII_CBUS_REG_READ(0x20) & BIT(6)) | |
- return -EAGAIN; | |
- /* FALLTHROUGH */ | |
- default: | |
- req->retval = 0; | |
- break; | |
- } | |
- mhl_msc_command_done(mhl_state->mhl_dev, req); | |
- | |
- MHL_DEV_DBG("%s: done\n", __func__); | |
- | |
- return 0; | |
-cbus_command_send_out: | |
- return -EFAULT; | |
-} | |
- | |
-static void mhl_sii_switch_power_state(int state) | |
-{ | |
- u8 regval; | |
- | |
- switch (state) { | |
- case POWER_STATE_D3: | |
- mutex_lock(&mhl_state_mutex); | |
- mhl_state->power_state = POWER_STATE_D3; | |
- mutex_unlock(&mhl_state_mutex); | |
- | |
- /* Force HPD = 0 */ | |
- mhl_sii_hpd_control(FALSE); | |
- | |
- /* Change TMDS termination to | |
- high impedance on disconnection */ | |
- MHL_SII_PAGE3_REG_WRITE(0x30, 0xD0); | |
- | |
- /* wait Tsrc:cbus_float */ | |
- msleep(50); | |
- | |
- /* Change state to D3 by clearing bit 0 SW_TPI */ | |
- regval = MHL_SII_PAGE1_REG_READ(0x3D); | |
- regval &= ~BIT(0); | |
- MHL_SII_PAGE1_REG_WRITE(0x3D, regval); | |
- | |
- MHL_DEV_DBG("mhl: power state switched to D3\n"); | |
- break; | |
- case POWER_STATE_D0_NO_MHL: | |
- mutex_lock(&mhl_state_mutex); | |
- mhl_state->power_state = POWER_STATE_D0_NO_MHL; | |
- mutex_unlock(&mhl_state_mutex); | |
- | |
- mhl_sii_chip_init(); | |
- | |
- MHL_SII_PAGE3_REG_WRITE(0x10, 0x25); | |
- regval = MHL_SII_PAGE0_REG_READ(0x1E); | |
- regval &= ~(BIT(0) | BIT(1)); | |
- MHL_SII_PAGE0_REG_WRITE(0x1E, regval); | |
- | |
- MHL_DEV_DBG("mhl: power state switched to D0\n"); | |
- break; | |
- default: | |
- pr_err("mhl: invalid power state! (%d)\n", state); | |
- break; | |
- } | |
-} | |
- | |
-static void mhl_sii_int1_isr(void) | |
-{ | |
- u8 regval; | |
- regval = MHL_SII_PAGE0_REG_READ(0x71); | |
- if (regval) { | |
- /* Clear all interrupts coming from this register. */ | |
- MHL_SII_PAGE0_REG_WRITE(0x71, regval); | |
- if (regval & BIT(6)) { | |
- regval = MHL_SII_CBUS_REG_READ(0x0D); | |
- mhl_notify_hpd(mhl_state->mhl_dev, | |
- !!(regval & BIT(6))); | |
- } | |
- } | |
-} | |
- | |
-static void mhl_sii_scdt_status_change(void) | |
-{ | |
- u8 regval = MHL_SII_PAGE3_REG_READ(0x40); | |
- MHL_DEV_DBG("MHL: scdt status (0x%02x)\n", regval); | |
- if (regval & 0x02) { | |
- u8 fifo_status = MHL_SII_PAGE3_REG_READ(0x23); | |
- MHL_DEV_DBG("MHL: MHL FIFO status = 0x%02x\n", fifo_status); | |
- if (fifo_status & 0x0C) { | |
- MHL_SII_PAGE3_REG_WRITE(0x23, 0x0C); | |
- MHL_DEV_DBG("MHL: MHL FIFO reset!\n"); | |
- MHL_SII_PAGE3_REG_WRITE(0x00, 0x94); | |
- MHL_SII_PAGE3_REG_WRITE(0x00, 0x84); | |
- } | |
- } | |
-} | |
- | |
-static int mhl_sii_rgnd(void) | |
-{ | |
- int ret; | |
- int counter; | |
- u8 regval = MHL_SII_PAGE3_REG_READ(0x1C) & (BIT(1) | BIT(0)); | |
- /* 00, 01 or 11 means USB. */ | |
- /* 10 means 1K impedance (MHL) */ | |
- mutex_lock(&mhl_state_mutex); | |
- if (regval == 0x02) { | |
- if (timer_pending(&mhl_state->discovery_timer)) | |
- del_timer(&mhl_state->discovery_timer); | |
- mhl_state->mhl_mode = TRUE; | |
- mhl_state->notify_plugged = TRUE; | |
- wake_lock(&mhl_wake_lock); | |
- mutex_unlock(&mhl_state_mutex); | |
- mhl_notify_plugged(mhl_state->mhl_dev); | |
- if (mhl_state->charging_enable) { | |
- /* 700 means 700mA charging ready */ | |
- ret = mhl_state->charging_enable(TRUE, 700); | |
- if (ret) { | |
- /* We used late_initcall before for | |
- * charger_enable(). Still, call of | |
- * charger_enable() is some fail. | |
- * Waits here until initialization success it. | |
- */ | |
- counter = CHARGER_INIT_WAIT; | |
- while (ret && counter--) { | |
- msleep(CHARGER_INIT_DELAYED_TIME); | |
- ret = mhl_state->charging_enable | |
- (TRUE, 700); | |
- } | |
- } | |
- } | |
- pr_info("mhl: MHL detected\n"); | |
- complete_all(&mhl_state->rgnd_done); | |
- } else { | |
- wake_unlock(&mhl_wake_lock); | |
- mhl_state->mhl_mode = FALSE; | |
- mutex_unlock(&mhl_state_mutex); | |
- pr_info("mhl: USB detected\n"); | |
- complete_all(&mhl_state->rgnd_done); | |
- } | |
- return mhl_state->mhl_mode ? | |
- MHL_DISCOVERY_RESULT_MHL : MHL_DISCOVERY_RESULT_USB; | |
-} | |
- | |
-static void mhl_sii_connection(void) | |
-{ | |
- u8 regval; | |
- | |
- mutex_lock(&mhl_state_mutex); | |
- if (mhl_state->power_state == POWER_STATE_D0_MHL) { | |
- mutex_unlock(&mhl_state_mutex); | |
- return; | |
- } | |
- mhl_state->power_state = POWER_STATE_D0_MHL; | |
- mutex_unlock(&mhl_state_mutex); | |
- | |
- MHL_SII_PAGE3_REG_WRITE(0x30, 0x10); | |
- | |
- MHL_SII_CBUS_REG_WRITE(0x07, 0xF2); | |
- | |
- /* Keep the discovery enabled. Need RGND interrupt */ | |
- regval = MHL_SII_PAGE3_REG_READ(0x10); | |
- MHL_SII_PAGE3_REG_WRITE(0x10, regval | BIT(0)); | |
- | |
- mhl_notify_online(mhl_state->mhl_dev); | |
-} | |
- | |
-static void mhl_sii_disconnection(void) | |
-{ | |
- MHL_SII_PAGE3_REG_WRITE(0x30, 0xD0); | |
- | |
- /* Force HPD = 0 */ | |
- mhl_sii_hpd_control(FALSE); | |
- | |
- /* switch power state to D3 */ | |
- mhl_sii_switch_power_state(POWER_STATE_D3); | |
- | |
- mhl_notify_offline(mhl_state->mhl_dev); | |
-} | |
- | |
-static void mhl_sii_force_usbidswitch_open(void) | |
-{ | |
- u8 regval; | |
- | |
- /* Disable discovery */ | |
- MHL_SII_PAGE3_REG_WRITE(0x10, 0x26); | |
- | |
- /* Force USB ID switch to open */ | |
- regval = MHL_SII_PAGE3_REG_READ(0x15); | |
- MHL_SII_PAGE3_REG_WRITE(0x15, regval | BIT(6)); | |
- | |
- MHL_SII_PAGE3_REG_WRITE(0x12, 0x86); | |
-} | |
- | |
-static void mhl_sii_release_usbidswitch_open(void) | |
-{ | |
- u8 regval; | |
- | |
- msleep(50); | |
- | |
- regval = MHL_SII_PAGE3_REG_READ(0x15); | |
- regval &= ~(BIT(6)); | |
- MHL_SII_PAGE3_REG_WRITE(0x15, regval); | |
- | |
- /* Enable discovery */ | |
- regval = MHL_SII_PAGE3_REG_READ(0x10); | |
- MHL_SII_PAGE3_REG_WRITE(0x10, regval | BIT(0)); | |
-} | |
- | |
-static void mhl_discovery_timer_work(struct work_struct *w) | |
-{ | |
- mutex_lock(&mhl_state_mutex); | |
- if (mhl_state->notify_plugged) { | |
- mhl_notify_unplugged(mhl_state->mhl_dev); | |
- wake_unlock(&mhl_wake_lock); | |
- if (mhl_state->charging_enable) | |
- mhl_state->charging_enable(FALSE, 0); | |
- del_timer(&mhl_state->discovery_timer); | |
- mhl_state->notify_plugged = FALSE; | |
- } | |
- mutex_unlock(&mhl_state_mutex); | |
-} | |
- | |
-static void mhl_discovery_timer(unsigned long data) | |
-{ | |
- schedule_work(&mhl_state->timer_work); | |
-} | |
- | |
-static void mhl_sii_int4_isr(void) | |
-{ | |
- u8 regval = MHL_SII_PAGE3_REG_READ(0x21); | |
- if (regval != 0xFF && regval != 0x00) { | |
- MHL_DEV_DBG("%s: %02x\n", __func__, regval); | |
- /* SCDT_CHANGE */ | |
- if (regval & BIT(0)) | |
- if (chip_rev_id < 1) | |
- mhl_sii_scdt_status_change(); | |
- /* RPWR5V_CHANGE */ | |
- if (regval & BIT(1)) | |
- MHL_DEV_DBG("mhl: 5V status changed\n"); | |
- /* MHL_EST */ | |
- if (regval & BIT(2)) { | |
- /* MHL device detected */ | |
- wake_lock(&mhl_wake_lock); | |
- mhl_sii_connection(); | |
- } | |
- /* MHL_DISCOVERY_FAIL */ | |
- if (regval & BIT(3)) { | |
- /* USB SLAVE device detected */ | |
- mod_timer(&mhl_state->discovery_timer, | |
- jiffies + 4*HZ/10); | |
- /* re-enter power state to D3 */ | |
- MHL_SII_PAGE3_REG_WRITE(0x21, regval); | |
- mhl_sii_switch_power_state | |
- (POWER_STATE_D3); | |
- return; | |
- } | |
- /* VBUS_LOW */ | |
- if (regval & BIT(5)) { | |
- mod_timer(&mhl_state->discovery_timer, | |
- jiffies + 4*HZ/10); | |
- mutex_lock(&mhl_state_mutex); | |
- mhl_state->mhl_mode = FALSE; | |
- mutex_unlock(&mhl_state_mutex); | |
- MHL_SII_PAGE3_REG_WRITE(0x21, regval); | |
- mhl_sii_disconnection(); | |
- wake_unlock(&mhl_wake_lock); | |
- return; | |
- } | |
- /* R_ID_DONE */ | |
- if (regval & BIT(6)) { | |
- mutex_lock(&mhl_state_mutex); | |
- if (mhl_state->power_state == POWER_STATE_D3) { | |
- mutex_unlock(&mhl_state_mutex); | |
- mhl_sii_switch_power_state | |
- (POWER_STATE_D0_NO_MHL); | |
- if (mhl_sii_rgnd() | |
- == MHL_DISCOVERY_RESULT_USB) { | |
- /* Exit D3 via CBUS falling edge */; | |
- MHL_SII_PAGE3_REG_WRITE(0x1C, 0x80); | |
- /* USB SLAVE device detected */ | |
- /* re-enter power state to D3 */ | |
- MHL_SII_PAGE3_REG_WRITE(0x21, regval); | |
- mhl_sii_switch_power_state | |
- (POWER_STATE_D3); | |
- return; | |
- } | |
- } else | |
- mutex_unlock(&mhl_state_mutex); | |
- } | |
- /* CBUS_LKOUT */ | |
- if (regval & BIT(4)) { | |
- mutex_lock(&mhl_state_mutex); | |
- if (mhl_state->power_state != POWER_STATE_D3) { | |
- mutex_unlock(&mhl_state_mutex); | |
- mhl_sii_force_usbidswitch_open(); | |
- mhl_sii_release_usbidswitch_open(); | |
- } else | |
- mutex_unlock(&mhl_state_mutex); | |
- } | |
- } | |
- /* clear all interrupts */ | |
- MHL_SII_PAGE3_REG_WRITE(0x21, regval); | |
-} | |
- | |
-static void mhl_sii_int5_isr(void) | |
-{ | |
- u8 regval = MHL_SII_PAGE3_REG_READ(0x23); | |
- MHL_SII_PAGE3_REG_WRITE(0x23, regval); | |
-} | |
- | |
-static void mhl_sii_cbus_process_errors(u8 int_status) | |
-{ | |
- u8 abort_reason = 0; | |
- if (int_status & BIT(2)) { | |
- abort_reason = MHL_SII_CBUS_REG_READ(0x0B); | |
- MHL_DEV_DBG("%s: CBUS DDC Abort Reason(0x%02x)\n", | |
- __func__, abort_reason); | |
- } | |
- if (int_status & BIT(5)) { | |
- abort_reason = MHL_SII_CBUS_REG_READ(0x0D); | |
- MHL_DEV_DBG("%s: CBUS MSC Requestor Abort Reason(0x%02x)\n", | |
- __func__, abort_reason); | |
- MHL_SII_CBUS_REG_WRITE(0x0D, 0xFF); | |
- } | |
- if (int_status & BIT(6)) { | |
- abort_reason = MHL_SII_CBUS_REG_READ(0x0E); | |
- MHL_DEV_DBG("%s: CBUS MSC Responder Abort Reason(0x%02x)\n", | |
- __func__, abort_reason); | |
- MHL_SII_CBUS_REG_WRITE(0x0E, 0xFF); | |
- } | |
-} | |
- | |
-static void mhl_sii_cbus_isr(void) | |
-{ | |
- u8 regval; | |
- int req_done = FALSE; | |
- u8 sub_cmd; | |
- u8 cmd_data; | |
- int msc_msg_recved = FALSE; | |
- int rc; | |
- | |
- regval = MHL_SII_CBUS_REG_READ(0x08); | |
- if (regval == 0xff) | |
- return; | |
- | |
- /* clear all interrupts that were raised even if we did not process */ | |
- if (regval) | |
- MHL_SII_CBUS_REG_WRITE(0x08, regval); | |
- | |
- MHL_DEV_DBG("%s: CBUS_INT = %02x\n", __func__, regval); | |
- | |
- /* MSC_MSG (RCP/RAP) */ | |
- if (regval & BIT(3)) { | |
- sub_cmd = MHL_SII_CBUS_REG_READ(0x18); | |
- cmd_data = MHL_SII_CBUS_REG_READ(0x19); | |
- msc_msg_recved = TRUE; | |
- } | |
- | |
- /* MSC_MT_ABRT/MSC_MR_ABRT/DDC_ABORT */ | |
- if (regval & (BIT(6) | BIT(5) | BIT(2))) | |
- mhl_sii_cbus_process_errors(regval); | |
- | |
- /* MSC_REQ_DONE */ | |
- if (regval & BIT(4)) | |
- req_done = TRUE; | |
- | |
- /* Now look for interrupts on CBUS_MSC_INT2 */ | |
- regval = MHL_SII_CBUS_REG_READ(0x1E); | |
- | |
- /* clear all interrupts that were raised */ | |
- /* even if we did not process */ | |
- if (regval) | |
- MHL_SII_CBUS_REG_WRITE(0x1E, regval); | |
- | |
- MHL_DEV_DBG("%s: CBUS_MSC_INT2 = %02x\n", __func__, regval); | |
- | |
- /* received SET_INT */ | |
- if (regval & BIT(2)) { | |
- u8 intr; | |
- | |
- intr = MHL_SII_CBUS_REG_READ(0xA0); | |
- MHL_SII_CBUS_REG_WRITE(0xA0, intr); | |
- MHL_DEV_DBG("%s: MHL_INT_0 = %02x\n", __func__, intr); | |
- mhl_msc_recv_set_int(mhl_state->mhl_dev, 0, intr); | |
- | |
- intr = MHL_SII_CBUS_REG_READ(0xA1); | |
- MHL_SII_CBUS_REG_WRITE(0xA1, intr); | |
- MHL_DEV_DBG("%s: MHL_INT_1 = %02x\n", __func__, intr); | |
- mhl_msc_recv_set_int(mhl_state->mhl_dev, 1, intr); | |
- } | |
- | |
- /* received WRITE_STAT */ | |
- if (regval & BIT(3)) { | |
- u8 stat; | |
- | |
- stat = MHL_SII_CBUS_REG_READ(0xB0); | |
- MHL_DEV_DBG("%s: MHL_STATUS_0 = %02x\n", __func__, stat); | |
- if (stat ^ mhl_state->mhl_dev->state.device_status[0]) | |
- mhl_msc_recv_write_stat(mhl_state->mhl_dev, 0, stat); | |
- | |
- stat = MHL_SII_CBUS_REG_READ(0xB1); | |
- MHL_DEV_DBG("%s: MHL_STATUS_1 = %02x\n", __func__, stat); | |
- if (stat ^ mhl_state->mhl_dev->state.device_status[1]) | |
- mhl_msc_recv_write_stat(mhl_state->mhl_dev, 1, stat); | |
- | |
- MHL_SII_CBUS_REG_WRITE(0xB0, 0xFF); | |
- MHL_SII_CBUS_REG_WRITE(0xB1, 0xFF); | |
- MHL_SII_CBUS_REG_WRITE(0xB2, 0xFF); | |
- MHL_SII_CBUS_REG_WRITE(0xB3, 0xFF); | |
- } | |
- | |
- /* received MSC_MSG */ | |
- if (msc_msg_recved) { | |
- rc = mhl_msc_recv_msc_msg(mhl_state->mhl_dev, | |
- sub_cmd, cmd_data); | |
- if (rc) | |
- pr_err("MHL: mhl_msc_recv_msc_msg failed(%d)!\n", rc); | |
- } | |
- | |
- /* complete last command */ | |
- if (req_done) | |
- complete_all(&mhl_state->msc_command_done); | |
-} | |
- | |
- | |
-static irqreturn_t mhl_sii_isr(int irq, void *dev_id) | |
-{ | |
- mhl_sii_int4_isr(); | |
- mutex_lock(&mhl_state_mutex); | |
- switch (mhl_state->power_state) { | |
- case POWER_STATE_D0_MHL: | |
- mutex_unlock(&mhl_state_mutex); | |
- mhl_sii_int5_isr(); | |
- mhl_sii_cbus_isr(); | |
- mhl_sii_int1_isr(); | |
- break; | |
- case POWER_STATE_D0_NO_MHL: | |
- mutex_unlock(&mhl_state_mutex); | |
- break; | |
- case POWER_STATE_D3: | |
- mutex_unlock(&mhl_state_mutex); | |
- break; | |
- default: | |
- mutex_unlock(&mhl_state_mutex); | |
- pr_err("MHL: got interrupt in invalid state!\n"); | |
- break; | |
- } | |
- | |
- return IRQ_HANDLED; | |
-} | |
- | |
-static int mhl_sii_charging_control(int enable, int max_curr) | |
-{ | |
- u8 regval; | |
- | |
- if (mhl_state->power_state != POWER_STATE_D0_MHL) { | |
- MHL_DEV_DBG("%s: power_state:%02x\n", | |
- __func__, mhl_state->power_state); | |
- return -EFAULT; | |
- } | |
- | |
- if (enable) { | |
- regval = MHL_SII_PAGE3_REG_READ(0x17); | |
- MHL_SII_PAGE3_REG_WRITE | |
- (0x17, regval | 0x04); | |
- if (mhl_state->charging_enable) | |
- mhl_state->charging_enable(TRUE, max_curr); | |
- } else { | |
- if (mhl_state->charging_enable) | |
- mhl_state->charging_enable(FALSE, max_curr); | |
- } | |
- return 0; | |
-} | |
- | |
-static int mhl_sii_hpd_control(int enable) | |
-{ | |
- u8 regval; | |
- | |
- if (mhl_state->power_state != POWER_STATE_D0_MHL) { | |
- MHL_DEV_DBG("%s: power_state:%02x\n", | |
- __func__, mhl_state->power_state); | |
- return -EFAULT; | |
- } | |
- | |
- if (enable) { | |
- mutex_lock(&mhl_hpd_tmds_mutex); | |
- /* disable HPD out override */ | |
- regval = MHL_SII_PAGE3_REG_READ(0x20); | |
- regval &= ~BIT(4); | |
- MHL_SII_PAGE3_REG_WRITE(0x20, regval); | |
- mutex_unlock(&mhl_hpd_tmds_mutex); | |
- MHL_DEV_DBG("%s: enabled\n", __func__); | |
- | |
- /* check HPD status */ | |
- regval = MHL_SII_CBUS_REG_READ(0x0D); | |
- if (regval & BIT(6)) | |
- mhl_notify_hpd(mhl_state->mhl_dev, TRUE); | |
- } else { | |
- mutex_lock(&mhl_hpd_tmds_mutex); | |
- /* enable HPD out override */ | |
- regval = MHL_SII_PAGE3_REG_READ(0x20); | |
- regval &= ~(BIT(4) | BIT(5)); | |
- MHL_SII_PAGE3_REG_WRITE(0x20, regval | BIT(4)); | |
- mutex_unlock(&mhl_hpd_tmds_mutex); | |
- MHL_DEV_DBG("%s: disabled\n", __func__); | |
- mhl_notify_hpd(mhl_state->mhl_dev, FALSE); | |
- } | |
- return 0; | |
-} | |
- | |
-static int mhl_sii_tmds_control(int enable) | |
-{ | |
- u8 regval; | |
- | |
- if (mhl_state->power_state != POWER_STATE_D0_MHL) { | |
- MHL_DEV_DBG("%s: power_state:%02x\n", | |
- __func__, mhl_state->power_state); | |
- return -EFAULT; | |
- } | |
- | |
- if (enable) { | |
- mutex_lock(&mhl_hpd_tmds_mutex); | |
- regval = MHL_SII_PAGE0_REG_READ(0x80); | |
- MHL_SII_PAGE0_REG_WRITE(0x80, regval | BIT(4)); | |
- mutex_unlock(&mhl_hpd_tmds_mutex); | |
- MHL_DEV_DBG("%s: enabled\n", __func__); | |
- | |
- mhl_sii_hpd_control(TRUE); | |
- } else { | |
- mutex_lock(&mhl_hpd_tmds_mutex); | |
- regval = MHL_SII_PAGE0_REG_READ(0x80); | |
- regval &= ~BIT(4); | |
- MHL_SII_PAGE0_REG_WRITE(0x80, regval); | |
- mutex_unlock(&mhl_hpd_tmds_mutex); | |
- MHL_DEV_DBG("%s: disabled\n", __func__); | |
- } | |
- return 0; | |
-} | |
- | |
-static int mhl_sii_device_reset(int enable) | |
-{ | |
- if (!mhl_state->reset) | |
- return -EFAULT; | |
- | |
- if (enable) { | |
- gpio_set_value(mhl_state->reset, 0); | |
- usleep_range(10000, 100000); | |
- gpio_set_value(mhl_state->reset, 1); | |
- } else | |
- gpio_set_value(mhl_state->reset, 0); | |
- | |
- msleep(100); | |
- | |
- return 0; | |
-} | |
- | |
-static void mhl_sii_cbus_reset(void) | |
-{ | |
- int index = 0; | |
- u8 regval = MHL_SII_PAGE3_REG_READ(0x00); | |
- regval &= ~BIT(3); | |
- MHL_SII_PAGE3_REG_WRITE(0x00, regval | BIT(3)); | |
- usleep_range(2000, 5000); | |
- MHL_SII_PAGE3_REG_WRITE(0x00, regval); | |
- | |
- /* unmask interrupts */ | |
- /* INTR1_MASK */ | |
- MHL_SII_PAGE0_REG_WRITE | |
- (0x75, (BIT(6) | BIT(5))); | |
- /* INTR4_MASK */ | |
- MHL_SII_PAGE3_REG_WRITE | |
- (0x22, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0))); | |
- /* INTR5_MASK */ | |
- if (chip_rev_id < 1) { | |
- MHL_SII_PAGE3_REG_WRITE | |
- (0x24, (BIT(4) | BIT(3))); | |
- } else { | |
- MHL_SII_PAGE3_REG_WRITE(0x24, 0x00); | |
- } | |
- /* CBUS_INTR_ENABLE */ | |
- MHL_SII_CBUS_REG_WRITE | |
- (0x09, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); | |
- /* CBUS_MSC_INT2_ENABLE */ | |
- MHL_SII_CBUS_REG_WRITE | |
- (0x1F, (BIT(3) | BIT(2))); | |
- | |
- while (index < 4) { | |
- /* Enable WRITE_STAT interrupt for */ | |
- /* writes to all 4 MSC Status registers. */ | |
- MHL_SII_CBUS_REG_WRITE((0xE0 + index), 0xFF); | |
- /* Enable SET_INT interrupt for */ | |
- /* writes to all 4 MSC Interrupt registers. */ | |
- MHL_SII_CBUS_REG_WRITE((0xF0 + index), 0xFF); | |
- index++; | |
- } | |
-} | |
- | |
-static void mhl_sii_cbus_init(void) | |
-{ | |
- u8 regval; | |
- | |
- /* Increase DDC translation layer timer */ | |
- MHL_SII_CBUS_REG_WRITE(0x07, 0xF2); | |
- /* Drive High Time */ | |
- MHL_SII_CBUS_REG_WRITE(0x36, 0x0B); | |
- /* Use programmed timing */ | |
- MHL_SII_CBUS_REG_WRITE(0x39, 0x30); | |
- /* CBUS Drive Strength */ | |
- MHL_SII_CBUS_REG_WRITE(0x40, 0x03); | |
- | |
- /* Setup SiI8334 devcap */ | |
- MHL_SII_CBUS_REG_WRITE(0x80, MHL_DEV_ACTIVE); | |
- MHL_SII_CBUS_REG_WRITE(0x81, MHL_VERSION); | |
- MHL_SII_CBUS_REG_WRITE(0x82, MHL_DEV_CAT_SOURCE); | |
- MHL_SII_CBUS_REG_WRITE(0x83, (mhl_state->adopter_id >> 8) & 0xFF); | |
- MHL_SII_CBUS_REG_WRITE(0x84, (mhl_state->adopter_id & 0xFF)); | |
- MHL_SII_CBUS_REG_WRITE(0x85, (MHL_DEV_VID_LINK_SUPPRGB444 | \ | |
- MHL_DEV_VID_LINK_SUPP_ISLANDS)); | |
- MHL_SII_CBUS_REG_WRITE(0x86, MHL_DEV_AUD_LINK_2CH); | |
- MHL_SII_CBUS_REG_WRITE(0x87, 0); | |
- MHL_SII_CBUS_REG_WRITE(0x88, MHL_DEV_LD_GUI); | |
- MHL_SII_CBUS_REG_WRITE(0x89, 0); | |
- MHL_SII_CBUS_REG_WRITE(0x8A, (MHL_FEATURE_RCP_SUPPORT | \ | |
- MHL_FEATURE_RAP_SUPPORT | \ | |
- MHL_FEATURE_SP_SUPPORT)); | |
- MHL_SII_CBUS_REG_WRITE(0x8B, (mhl_state->device_id >> 8) & 0xFF); | |
- MHL_SII_CBUS_REG_WRITE(0x8C, (mhl_state->device_id & 0xFF)); | |
- MHL_SII_CBUS_REG_WRITE(0x8D, MHL_SCRATCHPAD_SIZE); | |
- MHL_SII_CBUS_REG_WRITE(0x8E, MHL_INT_AND_STATUS_SIZE); | |
- MHL_SII_CBUS_REG_WRITE(0x8F, 0); | |
- | |
- /* Make bits 2,3 (initiator timeout) to 1,1 */ | |
- /* for CBUS_LINK_CONTROL_2 */ | |
- regval = MHL_SII_CBUS_REG_READ(0x31); | |
- MHL_SII_CBUS_REG_WRITE(0x31, (regval | 0x0C)); | |
- | |
- /* Clear legacy bit on Wolverine TX. */ | |
- MHL_SII_CBUS_REG_WRITE(0x22, 0x0F); | |
- | |
- /* Set NMax to 1 */ | |
- MHL_SII_CBUS_REG_WRITE(0x30, 0x01); | |
- | |
- /* disallow vendor specific commands */ | |
- regval = MHL_SII_CBUS_REG_READ(0x2E); | |
- MHL_SII_CBUS_REG_WRITE(0x2E, regval | BIT(4)); | |
-} | |
- | |
-static void mhl_sii_chip_init(void) | |
-{ | |
- u8 regval; | |
- | |
- /* Power up CVCC 1.2V core */ | |
- MHL_SII_PAGE1_REG_WRITE(0x3D, 0x3F); | |
- /* Enable TxPLL Clock */ | |
- MHL_SII_PAGE2_REG_WRITE(0x11, 0x01); | |
- /* Enable Tx Clock Path & Equalizer */ | |
- MHL_SII_PAGE2_REG_WRITE(0x12, 0x11); | |
- | |
- /* TX Source termination ON */ | |
- MHL_SII_PAGE3_REG_WRITE(0x30, 0x10); | |
- /* Enable 1X MHL clock output */ | |
- MHL_SII_PAGE3_REG_WRITE(0x35, 0xBC); | |
- /* TX Differential Driver Config */ | |
- MHL_SII_PAGE3_REG_WRITE(0x31, 0x3C); | |
- MHL_SII_PAGE3_REG_WRITE(0x33, 0xC8); | |
- | |
- MHL_SII_PAGE3_REG_WRITE(0x36, 0x03); | |
- /* PLL bias current, PLL BW Control */ | |
- MHL_SII_PAGE3_REG_WRITE(0x37, 0x0A); | |
- | |
- /* Analog PLL Control */ | |
- /* Enable Rx PLL clock */ | |
- MHL_SII_PAGE0_REG_WRITE(0x80, 0x08); | |
- /* USB charge pump clock */ | |
- MHL_SII_PAGE0_REG_WRITE(0xF8, 0x8C); | |
- MHL_SII_PAGE0_REG_WRITE(0x85, 0x02); | |
- | |
- MHL_SII_PAGE2_REG_WRITE(0x00, 0x00); | |
- regval = MHL_SII_PAGE2_REG_READ(0x05); | |
- regval &= ~BIT(5); | |
- MHL_SII_PAGE2_REG_WRITE(0x05, regval); | |
- MHL_SII_PAGE2_REG_WRITE(0x13, 0x60); | |
- | |
- /* PLL Calrefsel */ | |
- MHL_SII_PAGE2_REG_WRITE(0x17, 0x03); | |
- /* VCO Cal */ | |
- MHL_SII_PAGE2_REG_WRITE(0x1A, 0x20); | |
- MHL_SII_PAGE2_REG_WRITE(0x22, 0xE0); | |
- MHL_SII_PAGE2_REG_WRITE(0x23, 0xC0); | |
- MHL_SII_PAGE2_REG_WRITE(0x24, 0xA0); | |
- MHL_SII_PAGE2_REG_WRITE(0x25, 0x80); | |
- MHL_SII_PAGE2_REG_WRITE(0x26, 0x60); | |
- MHL_SII_PAGE2_REG_WRITE(0x27, 0x40); | |
- MHL_SII_PAGE2_REG_WRITE(0x28, 0x20); | |
- MHL_SII_PAGE2_REG_WRITE(0x29, 0x00); | |
- | |
- /* Rx PLL BW ~ 4MHz */ | |
- MHL_SII_PAGE2_REG_WRITE(0x31, 0x0A); | |
- /* Rx PLL BW value from I2C */ | |
- MHL_SII_PAGE2_REG_WRITE(0x45, 0x06); | |
- MHL_SII_PAGE2_REG_WRITE(0x4B, 0x06); | |
- /* Manual zone control */ | |
- MHL_SII_PAGE2_REG_WRITE(0x4C, 0x60); | |
- /* Manual zone control */ | |
- MHL_SII_PAGE2_REG_WRITE(0x4C, 0xE0); | |
- /* PLL Mode Value */ | |
- MHL_SII_PAGE2_REG_WRITE(0x4D, 0x00); | |
- | |
- /* bring out from power down (script moved this here from above) */ | |
- MHL_SII_PAGE0_REG_WRITE(0x08, 0x35); | |
- | |
- MHL_SII_PAGE3_REG_WRITE(0x11, 0xAD); | |
- /* 1.8V CBUS VTH 5K pullup for MHL state */ | |
- MHL_SII_PAGE3_REG_WRITE(0x14, 0x57); | |
- /* RGND & single discovery attempt (RGND blocking) */ | |
- MHL_SII_PAGE3_REG_WRITE(0x15, 0x11); | |
- /* Ignore VBUS */ | |
- MHL_SII_PAGE3_REG_WRITE(0x17, 0x82); | |
-#ifndef CONFIG_MHL_SII8334_WAKE_PLUSE_DISABLE | |
- /* No OTG, Discovery pulse proceed, Wake pulse not bypassed */ | |
- MHL_SII_PAGE3_REG_WRITE(0x18, 0x24); | |
-#else | |
- /* No OTG, Discovery pulse proceed, Wake pulse bypassed */ | |
- MHL_SII_PAGE3_REG_WRITE(0x18, 0x26); | |
-#endif | |
- /* Pull-up resistance off for IDLE state and 10K for discovery state. */ | |
- MHL_SII_PAGE3_REG_WRITE(0x13, 0x8C); | |
- /* Enable CBUS discovery */ | |
- MHL_SII_PAGE3_REG_WRITE(0x10, 0x27); | |
- /* use 1K only setting */ | |
- MHL_SII_PAGE3_REG_WRITE(0x16, 0x20); | |
- /* MHL CBUS discovery */ | |
- MHL_SII_PAGE3_REG_WRITE(0x12, 0x86); | |
- | |
- /* setup int signal mode */ | |
- regval = MHL_SII_PAGE3_REG_READ(0x20); | |
- regval &= ~(BIT(6) | BIT(1) | BIT(2)); | |
- mutex_lock(&mhl_state_mutex); | |
- if (mhl_state->hpd_pin_mode & 0xF0) | |
- regval |= BIT(6); | |
- if (mhl_state->int_pin_mode & 0xF0) | |
- regval |= BIT(2); | |
- if (mhl_state->int_pin_mode & 0x0F) | |
- regval |= BIT(1); | |
- mutex_unlock(&mhl_state_mutex); | |
- MHL_SII_PAGE3_REG_WRITE(0x20, regval); | |
- MHL_DEV_DBG("%s: configured HPD mode as %s\n", | |
- __func__, | |
- (regval & BIT(6)) ? "opendrain" : "push-pull"); | |
- MHL_DEV_DBG("%s: configured INT mode as %s, active %s\n", | |
- __func__, | |
- (regval & BIT(2)) ? "opendrain" : "push-pull", | |
- (regval & BIT(1)) ? "low" : "hi"); | |
- | |
- /* Force HPD = 0 when not in MHL mode. */ | |
- mutex_lock(&mhl_state_mutex); | |
- if (mhl_state->power_state != POWER_STATE_D0_MHL) { | |
- mutex_unlock(&mhl_state_mutex); | |
- mhl_sii_hpd_control(FALSE); | |
- } else | |
- mutex_unlock(&mhl_state_mutex); | |
- | |
- /* Enable Auto soft reset on SCDT = 0 */ | |
- MHL_SII_PAGE3_REG_WRITE(0x00, 0x84); | |
- | |
- /* HDMI Transcode mode enable */ | |
- MHL_SII_PAGE0_REG_WRITE(0x0D, 0x1C); | |
- | |
- mhl_sii_cbus_reset(); | |
- | |
- mhl_sii_cbus_init(); | |
- | |
-} | |
- | |
-static void mhl_sii_device_init(void) | |
-{ | |
- mhl_sii_device_reset(TRUE); | |
- | |
- chip_rev_id = MHL_SII_PAGE0_REG_READ(0x04); | |
- | |
- pr_info("%s: %02x%02x (%02x)\n", | |
- __func__, | |
- MHL_SII_PAGE0_REG_READ(0x03), | |
- MHL_SII_PAGE0_REG_READ(0x02), | |
- chip_rev_id); | |
- | |
- mhl_sii_chip_init(); | |
- | |
- /* switch power state to D3 */ | |
- mhl_sii_switch_power_state(POWER_STATE_D3); | |
-} | |
- | |
-static int mhl_sii_discovery_result_get(int *result) | |
-{ | |
- int timeout; | |
- MHL_DEV_DBG("%s: start\n", __func__); | |
- if (mhl_state->power_state != POWER_STATE_D0_MHL) { | |
- /* give MHL driver chance to handle RGND interrupt */ | |
- init_completion(&mhl_state->rgnd_done); | |
- timeout = wait_for_completion_interruptible_timeout | |
- (&mhl_state->rgnd_done, HZ/2); | |
- if (!timeout) { | |
- MHL_DEV_DBG("%s: RGND timed out!\n", __func__); | |
- /* most likely nothing plugged in USB connector, */ | |
- /* USB HOST connected or already in USB mode */ | |
- *result = MHL_DISCOVERY_RESULT_USB; | |
- return 0; | |
- } | |
- *result = mhl_state->mhl_mode ? | |
- MHL_DISCOVERY_RESULT_MHL : MHL_DISCOVERY_RESULT_USB; | |
- } else { | |
- /* in POWER_STATE_D0_MHL. already in MHL mode */ | |
- *result = MHL_DISCOVERY_RESULT_MHL; | |
- } | |
- MHL_DEV_DBG("%s: done\n", __func__); | |
- return 0; | |
-} | |
- | |
-#ifdef CONFIG_MHL_OSD_NAME | |
-static int mhl_sii_scratchpad_data_get(void) | |
-{ | |
- unsigned char burst_data[MHL_SCRATCHPAD_SIZE]; | |
- int i; | |
- MHL_DEV_DBG("%s: start\n", __func__); | |
- for (i = 0; i < MHL_SCRATCHPAD_SIZE; i++) | |
- burst_data[i] = MHL_SII_CBUS_REG_READ(0xC0 + i); | |
- mhl_notify_scpd_recv(mhl_state->mhl_dev, &burst_data[0]); | |
- MHL_DEV_DBG("%s: done\n", __func__); | |
- return 0; | |
-} | |
-#endif /* CONFIG_MHL_OSD_NAME */ | |
- | |
-const struct mhl_ops mhl_sii_ops = { | |
- .discovery_result_get = mhl_sii_discovery_result_get, | |
- .send_msc_command = mhl_sii_send_msc_command, | |
- .charging_control = mhl_sii_charging_control, | |
- .hpd_control = mhl_sii_hpd_control, | |
- .tmds_control = mhl_sii_tmds_control, | |
-#ifdef CONFIG_MHL_OSD_NAME | |
- .scratchpad_data_get = mhl_sii_scratchpad_data_get, | |
-#endif /* CONFIG_MHL_OSD_NAME */ | |
-}; | |
- | |
-static int mhl_sii_probe(struct i2c_client *client, | |
- const struct i2c_device_id *id) | |
-{ | |
- int rc = 0; | |
- struct mhl_sii_platform_data *pdata; | |
- | |
- pdata = client->dev.platform_data; | |
- if (!pdata) { | |
- pr_err("%s: invalid platform_data\n", __func__); | |
- return -EFAULT; | |
- } | |
- | |
- mhl_state->irq = client->irq; | |
- mhl_state->reset = pdata->reset; | |
- mhl_state->hpd_pin_mode = pdata->hpd_pin_mode; | |
- mhl_state->int_pin_mode = pdata->int_pin_mode; | |
- | |
- mhl_state->adopter_id = pdata->adopter_id; | |
- mhl_state->device_id = pdata->device_id; | |
- | |
- mhl_state->client = *client; | |
- | |
- mhl_state->power_state = POWER_STATE_FIRST_INIT; | |
- | |
- init_completion(&mhl_state->rgnd_done); | |
- INIT_WORK(&mhl_state->timer_work, mhl_discovery_timer_work); | |
- | |
- if (pdata->setup_power) { | |
- rc = pdata->setup_power(TRUE); | |
- if (rc) { | |
- pr_err("%s: setup power failed\n", __func__); | |
- goto probe_out; | |
- } | |
- } else | |
- pr_warn("%s: setup_power not supported\n", __func__); | |
- | |
- if (pdata->setup_low_power_mode) | |
- mhl_state->low_power_mode = pdata->setup_low_power_mode; | |
- else | |
- pr_warn("%s: MHL Low Power Mode not supported\n", __func__); | |
- | |
- if (pdata->setup_gpio) { | |
- rc = pdata->setup_gpio(TRUE); | |
- if (rc) { | |
- pr_err("%s: setup gpio failed\n", __func__); | |
- if (pdata->setup_power) | |
- pdata->setup_power(FALSE); | |
- goto probe_out; | |
- } | |
- } else | |
- pr_warn("%s: setup_gpio not supported\n", __func__); | |
- | |
- if (pdata->charging_enable) | |
- mhl_state->charging_enable = pdata->charging_enable; | |
- else | |
- pr_warn("%s: MHL charging not supported\n", __func__); | |
- | |
- /* register mhl device */ | |
- mhl_state->mhl_dev = mhl_device_register(SII_DEV_NAME, | |
- &client->dev, NULL, &mhl_sii_ops); | |
- if (IS_ERR(mhl_state->mhl_dev)) { | |
- pr_err("%s: mhl_device_register failed!\n", __func__); | |
- goto probe_out; | |
- } | |
- | |
- mhl_sii_device_init(); | |
- | |
- rc = request_threaded_irq(mhl_state->irq, NULL, &mhl_sii_isr, | |
- IRQF_TRIGGER_LOW | IRQF_ONESHOT, "mhl_sii_isr", NULL); | |
- if (rc) { | |
- pr_err("%s: request irq failed\n", __func__); | |
- if (pdata->setup_gpio) | |
- pdata->setup_gpio(FALSE); | |
- if (pdata->setup_power) | |
- pdata->setup_power(FALSE); | |
- goto probe_out; | |
- } | |
- | |
- init_timer(&mhl_state->discovery_timer); | |
- mhl_state->discovery_timer.function = | |
- mhl_discovery_timer; | |
- mhl_state->discovery_timer.data = (unsigned long)NULL; | |
- mhl_state->discovery_timer.expires = 0xffffffffL; | |
- add_timer(&mhl_state->discovery_timer); | |
- | |
- return 0; | |
- | |
-probe_out: | |
- return rc; | |
-} | |
- | |
-static int mhl_sii_remove(struct i2c_client *client) | |
-{ | |
- struct mhl_sii_platform_data *pdata; | |
- | |
- pdata = client->dev.platform_data; | |
- if (!pdata) { | |
- pr_err("%s: invalid platform_data\n", __func__); | |
- return -EFAULT; | |
- } | |
- | |
- disable_irq(mhl_state->irq); | |
- free_irq(mhl_state->irq, NULL); | |
- | |
- mhl_sii_device_reset(FALSE); | |
- | |
- if (pdata->setup_power) | |
- pdata->setup_power(FALSE); | |
- | |
- if (pdata->setup_gpio) | |
- pdata->setup_gpio(FALSE); | |
- | |
- /* unregister mhl device */ | |
- mhl_device_unregister(mhl_state->mhl_dev); | |
- | |
- return 0; | |
-} | |
- | |
-static void mhl_sii_shutdown(struct i2c_client *client) | |
-{ | |
- mhl_device_shutdown(mhl_state->mhl_dev); | |
-} | |
- | |
-#ifdef CONFIG_PM | |
-static int mhl_sii_i2c_suspend(struct device *dev) | |
-{ | |
- flush_work_sync(&mhl_state->timer_work); | |
- | |
- /* enable_irq_wake to setup this irq for wakeup trigger */ | |
- enable_irq_wake(mhl_state->irq); | |
- | |
- /* this is needed isr not to be executed before i2c resume */ | |
- disable_irq(mhl_state->irq); | |
- | |
- /* sii8334 power shoule be keep enbaled and sii8334 shoule be in D3 */ | |
- /* and if low_power_mode operation exist, call it for some reason. */ | |
- if (mhl_state->low_power_mode) | |
- mhl_state->low_power_mode(1); | |
- | |
- return 0; | |
-} | |
- | |
-static int mhl_sii_i2c_resume(struct device *dev) | |
-{ | |
- /* exit from low_power_mode */ | |
- if (mhl_state->low_power_mode) | |
- mhl_state->low_power_mode(0); | |
- | |
- disable_irq_wake(mhl_state->irq); | |
- | |
- enable_irq(mhl_state->irq); | |
- | |
- return 0; | |
-} | |
- | |
-SIMPLE_DEV_PM_OPS(mhl_sii_pm_ops, mhl_sii_i2c_suspend, mhl_sii_i2c_resume); | |
-#endif /* CONFIG_PM */ | |
- | |
-static const struct i2c_device_id mhl_sii_id[] = { | |
- { SII_DEV_NAME, 0 }, | |
- { } | |
-}; | |
- | |
-static struct i2c_driver mhl_sii_i2c_driver = { | |
- .driver = { | |
- .name = SII_DEV_NAME, | |
- .owner = THIS_MODULE, | |
-#ifdef CONFIG_PM | |
- .pm = &mhl_sii_pm_ops, | |
-#endif /* CONFIG_PM */ | |
- }, | |
- .probe = mhl_sii_probe, | |
- .remove = mhl_sii_remove, | |
- .shutdown = mhl_sii_shutdown, | |
- .id_table = mhl_sii_id, | |
-}; | |
- | |
-static int __init mhl_sii_init(void) | |
-{ | |
- int rc; | |
- | |
- mhl_state = kzalloc(sizeof(*mhl_state), GFP_KERNEL); | |
- if (!mhl_state) { | |
- pr_err("%s: out of memory!\n", __func__); | |
- return -ENOMEM; | |
- } | |
- | |
- rc = i2c_add_driver(&mhl_sii_i2c_driver); | |
- if (rc) { | |
- pr_err("%s: i2c_add_driver failed (%d)\n", | |
- __func__, rc); | |
- kfree(mhl_state); | |
- goto init_out; | |
- } | |
- | |
- wake_lock_init(&mhl_wake_lock, WAKE_LOCK_SUSPEND, "mhl_wake_lock"); | |
- | |
- return 0; | |
- | |
-init_out: | |
- return rc; | |
-} | |
- | |
-static void __exit mhl_sii_exit(void) | |
-{ | |
- wake_lock_destroy(&mhl_wake_lock); | |
- i2c_del_driver(&mhl_sii_i2c_driver); | |
- kfree(mhl_state); | |
-} | |
- | |
- | |
-/* | |
- * We have to use late_initcall instead of module_init. | |
- * Because, when we use module_init, the issue occurred | |
- * that cannot charge a phone from dongle or MHL straight cable | |
- * when a phone is a power off state. | |
- * This reason is cause that reading DEV_CAT of mhl_msc_command_done() | |
- * of the MHL driver is run before calling pm8921_charger_probe(). | |
- * To solve this issue, It is necessary for us to call late_initcall | |
- * which pm8921_charger driver called. | |
- */ | |
-late_initcall(mhl_sii_init); | |
-module_exit(mhl_sii_exit); | |
- | |
-MODULE_LICENSE("GPL v2"); | |
-MODULE_VERSION("1.0"); | |
-MODULE_AUTHOR("Sony Ericsson Mobile Communications AB"); | |
-MODULE_DESCRIPTION("SiI8334 MHL Transmitter Driver"); | |
diff --git a/drivers/video/msm/mipi_dsi.c b/drivers/video/msm/mipi_dsi.c | |
index 09d4f8b..4816059 100644 | |
--- a/drivers/video/msm/mipi_dsi.c | |
+++ b/drivers/video/msm/mipi_dsi.c | |
@@ -1,5 +1,4 @@ | |
/* Copyright (c) 2008-2013, The Linux Foundation. All rights reserved. | |
- * Copyright (C) 2012-2013 Sony Mobile Communications AB. | |
* | |
* This program is free software; you can redistribute it and/or modify | |
* it under the terms of the GNU General Public License version 2 and | |
@@ -35,7 +34,6 @@ | |
#include "mipi_dsi.h" | |
#include "mdp.h" | |
#include "mdp4.h" | |
-#include "mipi_dsi_panel_driver.h" | |
u32 dsi_irq; | |
u32 esc_byte_ratio; | |
@@ -603,16 +601,6 @@ static int mipi_dsi_probe(struct platform_device *pdev) | |
pdev_list[pdev_list_cnt++] = pdev; | |
- if (mfd->panel_pdev) { | |
- struct mipi_dsi_data *dsi_data; | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data) | |
- return -ENODEV; | |
- if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) | |
- dsi_data->dsi_power_save = | |
- mipi_dsi_pdata->dsi_power_save; | |
- } | |
- | |
esc_byte_ratio = pinfo->mipi.esc_byte_ratio; | |
if (!mfd->cont_splash_done) | |
diff --git a/drivers/video/msm/mipi_dsi.h b/drivers/video/msm/mipi_dsi.h | |
index b0d1105..7d994f2 100644 | |
--- a/drivers/video/msm/mipi_dsi.h | |
+++ b/drivers/video/msm/mipi_dsi.h | |
@@ -292,7 +292,6 @@ void mipi_dsi_init(void); | |
void mipi_dsi_lane_cfg(void); | |
void mipi_dsi_bist_ctrl(void); | |
int mipi_dsi_buf_alloc(struct dsi_buf *, int size); | |
-void mipi_dsi_buf_release(struct dsi_buf *dp); | |
int mipi_dsi_cmd_dma_add(struct dsi_buf *dp, struct dsi_cmd_desc *cm); | |
int mipi_dsi_cmds_tx(struct dsi_buf *dp, struct dsi_cmd_desc *cmds, int cnt); | |
int mipi_dsi_cmds_single_tx(struct dsi_buf *dp, struct dsi_cmd_desc *cmds, | |
diff --git a/drivers/video/msm/mipi_dsi_host.c b/drivers/video/msm/mipi_dsi_host.c | |
index 1ee4007..9e4160c 100644 | |
--- a/drivers/video/msm/mipi_dsi_host.c | |
+++ b/drivers/video/msm/mipi_dsi_host.c | |
@@ -332,16 +332,6 @@ int mipi_dsi_buf_alloc(struct dsi_buf *dp, int size) | |
return size; | |
} | |
-void mipi_dsi_buf_release(struct dsi_buf *dp) | |
-{ | |
- kfree(dp->start); | |
- dp->start = NULL; | |
- dp->end = NULL; | |
- dp->data = NULL; | |
- dp->size = 0; | |
- dp->len = 0; | |
-} | |
- | |
/* | |
* mipi dsi gerneric long write | |
*/ | |
@@ -1296,6 +1286,16 @@ int mipi_dsi_cmds_rx(struct msm_fb_data_type *mfd, | |
if (len > MIPI_DSI_LEN) | |
len = MIPI_DSI_LEN; /* 8 bytes at most */ | |
+ len = (len + 3) & ~0x03; /* len 4 bytes align */ | |
+ diff = len - rlen; | |
+ /* | |
+ * add extra 2 bytes to len to have overall | |
+ * packet size is multipe by 4. This also make | |
+ * sure 4 bytes dcs headerlocates within a | |
+ * 32 bits register after shift in. | |
+ * after all, len should be either 6 or 10. | |
+ */ | |
+ len += 2; | |
cnt = len + 6; /* 4 bytes header + 2 bytes crc */ | |
} | |
@@ -1339,9 +1339,6 @@ int mipi_dsi_cmds_rx(struct msm_fb_data_type *mfd, | |
mipi_dsi_cmd_dma_rx(rp, cnt); | |
- diff = rp->len - cnt; | |
- rp->data += diff; | |
- | |
if (mfd->panel_info.mipi.no_max_pkt_size) { | |
/* | |
* remove extra 2 bytes from previous | |
@@ -1369,6 +1366,8 @@ int mipi_dsi_cmds_rx(struct msm_fb_data_type *mfd, | |
case DTYPE_GEN_LREAD_RESP: | |
case DTYPE_DCS_LREAD_RESP: | |
mipi_dsi_long_read_resp(rp); | |
+ rp->len -= 2; /* extra 2 bytes added */ | |
+ rp->len -= diff; /* align bytes */ | |
break; | |
default: | |
break; | |
diff --git a/drivers/video/msm/mipi_dsi_panel_debugfs.c b/drivers/video/msm/mipi_dsi_panel_debugfs.c | |
deleted file mode 100644 | |
index 8ab8670..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_debugfs.c | |
+++ /dev/null | |
@@ -1,898 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_debugfs.c | |
- * | |
- * Copyright (C) 2012-2013 Sony Mobile Communications AB. | |
- * | |
- * Sony Mobile DSI display driver debug fs | |
- * | |
- * Author: Johan Olson <[email protected]> | |
- * Author: Joakim Wesslen <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2, as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
-/* #define DEBUG */ | |
- | |
-#include <linux/module.h> | |
-#include <linux/kernel.h> | |
-#include <linux/sched.h> | |
-#include <linux/init.h> | |
-#include <linux/list.h> | |
-#include <linux/kobject.h> | |
-#include <linux/platform_device.h> | |
-#include <linux/io.h> | |
-#include <linux/debugfs.h> | |
-#include <linux/seq_file.h> | |
-#include <linux/slab.h> | |
-#include <linux/delay.h> | |
-#include <linux/uaccess.h> | |
-#include <linux/ctype.h> | |
- | |
-#include "msm_fb.h" | |
-#include <video/mipi_dsi_panel.h> | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-static char *res_buf; | |
-static int buf_sz; | |
- | |
-#define TMP_BUF_SZ 128 | |
-#define MAX_WRITE_DATA 100 | |
- | |
-#ifdef CONFIG_FB_MSM_MDP303 | |
-#define DSI_VIDEO_BASE 0xF0000 /* Taken from mdp_dma_dsi_video.c */ | |
-#else | |
-#define DSI_VIDEO_BASE 0xE0000 /* Taken from mdp4_overlay_dsi_video.c */ | |
-#endif | |
- | |
-enum dbg_cmd_type { | |
- DCS, | |
- GEN, | |
-}; | |
- | |
-static void update_res_buf(char *string) | |
-{ | |
- res_buf = krealloc(res_buf, buf_sz + strnlen(string, TMP_BUF_SZ) + 1, | |
- GFP_KERNEL); | |
- if (!res_buf) { | |
- pr_err("%s: Failed to allocate buffer\n", __func__); | |
- return; | |
- } | |
- | |
- memcpy(res_buf + buf_sz, string, strnlen(string, TMP_BUF_SZ) + 1); | |
- buf_sz += strnlen(string, TMP_BUF_SZ); /* Exclude NULL termination */ | |
-} | |
- | |
-static void reset_res_buf(void) | |
-{ | |
- kfree(res_buf); | |
- res_buf = NULL; | |
- buf_sz = 0; | |
-} | |
- | |
-static void print_cmds2file(const struct panel_cmd *pcmd, struct seq_file *s) | |
-{ | |
- int n, i, j; | |
- struct dsi_cmd_desc dsi; | |
- | |
- if (!pcmd) { | |
- seq_printf(s, "---------\n"); | |
- goto exit; | |
- } | |
- | |
- for (n = 0; ; ++n) { | |
- switch (pcmd[n].type) { | |
- case CMD_END: | |
- seq_printf(s, "---------\n"); | |
- goto exit; | |
- break; | |
- case CMD_WAIT_MS: | |
- seq_printf(s, "CMD_WAIT_MS: %d ms\n", | |
- pcmd[n].payload.data); | |
- break; | |
- case CMD_DSI: | |
- for (i = 0; i < pcmd[n].payload.dsi_payload.cnt; i++) { | |
- dsi = pcmd[n].payload.dsi_payload.dsi[i]; | |
- switch (dsi.dtype) { | |
- case DTYPE_GEN_WRITE: | |
- seq_printf(s, "DTYPE_GEN_WRITE: "); | |
- break; | |
- case DTYPE_GEN_WRITE1: | |
- seq_printf(s, "DTYPE_GEN_WRITE1: "); | |
- break; | |
- case DTYPE_GEN_WRITE2: | |
- seq_printf(s, "DTYPE_GEN_WRITE2: "); | |
- break; | |
- case DTYPE_GEN_LWRITE: | |
- seq_printf(s, "DTYPE_GEN_LWRITE: "); | |
- break; | |
- case DTYPE_GEN_READ: | |
- seq_printf(s, "DTYPE_GEN_READ: "); | |
- break; | |
- case DTYPE_GEN_READ1: | |
- seq_printf(s, "DTYPE_GEN_READ1: "); | |
- break; | |
- case DTYPE_GEN_READ2: | |
- seq_printf(s, "DTYPE_GEN_READ2: "); | |
- break; | |
- case DTYPE_DCS_LWRITE: | |
- seq_printf(s, "DTYPE_DCS_LWRITE: "); | |
- break; | |
- case DTYPE_DCS_WRITE: | |
- seq_printf(s, "DTYPE_DCS_WRITE: "); | |
- break; | |
- case DTYPE_DCS_WRITE1: | |
- seq_printf(s, "DTYPE_DCS_WRITE1: "); | |
- break; | |
- case DTYPE_DCS_READ: | |
- seq_printf(s, "DTYPE_DCS_READ: "); | |
- break; | |
- case DTYPE_MAX_PKTSIZE: | |
- seq_printf(s, "DTYPE_MAX_PKTSIZE: "); | |
- break; | |
- case DTYPE_NULL_PKT: | |
- seq_printf(s, "DTYPE_NULL_PKT: "); | |
- break; | |
- case DTYPE_BLANK_PKT: | |
- seq_printf(s, "DTYPE_BLANK_PKT: "); | |
- break; | |
- case DTYPE_CM_ON: | |
- seq_printf(s, "DTYPE_CM_ON: "); | |
- break; | |
- case DTYPE_CM_OFF: | |
- seq_printf(s, "DTYPE_CM_OFF: "); | |
- break; | |
- case DTYPE_PERIPHERAL_ON: | |
- seq_printf(s, "DTYPE_PERIPHERAL_ON: "); | |
- break; | |
- case DTYPE_PERIPHERAL_OFF: | |
- seq_printf(s, "DTYPE_PERIPHERAL_OFF: "); | |
- break; | |
- default: | |
- seq_printf(s, "Unknown dtype: 0x%x: ", | |
- dsi.dtype); | |
- } | |
- seq_printf(s, "last = %d, vc = %d, ack = %d, ", | |
- dsi.last, dsi.vc, dsi.ack); | |
- seq_printf(s, "wait = %d, dlen = %d\npayload: ", | |
- dsi.wait, dsi.dlen); | |
- | |
- for (j = 0; j < dsi.dlen; j++) | |
- seq_printf(s, "0x%.2x ", | |
- dsi.payload[j]); | |
- seq_printf(s, "\n"); | |
- } | |
- break; | |
- case CMD_RESET: | |
- seq_printf(s, "CMD_RESET: data: %d\n", | |
- pcmd[n].payload.data); | |
- break; | |
- case CMD_PLATFORM: | |
- seq_printf(s, "CMD_PLATFORM: data: %d\n", | |
- pcmd[n].payload.data); | |
- break; | |
- default: | |
- seq_printf(s, "UNKNOWN CMD: 0x%.2x data: %d\n", | |
- pcmd[n].type, pcmd[n].payload.data); | |
- } | |
- } | |
-exit: | |
- return; | |
-} | |
- | |
-static int info_show(struct seq_file *s, void *unused) | |
-{ | |
- struct msm_fb_data_type *mfd = s->private; | |
- struct mipi_dsi_data *dsi_data; | |
- | |
- dev_dbg(&mfd->panel_pdev->dev, "%s\n", __func__); | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data || !dsi_data->panel) { | |
- seq_printf(s, "No panel\n"); | |
- pr_err("%s: no panels\n", __func__); | |
- return 0; | |
- } | |
- | |
- if (dsi_data->panel->name) { | |
- seq_printf(s, "Panel: %s\n", dsi_data->panel->name); | |
- seq_printf(s, "xres = %d, yres = %d\n", | |
- dsi_data->panel_data.panel_info.xres, | |
- dsi_data->panel_data.panel_info.yres); | |
- seq_printf(s, "width = %d mm, height = %d mm\n", | |
- dsi_data->panel->width, | |
- dsi_data->panel->height); | |
- seq_printf(s, "---------\n"); | |
- if (dsi_data->panel->pctrl) { | |
- seq_printf(s, "display_init commands:\n"); | |
- print_cmds2file(dsi_data->panel->pctrl->display_init, | |
- s); | |
- seq_printf(s, "display_on commands:\n"); | |
- print_cmds2file(dsi_data->panel->pctrl->display_on, s); | |
- seq_printf(s, "display_off commands:\n"); | |
- print_cmds2file(dsi_data->panel->pctrl->display_off, s); | |
- seq_printf(s, "read_id commands:\n"); | |
- print_cmds2file(dsi_data->panel->pctrl->read_id, s); | |
- } else { | |
- seq_printf(s, "No pctrl\n"); | |
- } | |
- } else { | |
- seq_printf(s, "No panel name\n"); | |
- } | |
- return 0; | |
-} | |
- | |
-static void print_params(int dtype, u8 reg, int len, u8 *data) | |
-{ | |
- int i = 0; | |
- char tmp[TMP_BUF_SZ]; | |
- | |
- switch (dtype) { | |
- case DTYPE_GEN_WRITE: | |
- update_res_buf("GEN_WRITE\n"); | |
- break; | |
- case DTYPE_GEN_WRITE1: | |
- update_res_buf("GEN_WRITE1\n"); | |
- break; | |
- case DTYPE_GEN_WRITE2: | |
- update_res_buf("GEN_WRITE2\n"); | |
- break; | |
- case DTYPE_GEN_LWRITE: | |
- update_res_buf("GEN_LWRITE\n"); | |
- break; | |
- case DTYPE_GEN_READ: | |
- update_res_buf("GEN_READ\n"); | |
- break; | |
- case DTYPE_GEN_READ1: | |
- update_res_buf("GEN_READ1\n"); | |
- break; | |
- case DTYPE_GEN_READ2: | |
- update_res_buf("GEN_READ2\n"); | |
- break; | |
- case DTYPE_DCS_LWRITE: | |
- update_res_buf("DCS_LWRITE\n"); | |
- break; | |
- case DTYPE_DCS_WRITE: | |
- update_res_buf("DCS_WRITE\n"); | |
- break; | |
- case DTYPE_DCS_WRITE1: | |
- update_res_buf("DCS_WRITE1\n"); | |
- break; | |
- case DTYPE_DCS_READ: | |
- update_res_buf("DCS_READ\n"); | |
- break; | |
- default: | |
- snprintf(tmp, sizeof(tmp), "Unknown dtype = 0x%x\n", dtype); | |
- update_res_buf(tmp); | |
- } | |
- | |
- if (len > 0) { | |
- snprintf(tmp, sizeof(tmp), "reg=0x%.2X\n", reg); | |
- update_res_buf(tmp); | |
- snprintf(tmp, sizeof(tmp), "len=%d\n", len); | |
- update_res_buf(tmp); | |
- for (i = 0; i < len; i++) { | |
- snprintf(tmp, sizeof(tmp), "data[%d]=0x%.2X\n", i, | |
- data[i]); | |
- update_res_buf(tmp); | |
- } | |
- } else { | |
- update_res_buf("Something went wrong, length is zero.\n"); | |
- snprintf(tmp, sizeof(tmp), | |
- "reg=0x%.2X, len=%d, data[0]=0x%.2X\n", | |
- reg, len, data[0]); | |
- update_res_buf(tmp); | |
- } | |
-} | |
- | |
-static int setup_reg_access(struct device *dev, struct dsi_buf *rx_buf, | |
- struct dsi_buf *tx_buf, char **buf, | |
- const char __user *ubuf, size_t count) | |
-{ | |
- int ret = 0; | |
- | |
- reset_res_buf(); | |
- | |
- if (rx_buf) { | |
- ret = mipi_dsi_buf_alloc(rx_buf, DSI_BUF_SIZE); | |
- if (ret <= 0) { | |
- dev_err(dev, "mipi_dsi_buf_alloc(rx) failed!\n"); | |
- ret = -ENOMEM; | |
- goto exit; | |
- } | |
- } | |
- | |
- if (tx_buf) { | |
- ret = mipi_dsi_buf_alloc(tx_buf, DSI_BUF_SIZE); | |
- if (ret <= 0) { | |
- dev_err(dev, "mipi_dsi_buf_alloc(tx) failed!\n"); | |
- ret = -ENOMEM; | |
- goto fail_free_rx; | |
- } | |
- } | |
- | |
- *buf = kzalloc(sizeof(char) * count, GFP_KERNEL); | |
- if (!*buf) { | |
- dev_err(dev, "%s: Failed to allocate buffer\n", __func__); | |
- ret = -ENOMEM; | |
- goto fail_free_all; | |
- } | |
- | |
- if (copy_from_user(*buf, ubuf, count)) { | |
- ret = -EFAULT; | |
- goto fail_free_all; | |
- } | |
- return 0; | |
- | |
-fail_free_all: | |
- if (tx_buf) | |
- mipi_dsi_buf_release(tx_buf); | |
- kfree(*buf); | |
-fail_free_rx: | |
- if (rx_buf) | |
- mipi_dsi_buf_release(rx_buf); | |
-exit: | |
- return ret; | |
-} | |
- | |
-static int get_cmd_type(char *buf, enum dbg_cmd_type *cmd) | |
-{ | |
- int ret = 0; | |
- | |
- if (!strncmp(buf, "dcs", 3)) | |
- *cmd = DCS; | |
- else if (!strncmp(buf, "gen", 3)) | |
- *cmd = GEN; | |
- else | |
- ret = -EFAULT; | |
- return ret; | |
-} | |
- | |
-static int get_parameters(const char *p, u8 *par_buf, int par_buf_size, | |
- int *nbr_params) | |
-{ | |
- int ret = 0; | |
- | |
- while (true) { | |
- if (isspace(*p)) { | |
- p++; | |
- } else { | |
- if (sscanf(p, "%4hhx", &par_buf[*nbr_params]) == 1) { | |
- (*nbr_params)++; | |
- while (isxdigit(*p) || (*p == 'x')) | |
- p++; | |
- } | |
- } | |
- if (*nbr_params > par_buf_size) { | |
- update_res_buf("Too many parameters\n"); | |
- ret = -EINVAL; | |
- goto exit; | |
- } | |
- if (iscntrl(*p)) | |
- break; | |
- } | |
-exit: | |
- return ret; | |
-} | |
- | |
-int prepare_for_reg_access(struct msm_fb_data_type *mfd, | |
- enum power_state *old_state) | |
-{ | |
- struct device *dev = &mfd->panel_pdev->dev; | |
- struct mipi_dsi_data *dsi_data; | |
- int ret = 0; | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- | |
- /* Needed to make sure the display stack isn't powered on/off while */ | |
- /* we are executing. The best solution would be a read/write function */ | |
- /* that handles the current power state */ | |
- mutex_lock(&mfd->power_lock); | |
- | |
- if (mfd->panel_power_on) { | |
- dev_dbg(dev, "%s: panel is on, don't do anything\n", __func__); | |
- } else { | |
- dev_dbg(dev, "%s: panel is NOT on, power on stack\n", __func__); | |
- | |
- mutex_lock(&dsi_data->lock); | |
- *old_state = dsi_data->panel_state; | |
- dsi_data->panel_state = DEBUGFS_POWER_OFF; | |
- mutex_unlock(&dsi_data->lock); | |
- | |
- ret = panel_next_on(mfd->pdev); /* msm_fb_dev */ | |
- if (ret) { | |
- mutex_unlock(&mfd->power_lock); | |
- goto exit; | |
- } | |
- } | |
- | |
- mutex_lock(&mfd->dma->ov_mutex); | |
- /* This should not be needed, but without this we sometimes don't get an | |
- * interrupt when transmitting the command */ | |
- if (mfd->panel_info.mipi.mode == DSI_VIDEO_MODE) { | |
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); | |
- MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); | |
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); | |
- msleep(20); | |
- mipi_dsi_controller_cfg(0); | |
- mipi_dsi_op_mode_config(DSI_CMD_MODE); | |
- } | |
-exit: | |
- return ret; | |
-} | |
- | |
-void post_reg_access(struct msm_fb_data_type *mfd, | |
- enum power_state old_state) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- | |
- /* This should not be needed, but without this we sometimes don't get an | |
- * interrupt when transmitting the command */ | |
- if (mfd->panel_info.mipi.mode == DSI_VIDEO_MODE) { | |
- mipi_dsi_op_mode_config(DSI_VIDEO_MODE); | |
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); | |
- mipi_dsi_sw_reset(); | |
- mipi_dsi_controller_cfg(1); | |
- MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1); | |
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); | |
- } | |
- mutex_unlock(&mfd->dma->ov_mutex); | |
- | |
- if (dsi_data->panel_state == DEBUGFS_POWER_ON) { | |
- (void)panel_next_off(mfd->pdev); | |
- mutex_lock(&dsi_data->lock); | |
- dsi_data->panel_state = old_state; | |
- mutex_unlock(&dsi_data->lock); | |
- } | |
- mutex_unlock(&mfd->power_lock); | |
-} | |
- | |
-static ssize_t reg_read(struct file *file, const char __user *ubuf, | |
- size_t count, loff_t *ppos) | |
-{ | |
- struct seq_file *s = file->private_data; | |
- struct msm_fb_data_type *mfd = s->private; | |
- struct device *dev; | |
- u8 params[3]; /* No more than reg + two parameters is allowed */ | |
- char *buf; | |
- const char *p; | |
- int ret; | |
- int nbr_bytes_to_read; | |
- int i; | |
- int j; | |
- enum dbg_cmd_type cmd; | |
- struct dsi_buf tx_buf; | |
- struct dsi_buf rx_buf; | |
- struct dsi_cmd_desc dsi; | |
- enum power_state old_state = PANEL_OFF; | |
- | |
- dev = &mfd->panel_pdev->dev; | |
- dev_dbg(dev, "%s\n", __func__); | |
- | |
- ret = setup_reg_access(dev, &rx_buf, &tx_buf, &buf, ubuf, count); | |
- if (ret) | |
- goto exit; | |
- | |
- ret = get_cmd_type(buf, &cmd); | |
- if (ret) { | |
- update_res_buf("Read - unknown type\n"); | |
- goto fail_free_all; | |
- } | |
- | |
- p = buf; | |
- p = p+4; | |
- | |
- /* Get nbr_bytes_to_read */ | |
- if (sscanf(p, "%d", &nbr_bytes_to_read) != 1) { | |
- update_res_buf("Read - parameter error\n"); | |
- ret = -EINVAL; | |
- goto fail_free_all; | |
- } | |
- | |
- while (isxdigit(*p) || (*p == 'x')) | |
- p++; | |
- | |
- dev_dbg(dev, "nbr_bytes_to_read = %d\n", nbr_bytes_to_read); | |
- i = 0; | |
- | |
- ret = get_parameters(p, params, ARRAY_SIZE(params), &i); | |
- if (ret) | |
- goto fail_free_all; | |
- | |
- ret = prepare_for_reg_access(mfd, &old_state); | |
- if (ret) | |
- goto fail_free_all; | |
- | |
- if (cmd == DCS) { | |
- dsi.dtype = DTYPE_DCS_READ; | |
- } else { | |
- if (i == 1) { /* 0 parameters */ | |
- dsi.dtype = DTYPE_GEN_READ; | |
- } else if (i == 2) { /* 1 parameter */ | |
- dsi.dtype = DTYPE_GEN_READ1; | |
- } else { /* 2 paramters */ | |
- dsi.dtype = DTYPE_GEN_READ2; | |
- } | |
- } | |
- dsi.last = 1; | |
- dsi.vc = 0; | |
- dsi.ack = 1; | |
- dsi.wait = 5; /* why 5? */ | |
- dsi.dlen = i; | |
- dsi.payload = params; | |
- | |
- dev_dbg(dev, "dtype = %d, last = %d, vc = %d, ack = %d, wait = %d, " | |
- "dlen = %d\n", dsi.dtype, dsi.last, dsi.vc, dsi.ack, dsi.wait, | |
- dsi.dlen); | |
- for (j = 0; j < i; j++) | |
- dev_dbg(dev, "payload[%d] = 0x%x\n", j, dsi.payload[j]); | |
- | |
- mipi_dsi_cmds_rx(mfd, &tx_buf, &rx_buf, &dsi, nbr_bytes_to_read); | |
- post_reg_access(mfd, old_state); | |
- print_params(dsi.dtype, params[0], rx_buf.len, rx_buf.data); | |
- | |
-fail_free_all: | |
- kfree(buf); | |
- mipi_dsi_buf_release(&rx_buf); | |
- mipi_dsi_buf_release(&tx_buf); | |
-exit: | |
- return count; | |
-} | |
- | |
-static ssize_t reg_write(struct file *file, const char __user *ubuf, | |
- size_t count, loff_t *ppos) | |
-{ | |
- struct seq_file *s = file->private_data; | |
- struct msm_fb_data_type *mfd = s->private; | |
- struct device *dev; | |
- char *buf; | |
- const char *p; | |
- enum dbg_cmd_type cmd; | |
- u8 data[MAX_WRITE_DATA]; | |
- int i = 0; | |
- int j; | |
- int ret; | |
- struct dsi_buf tx_buf; | |
- struct dsi_cmd_desc dsi; | |
- enum power_state old_state = PANEL_OFF; | |
- | |
- dev = &mfd->panel_pdev->dev; | |
- dev_dbg(dev, "%s\n", __func__); | |
- ret = setup_reg_access(dev, NULL, &tx_buf, &buf, ubuf, count); | |
- if (ret) | |
- goto exit; | |
- | |
- ret = get_cmd_type(buf, &cmd); | |
- if (ret) { | |
- update_res_buf("Write - unknown type\n"); | |
- goto fail_free_all; | |
- } | |
- | |
- p = buf; | |
- p = p+4; | |
- | |
- /* Get first param, Register */ | |
- if (sscanf(p, "%4hhx", &data[0]) != 1) { | |
- update_res_buf("Write - parameter error\n"); | |
- ret = -EINVAL; | |
- goto fail_free_all; | |
- } | |
- i++; | |
- | |
- while (isxdigit(*p) || (*p == 'x')) | |
- p++; | |
- | |
- ret = get_parameters(p, data, ARRAY_SIZE(data) - 1, &i); | |
- if (ret) | |
- goto fail_free_all; | |
- | |
- ret = prepare_for_reg_access(mfd, &old_state); | |
- if (ret) | |
- goto fail_free_all; | |
- | |
- if (cmd == DCS) { | |
- if (i == 1) { /* 0 parameters */ | |
- dsi.dtype = DTYPE_DCS_WRITE; | |
- } else if (i == 2) { /* 1 parameter */ | |
- dsi.dtype = DTYPE_DCS_WRITE1; | |
- } else { /* Many parameters */ | |
- dsi.dtype = DTYPE_DCS_LWRITE; | |
- } | |
- } else { | |
- if (i == 1) { /* 0 parameters */ | |
- dsi.dtype = DTYPE_GEN_WRITE; | |
- } else if (i == 2) { /* 1 parameter */ | |
- dsi.dtype = DTYPE_GEN_WRITE1; | |
- } else if (i == 3) { /* 2 parameters */ | |
- dsi.dtype = DTYPE_GEN_WRITE2; | |
- } else { /* Many parameters */ | |
- dsi.dtype = DTYPE_GEN_LWRITE; | |
- } | |
- } | |
- dsi.last = 1; | |
- dsi.vc = 0; | |
- dsi.ack = 0; | |
- dsi.wait = 0; | |
- dsi.dlen = i; | |
- dsi.payload = data; | |
- | |
- dev_dbg(dev, "last = %d, vc = %d, ack = %d, wait = %d, dlen = %d\n", | |
- dsi.last, dsi.vc, dsi.ack, dsi.wait, dsi.dlen); | |
- for (j = 0; j < i; j++) | |
- dev_dbg(dev, "payload[%d] = 0x%x\n", j, dsi.payload[j]); | |
- mipi_dsi_cmds_tx(&tx_buf, &dsi, 1); | |
- | |
- post_reg_access(mfd, old_state); | |
- print_params(dsi.dtype, data[0], i, dsi.payload); | |
- | |
-fail_free_all: | |
- kfree(buf); | |
- mipi_dsi_buf_release(&tx_buf); | |
-exit: | |
- return count; | |
-} | |
- | |
-static int panels_show(struct seq_file *s, void *unused) | |
-{ | |
- struct msm_fb_data_type *mfd = s->private; | |
- int n = 0; | |
- struct mipi_dsi_data *dsi_data; | |
- | |
- dev_dbg(&mfd->panel_pdev->dev, "%s\n", __func__); | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data || !dsi_data->panels) { | |
- seq_printf(s, "No panel platform data\n"); | |
- pr_err("%s: no panels\n", __func__); | |
- return 0; | |
- } | |
- | |
- seq_printf(s, "Supported display panels:\n"); | |
- while (dsi_data->panels[n] != NULL) { | |
- seq_printf(s, "DSI panel[%d]=%s\n", n, | |
- dsi_data->panels[n]->name); | |
- n++; | |
- } | |
- return 0; | |
-} | |
- | |
-static int result_show(struct seq_file *s, void *unused) | |
-{ | |
- seq_printf(s, "%s", res_buf); | |
- if (!res_buf) | |
- seq_printf(s, "\n"); | |
- return 0; | |
-} | |
- | |
-static int reset(struct file *file, const char __user *ubuf, | |
- size_t count, loff_t *ppos) | |
-{ | |
- struct seq_file *s = file->private_data; | |
- struct msm_fb_data_type *mfd = s->private; | |
- struct device *dev; | |
- long level; | |
- int ret = 0; | |
- char *buf; | |
- struct mipi_dsi_data *dsi_data; | |
- | |
- reset_res_buf(); | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- dev = &mfd->panel_pdev->dev; | |
- if (!dsi_data->lcd_reset) { | |
- ret = -EFAULT; | |
- goto exit; | |
- } | |
- | |
- buf = kzalloc(sizeof(char) * count, GFP_KERNEL); | |
- if (!buf) { | |
- ret = -ENOMEM; | |
- goto exit; | |
- } | |
- | |
- if (copy_from_user(buf, ubuf, count)) { | |
- ret = -EFAULT; | |
- goto fail_free_all; | |
- } | |
- | |
- /* Get parameter */ | |
- if (kstrtol(buf, 10, &level) < 0) { | |
- update_res_buf("Reset - parameter error\n"); | |
- ret = -EINVAL; | |
- goto fail_free_all; | |
- } | |
- | |
- if (level != 0 && level != 1) { | |
- update_res_buf("Reset - parameter error\n"); | |
- ret = -EINVAL; | |
- goto fail_free_all; | |
- } | |
- | |
- ret = dsi_data->lcd_reset(level); | |
- if (ret) | |
- goto fail_free_all; | |
- update_res_buf("Reset succeeded\n"); | |
- dev_info(dev, "%s: Display reset performed.\n", __func__); | |
-fail_free_all: | |
- kfree(buf); | |
-exit: | |
- if (ret) { | |
- dev_err(dev, "%s: Reset failed, ret = 0x%x\n", __func__, ret); | |
- update_res_buf("Reset failed\n"); | |
- } | |
- return count; | |
-} | |
- | |
-static int info_open(struct inode *inode, struct file *file) | |
-{ | |
- return single_open(file, info_show, inode->i_private); | |
-} | |
- | |
-static const struct file_operations info_fops = { | |
- .owner = THIS_MODULE, | |
- .open = info_open, | |
- .read = seq_read, | |
- .llseek = seq_lseek, | |
- .release = single_release, | |
-}; | |
- | |
-static int read_open(struct inode *inode, struct file *file) | |
-{ | |
- return single_open(file, NULL, inode->i_private); | |
-} | |
- | |
-static const struct file_operations read_fops = { | |
- .owner = THIS_MODULE, | |
- .open = read_open, | |
- .write = reg_read, | |
- .llseek = seq_lseek, | |
- .release = single_release, | |
-}; | |
- | |
-static int write_open(struct inode *inode, struct file *file) | |
-{ | |
- return single_open(file, NULL, inode->i_private); | |
-} | |
- | |
-static const struct file_operations write_fops = { | |
- .owner = THIS_MODULE, | |
- .open = write_open, | |
- .write = reg_write, | |
- .llseek = seq_lseek, | |
- .release = single_release, | |
-}; | |
- | |
-static int panels_open(struct inode *inode, struct file *file) | |
-{ | |
- return single_open(file, panels_show, inode->i_private); | |
-} | |
- | |
-static const struct file_operations panels_fops = { | |
- .owner = THIS_MODULE, | |
- .open = panels_open, | |
- .read = seq_read, | |
- .llseek = seq_lseek, | |
- .release = single_release, | |
-}; | |
- | |
-static int result_open(struct inode *inode, struct file *file) | |
-{ | |
- return single_open(file, result_show, inode->i_private); | |
-} | |
- | |
-static const struct file_operations result_fops = { | |
- .owner = THIS_MODULE, | |
- .open = result_open, | |
- .read = seq_read, | |
- .llseek = seq_lseek, | |
- .release = single_release, | |
-}; | |
- | |
-static int reset_open(struct inode *inode, struct file *file) | |
-{ | |
- return single_open(file, NULL, inode->i_private); | |
-} | |
- | |
-static const struct file_operations reset_fops = { | |
- .owner = THIS_MODULE, | |
- .open = reset_open, | |
- .write = reset, | |
- .llseek = seq_lseek, | |
- .release = single_release, | |
-}; | |
- | |
-void __devinit mipi_dsi_panel_create_debugfs(struct platform_device *pdev) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- struct device *dev; | |
- struct msm_fb_data_type *mfd; | |
- | |
- if (!pdev) { | |
- pr_err("%s: no device\n", __func__); | |
- return; | |
- } | |
- | |
- mfd = platform_get_drvdata(pdev); | |
- if (!mfd) { | |
- pr_err("%s: no mfd\n", __func__); | |
- return; | |
- } | |
- | |
- if (!mfd->panel_pdev) { | |
- pr_err("%s: no panel device\n", __func__); | |
- return; | |
- } | |
- dev = &mfd->panel_pdev->dev; | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data) { | |
- pr_err("%s: no dsi_data\n", __func__); | |
- return; | |
- } | |
- if (!&dev->kobj) { | |
- pr_err("%s: no &dev->kobj\n", __func__); | |
- return; | |
- } | |
- | |
- dev_info(dev, "%s: create folder %s\n", __func__, | |
- kobject_name(&dev->kobj)); | |
- dsi_data->dir = debugfs_create_dir(kobject_name(&dev->kobj), 0); | |
- if (!dsi_data->dir) { | |
- dev_err(dev, "%s: dbgfs create dir failed\n", __func__); | |
- } else { | |
- if (!debugfs_create_file("info", S_IRUGO, dsi_data->dir, mfd, | |
- &info_fops)) { | |
- dev_err(dev, "%s: failed to create dbgfs info file\n", | |
- __func__); | |
- return; | |
- } | |
- if (!debugfs_create_file("read", S_IWUSR, dsi_data->dir, mfd, | |
- &read_fops)) { | |
- dev_err(dev, "%s: failed to create dbgfs read file\n", | |
- __func__); | |
- return; | |
- } | |
- if (!debugfs_create_file("write", S_IWUSR, dsi_data->dir, mfd, | |
- &write_fops)) { | |
- dev_err(dev, "%s: failed to create dbgfs write file\n", | |
- __func__); | |
- return; | |
- } | |
- if (!debugfs_create_file("panels", S_IRUGO, dsi_data->dir, mfd, | |
- &panels_fops)) { | |
- dev_err(dev, "%s: failed to create dbgfs panels file\n", | |
- __func__); | |
- return; | |
- } | |
- if (!debugfs_create_file("result", S_IRUGO, dsi_data->dir, mfd, | |
- &result_fops)) { | |
- dev_err(dev, "%s: failed to create dbgfs result file\n", | |
- __func__); | |
- return; | |
- } | |
- if (!debugfs_create_file("reset", S_IWUSR, dsi_data->dir, mfd, | |
- &reset_fops)) { | |
- dev_err(dev, "%s: failed to create dbgfs reset file\n", | |
- __func__); | |
- return; | |
- } | |
- } | |
-} | |
- | |
-void __devexit mipi_dsi_panel_remove_debugfs(struct platform_device *pdev) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- | |
- if (!pdev || !&pdev->dev) { | |
- pr_err("%s: no device\n", __func__); | |
- return; | |
- } | |
- | |
- dsi_data = platform_get_drvdata(pdev); | |
- if (!dsi_data) { | |
- pr_err("%s: no dsi_data\n", __func__); | |
- return; | |
- } | |
- debugfs_remove_recursive(dsi_data->dir); | |
-} | |
diff --git a/drivers/video/msm/mipi_dsi_panel_driver.c b/drivers/video/msm/mipi_dsi_panel_driver.c | |
deleted file mode 100644 | |
index 40722e2d..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_driver.c | |
+++ /dev/null | |
@@ -1,1565 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_driver.c | |
- * | |
- * Copyright (C) 2012-2013 Sony Mobile Communications AB. | |
- * | |
- * Author: Johan Olson <[email protected]> | |
- * Author: Joakim Wesslen <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2; as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
-/* #define DEBUG */ | |
- | |
-#include <linux/kernel.h> | |
-#include <linux/device.h> | |
-#include <linux/delay.h> | |
-#include <linux/err.h> | |
-#include <linux/time.h> | |
-#include <linux/mutex.h> | |
- | |
-#include <video/mipi_dsi_panel.h> | |
-#include "msm_fb.h" | |
-#include "mdp4.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-#ifdef CONFIG_FB_MSM_MDP303 | |
-#define DSI_VIDEO_BASE 0xF0000 /* Taken from mdp_dma_dsi_video.c */ | |
-#else | |
-#define DSI_VIDEO_BASE 0xE0000 /* Taken from mdp4_overlay_dsi_video.c */ | |
-#endif | |
- | |
-#define DEFAULT_FPS_LOG_INTERVAL 100 | |
-#define DEFAULT_FPS_ARRAY_SIZE 120 | |
-#define NVRW_RETRY 10 | |
-#define NVRW_SEPARATOR_POS 2 | |
-#define NVRW_ONE_PARAM_SIZE 3 | |
-#define NVRW_DATA_SIZE ((NVRW_NUM_E6_PARAM + NVRW_NUM_E7_PARAM + \ | |
- NVRW_NUM_DE_PARAM) * NVRW_ONE_PARAM_SIZE) | |
-#define NVRW_PANEL_OFF_MSLEEP 100 | |
-#define NVRW_USEFUL_DE_PARAM 4 | |
-#define NVRW_ERASE_RES_OK 0xB9 | |
-#define NVRW_STATUS_RES_NG 0x00 | |
- | |
-#define calc_coltype_num(val, numpart, maxval)\ | |
- ((val >= maxval) ? numpart - 1 : val / (maxval / numpart)) | |
- | |
-struct fps_array { | |
- u32 frame_nbr; | |
- u32 time_delta; | |
-}; | |
-static u16 fps_array_cnt; | |
- | |
-static struct fps_data { | |
- struct mutex fps_lock; | |
- u32 log_interval; | |
- u32 interval_ms; | |
- struct timespec timestamp_last; | |
- u32 frame_counter_last; | |
- u32 frame_counter; | |
- u32 fpks; | |
- struct timespec fpks_ts_last; | |
- u16 fa_last_array_pos; | |
- struct fps_array fa[DEFAULT_FPS_ARRAY_SIZE]; | |
-} fpsd; | |
- | |
-static const struct mipi_dsi_phy_ctrl default_dsi_phy_db[] = { | |
- { | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0x78, 0x1a, 0x11, 0x00, 0x3e, 0x43, 0x16, 0x1d, | |
- 0x1d, 0x03, 0x04, 0xa0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0x8f, 0x31, 0xd9, 0x00, 0x50, 0x48, 0x63, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
- }, | |
-}; | |
- | |
-static struct msm_panel_info default_pinfo = { | |
- .type = MIPI_VIDEO_PANEL, | |
- .pdest = DISPLAY_1, | |
- .bpp = 24, | |
- | |
- .mipi.mode = DSI_VIDEO_MODE, | |
- .mipi.data_lane0 = TRUE, | |
- .mipi.data_lane1 = TRUE, | |
- .mipi.data_lane2 = TRUE, | |
- .mipi.data_lane3 = TRUE, | |
- .mipi.tx_eot_append = TRUE, | |
- .mipi.t_clk_post = 0x04, | |
- .mipi.t_clk_pre = 0x1B, | |
- .mipi.stream = 0, | |
- .mipi.mdp_trigger = DSI_CMD_TRIGGER_SW, | |
- .mipi.dma_trigger = DSI_CMD_TRIGGER_SW, | |
- .mipi.frame_rate = 60, | |
- .mipi.dsi_phy_db = | |
- (struct mipi_dsi_phy_ctrl *)default_dsi_phy_db, | |
-}; | |
- | |
-static struct mdp_pcc_cfg_data *color_calib; | |
- | |
-static u32 ts_diff_ms(struct timespec lhs, struct timespec rhs) | |
-{ | |
- struct timespec tdiff; | |
- s64 nsec; | |
- u32 msec; | |
- | |
- tdiff = timespec_sub(lhs, rhs); | |
- nsec = timespec_to_ns(&tdiff); | |
- msec = (u32)nsec; | |
- do_div(msec, NSEC_PER_MSEC); | |
- | |
- return msec; | |
-} | |
- | |
-static void update_fps_data(struct fps_data *fps) | |
-{ | |
- if (mutex_trylock(&fps->fps_lock)) { | |
- u32 fpks = 0; | |
- u32 ms_since_last = 0; | |
- u32 num_frames; | |
- struct timespec tlast = fps->timestamp_last; | |
- struct timespec tnow; | |
- u32 msec; | |
- | |
- getrawmonotonic(&tnow); | |
- msec = ts_diff_ms(tnow, tlast); | |
- fps->timestamp_last = tnow; | |
- | |
- fps->interval_ms = msec; | |
- fps->frame_counter++; | |
- num_frames = fps->frame_counter - fps->frame_counter_last; | |
- | |
- fps->fa[fps_array_cnt].frame_nbr = fps->frame_counter; | |
- fps->fa[fps_array_cnt].time_delta = msec; | |
- fps->fa_last_array_pos = fps_array_cnt; | |
- fps_array_cnt++; | |
- if (fps_array_cnt >= DEFAULT_FPS_ARRAY_SIZE) | |
- fps_array_cnt = 0; | |
- | |
- ms_since_last = ts_diff_ms(tnow, fps->fpks_ts_last); | |
- if (num_frames > 1 && ms_since_last >= fps->log_interval) { | |
- fpks = (num_frames * 1000000) / ms_since_last; | |
- fps->fpks_ts_last = tnow; | |
- fps->frame_counter_last = fps->frame_counter; | |
- fps->fpks = fpks; | |
- } | |
- mutex_unlock(&fps->fps_lock); | |
- } | |
-} | |
- | |
-static void mipi_dsi_panel_fps_array_clear(struct fps_data *fps) | |
-{ | |
- memset(fps->fa, 0, sizeof(fps->fa)); | |
- fps_array_cnt = 0; | |
-} | |
- | |
-static void mipi_dsi_panel_fps_data_init(struct fps_data *fps) | |
-{ | |
- fps->frame_counter = 0; | |
- fps->frame_counter_last = 0; | |
- fps->log_interval = DEFAULT_FPS_LOG_INTERVAL; | |
- fps->fpks = 0; | |
- fps->fa_last_array_pos = 0; | |
- getrawmonotonic(&fps->timestamp_last); | |
- mutex_init(&fps->fps_lock); | |
-} | |
- | |
-void mipi_dsi_panel_fps_data_update(struct msm_fb_data_type *mfd) | |
-{ | |
- /* Only count fps on primary display */ | |
- if (mfd->index == 0) | |
- update_fps_data(&fpsd); | |
-} | |
- | |
-static bool is_read_cmd(int dtype) | |
-{ | |
- return (dtype == DTYPE_DCS_READ || dtype == DTYPE_GEN_READ || | |
- dtype == DTYPE_GEN_READ1 || dtype == DTYPE_GEN_READ2); | |
-} | |
- | |
-static int panel_execute_cmd(struct msm_fb_data_type *mfd, | |
- struct mipi_dsi_data *dsi_data, | |
- const struct panel_cmd *pcmd, | |
- int nbr_bytes_to_read) | |
-{ | |
- struct device *dev = &mfd->panel_pdev->dev; | |
- int n; | |
- int ret = 0; | |
- | |
- if (!pcmd) { | |
- dev_err(dev, "%s: no command\n", __func__); | |
- ret = -EINVAL; | |
- goto exit; | |
- } | |
- | |
- for (n = 0; ; ++n) | |
- switch (pcmd[n].type) { | |
- case CMD_END: | |
- dev_dbg(dev, "CMD_END\n"); | |
- goto exit; | |
- break; | |
- case CMD_WAIT_MS: | |
- dev_dbg(dev, "%s: CMD_WAIT_MS = %d ms\n", | |
- __func__, pcmd[n].payload.data); | |
- msleep(pcmd[n].payload.data); | |
- break; | |
- case CMD_DSI: | |
- dev_dbg(dev, "%s: CMD_DSI\n", __func__); | |
- /* Sufficient to check if first cmd is a read, then | |
- * it is impled that all are of the same type */ | |
- if (is_read_cmd( | |
- pcmd[n].payload.dsi_payload.dsi[0].dtype)) { | |
- | |
- dev_dbg(dev, "%s: CMD_DSI READ\n", __func__); | |
- mipi_dsi_cmds_rx(mfd, &dsi_data->tx_buf, | |
- &dsi_data->rx_buf, | |
- pcmd[n].payload.dsi_payload.dsi, | |
- nbr_bytes_to_read); | |
- } else { | |
- mipi_dsi_cmds_tx(&dsi_data->tx_buf, | |
- pcmd[n].payload.dsi_payload.dsi, | |
- pcmd[n].payload.dsi_payload.cnt); | |
- } | |
- break; | |
- case CMD_RESET: | |
- dev_dbg(dev, "%s: CMD_RESET lvl=%d\n", __func__, | |
- pcmd[n].payload.data); | |
- if (dsi_data->lcd_reset) | |
- ret = dsi_data->lcd_reset(pcmd[n].payload.data); | |
- if (ret) | |
- goto exit; | |
- break; | |
- case CMD_PLATFORM: | |
- dev_dbg(dev, "%s: CMD_PLATFORM enable=%d\n", __func__, | |
- pcmd[n].payload.data); | |
- if (dsi_data->lcd_power) | |
- ret = dsi_data->lcd_power(pcmd[n].payload.data); | |
- if (ret) | |
- goto exit; | |
- break; | |
- default: | |
- dev_err(dev, "%s: Unknown command type!\n", | |
- __func__); | |
- } | |
-exit: | |
- return ret; | |
-} | |
- | |
-static int panel_id_reg_check(struct msm_fb_data_type *mfd, | |
- struct mipi_dsi_data *dsi_data, | |
- const struct panel *panel) | |
-{ | |
- struct device *dev = &mfd->panel_pdev->dev; | |
- int i; | |
- int ret = 0; | |
- | |
- dev_dbg(dev, "%s\n", __func__); | |
- | |
- mutex_lock(&mfd->dma->ov_mutex); | |
- ret = panel_execute_cmd(mfd, dsi_data, panel->pctrl->read_id, | |
- panel->id_num); | |
- mutex_unlock(&mfd->dma->ov_mutex); | |
- if (ret) { | |
- dev_err(dev, "%s: read id failed\n", __func__); | |
- goto exit; | |
- } | |
- | |
- for (i = 0; i < panel->id_num; i++) { | |
- if ((i >= dsi_data->rx_buf.len) || | |
- ((dsi_data->rx_buf.data[i] != panel->id[i]) && | |
- (panel->id[i] != PANEL_SKIP_ID))) { | |
- ret = -ENODEV; | |
- goto exit; | |
- } | |
- } | |
-exit: | |
- return ret; | |
-} | |
- | |
-static int panel_update_config(struct platform_device *pdev) | |
-{ | |
- struct msm_fb_data_type *mfd; | |
- struct fb_info *fbi; | |
- struct msm_panel_info *pinfo; | |
- struct mipi_panel_info *mipi; | |
- uint8 lanes = 0, bpp; | |
- uint32 h_period, v_period, dsi_pclk_rate; | |
- | |
- dev_dbg(&pdev->dev, "%s: pdev = %p, pdev->name = %s\n", __func__, | |
- pdev, pdev->name); | |
- | |
- mfd = platform_get_drvdata(pdev); | |
- pinfo = &mfd->panel_info; | |
- fbi = mfd->fbi; | |
- fbi->var.pixclock = pinfo->clk_rate; | |
- fbi->var.left_margin = pinfo->lcdc.h_back_porch; | |
- fbi->var.right_margin = pinfo->lcdc.h_front_porch; | |
- fbi->var.upper_margin = pinfo->lcdc.v_back_porch; | |
- fbi->var.lower_margin = pinfo->lcdc.v_front_porch; | |
- fbi->var.hsync_len = pinfo->lcdc.h_pulse_width; | |
- fbi->var.vsync_len = pinfo->lcdc.v_pulse_width; | |
- | |
- mipi = &pinfo->mipi; | |
- | |
- if (mipi->data_lane3) | |
- lanes += 1; | |
- if (mipi->data_lane2) | |
- lanes += 1; | |
- if (mipi->data_lane1) | |
- lanes += 1; | |
- if (mipi->data_lane0) | |
- lanes += 1; | |
- | |
- switch (mipi->dst_format) { | |
- case DSI_CMD_DST_FORMAT_RGB888: | |
- case DSI_VIDEO_DST_FORMAT_RGB888: | |
- case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE: | |
- bpp = 3; | |
- break; | |
- case DSI_CMD_DST_FORMAT_RGB565: | |
- case DSI_VIDEO_DST_FORMAT_RGB565: | |
- bpp = 2; | |
- break; | |
- default: | |
- bpp = 3; /* Default format set to RGB888 */ | |
- break; | |
- } | |
- | |
- if (pinfo->type == MIPI_VIDEO_PANEL && !pinfo->clk_rate) { | |
- h_period = pinfo->lcdc.h_pulse_width | |
- + pinfo->lcdc.h_back_porch | |
- + pinfo->xres | |
- + pinfo->lcdc.h_front_porch; | |
- | |
- v_period = pinfo->lcdc.v_pulse_width | |
- + pinfo->lcdc.v_back_porch | |
- + pinfo->yres | |
- + pinfo->lcdc.v_front_porch; | |
- | |
- if (lanes > 0) { | |
- pinfo->clk_rate = | |
- ((h_period * v_period * (mipi->frame_rate) * bpp * 8) | |
- / lanes); | |
- } else { | |
- dev_err(&pdev->dev, | |
- "%s: forcing mipi_dsi lanes to 1\n", __func__); | |
- pinfo->clk_rate = | |
- (h_period * v_period | |
- * (mipi->frame_rate) * bpp * 8); | |
- } | |
- } | |
- pll_divider_config.clk_rate = pinfo->clk_rate; | |
- | |
- mipi_dsi_clk_div_config(bpp, lanes, &dsi_pclk_rate); | |
- | |
- if ((dsi_pclk_rate < 3300000) || (dsi_pclk_rate > 200000000)) | |
- dsi_pclk_rate = 35000000; | |
- mipi->dsi_pclk_rate = dsi_pclk_rate; | |
- | |
- return 0; | |
-} | |
- | |
-static void mipi_dsi_update_lane_cfg(const struct mipi_dsi_lane_cfg *plncfg) | |
-{ | |
- int i, j, ln_offset; | |
- | |
- ln_offset = 0x300; | |
- for (i = 0; i < MIPI_DSI_NUM_PHY_LN; i++) { | |
- /* DSI1_DSIPHY_LN_CFG */ | |
- for (j = 0; j < 3; j++) | |
- MIPI_OUTP(MIPI_DSI_BASE + ln_offset + j * 4, | |
- plncfg->ln_cfg[i][j]); | |
- /* DSI1_DSIPHY_LN_TEST_DATAPATH */ | |
- MIPI_OUTP(MIPI_DSI_BASE + ln_offset + 0x0c, | |
- plncfg->ln_dpath[i]); | |
- /* DSI1_DSIPHY_LN_TEST_STR */ | |
- for (j = 0; j < 2; j++) | |
- MIPI_OUTP(MIPI_DSI_BASE + ln_offset + 0x14 + j * 4, | |
- plncfg->ln_str[i][j]); | |
- | |
- ln_offset += 0x40; | |
- } | |
- | |
- /* DSI1_DSIPHY_LNCK_CFG */ | |
- for (i = 0; i < 3; i++) | |
- MIPI_OUTP(MIPI_DSI_BASE + 0x0400 + i * 4, | |
- plncfg->lnck_cfg[i]); | |
- /* DSI1_DSIPHY_LNCK_TEST_DATAPATH */ | |
- MIPI_OUTP(MIPI_DSI_BASE + 0x040c, plncfg->lnck_dpath); | |
- /* DSI1_DSIPHY_LNCK_TEST_STR */ | |
- for (i = 0; i < 2; i++) | |
- MIPI_OUTP(MIPI_DSI_BASE + 0x0414 + i * 4, | |
- plncfg->lnck_str[i]); | |
-} | |
- | |
-static int panel_sleep_out_display_off(struct msm_fb_data_type *mfd, | |
- struct mipi_dsi_data *dsi_data) | |
-{ | |
- struct device *dev = &mfd->panel_pdev->dev; | |
- int ret = 0; | |
- | |
- dev_dbg(dev, "%s: Execute display_init\n", __func__); | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- dsi_data->panel->pctrl->display_init, 0); | |
- if (ret) | |
- dev_err(&mfd->panel_pdev->dev, "display_init failed\n"); | |
- return ret; | |
-} | |
- | |
-static int panel_display_on(struct msm_fb_data_type *mfd, | |
- struct mipi_dsi_data *dsi_data) | |
-{ | |
- struct device *dev = &mfd->panel_pdev->dev; | |
- int ret = 0; | |
- | |
- dev_dbg(dev, "%s: Execute display on\n", __func__); | |
- mipi_set_tx_power_mode(0); | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- dsi_data->panel->pctrl->display_on, 0); | |
- if (ret) { | |
- dev_err(dev, "%s: display_on failed\n", __func__); | |
- goto exit; | |
- } | |
- dev_info(dev, "%s: DISPLAY_ON sent\n", __func__); | |
-exit: | |
- return ret; | |
-} | |
- | |
-static int panel_on(struct platform_device *pdev) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- struct msm_fb_data_type *mfd; | |
- struct device *dev; | |
- bool skip_display_on = false; | |
- int ret = 0; | |
- | |
- mfd = platform_get_drvdata(pdev); | |
- if (!mfd) { | |
- ret = -ENODEV; | |
- goto exit; | |
- } | |
- if (mfd->key != MFD_KEY) { | |
- ret = -EINVAL; | |
- goto exit; | |
- } | |
- | |
- dev = &mfd->panel_pdev->dev; | |
- dev_dbg(dev, "%s\n", __func__); | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data) { | |
- ret = -ENODEV; | |
- goto exit; | |
- } | |
- | |
- /* Clear the buffer on resume */ | |
- mutex_lock(&fpsd.fps_lock); | |
- mipi_dsi_panel_fps_array_clear(&fpsd); | |
- mutex_unlock(&fpsd.fps_lock); | |
- | |
- mutex_lock(&dsi_data->lock); | |
- dev_dbg(dev, "%s: state = %d\n", __func__, dsi_data->panel_state); | |
- | |
- if (!dsi_data->panel_detected) | |
- goto unlock_and_exit; | |
- | |
- if (!dsi_data->panel) | |
- goto unlock_and_exit; | |
- | |
- if (dsi_data->panel_state == PANEL_OFF || | |
- dsi_data->panel_state == DEBUGFS_POWER_OFF) { | |
- if (dsi_data->pcc_config) | |
- mdp4_pcc_cfg(dsi_data->pcc_config); | |
- if (dsi_data->panel && dsi_data->panel->plncfg) | |
- mipi_dsi_update_lane_cfg(dsi_data->panel->plncfg); | |
- | |
- dev_dbg(dev, "%s: call power on\n", __func__); | |
- if (dsi_data->lcd_power) { | |
- ret = dsi_data->lcd_power(TRUE); | |
- if (ret) | |
- goto unlock_and_exit; | |
- } | |
- if (dsi_data->panel_state == DEBUGFS_POWER_OFF) | |
- dsi_data->panel_state = DEBUGFS_POWER_ON; | |
- } | |
- | |
- if (dsi_data->panel_state == DEBUGFS_POWER_ON) { | |
- dev_dbg(dev, "%s: debugfs state, don't exit sleep\n", __func__); | |
- goto unlock_and_exit; | |
- } | |
- if (!dsi_data->nvrw_panel_detective) | |
- goto unlock_and_exit; | |
- | |
- if (dsi_data->panel_state == PANEL_OFF) { | |
- ret = panel_sleep_out_display_off(mfd, dsi_data); | |
- if (ret) | |
- goto unlock_and_exit; | |
- if (dsi_data->panel_data.controller_on_panel_on) | |
- skip_display_on = true; | |
- dsi_data->panel_state = PANEL_SLEEP_OUT; | |
- } | |
- | |
- /* Call display on depending on if it is setup to receive video */ | |
- /* data data before display on or not */ | |
- if (!skip_display_on && dsi_data->panel_state == PANEL_SLEEP_OUT) { | |
- ret = panel_display_on(mfd, dsi_data); | |
- if (ret) | |
- goto unlock_and_exit; | |
- dsi_data->panel_state = PANEL_ON; | |
- } | |
-unlock_and_exit: | |
- mutex_unlock(&dsi_data->lock); | |
-exit: | |
- return ret; | |
-} | |
- | |
-static int panel_off(struct platform_device *pdev) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- struct msm_fb_data_type *mfd; | |
- struct device *dev; | |
- int ret = 0; | |
- | |
- mfd = platform_get_drvdata(pdev); | |
- if (!mfd) { | |
- ret = -ENODEV; | |
- goto exit; | |
- } | |
- if (mfd->key != MFD_KEY) { | |
- ret = -EINVAL; | |
- goto exit; | |
- } | |
- | |
- dev = &mfd->panel_pdev->dev; | |
- dev_dbg(dev, "%s\n", __func__); | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data) { | |
- ret = -ENODEV; | |
- goto exit; | |
- } | |
- | |
- mutex_lock(&dsi_data->lock); | |
- | |
- if (!dsi_data->panel_detected) { | |
- /* We rely on that we have detected a panel the first time | |
- this function is called */ | |
- dsi_data->panel_detected = true; | |
- goto unlock_and_exit; | |
- } | |
- | |
- if (dsi_data->panel_state == DEBUGFS_POWER_ON) { | |
- dev_dbg(dev, "%s: debugfs state, power off\n", __func__); | |
- goto power_off; | |
- } | |
- | |
- if (!dsi_data->panel) | |
- goto unlock_and_exit; | |
- | |
- if (dsi_data->panel->disable_dsi_timing_genarator_at_off) { | |
- MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); | |
- msleep(20); | |
- } | |
- | |
- dev_dbg(dev, "%s: Execute display off\n", __func__); | |
- /* Set to OFF even if commands fail below */ | |
- dsi_data->panel_state = PANEL_OFF; | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- dsi_data->panel->pctrl->display_off, 0); | |
- if (ret) { | |
- dev_err(dev, "%s: display_off failed\n", __func__); | |
- goto unlock_and_exit; | |
- } | |
- dev_info(dev, "%s: DISPLAY_OFF sent\n", __func__); | |
-power_off: | |
- if (dsi_data->lcd_power) | |
- ret = dsi_data->lcd_power(FALSE); | |
-unlock_and_exit: | |
- mutex_unlock(&dsi_data->lock); | |
-exit: | |
- return ret; | |
-} | |
- | |
-static struct msm_panel_info *detect_panel(struct msm_fb_data_type *mfd) | |
-{ | |
- int i; | |
- int ret; | |
- struct mipi_dsi_data *dsi_data; | |
- struct msm_fb_panel_data *pdata = NULL; | |
- struct device *dev; | |
- const struct panel *default_panel = NULL; | |
- | |
- dev = &mfd->panel_pdev->dev; | |
- dev_dbg(dev, "%s\n", __func__); | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data || !dsi_data->panels[0]) { | |
- dev_err(dev, "%s: Failed to detect panel, no panel data\n", | |
- __func__); | |
- return NULL; | |
- } | |
- | |
- mutex_lock(&dsi_data->lock); | |
- mipi_dsi_op_mode_config(DSI_CMD_MODE); | |
- for (i = 0; dsi_data->panels[i]; i++) { | |
- ret = panel_id_reg_check(mfd, dsi_data, dsi_data->panels[i]); | |
- if (dsi_data->panels[i]->id[0] == PANEL_SKIP_ID | |
- && dsi_data->panels[i]->id_num == 1) | |
- default_panel = dsi_data->panels[i]; | |
- if (!ret && !(dsi_data->panels[i]->id[0] == PANEL_SKIP_ID | |
- && dsi_data->panels[i]->id_num == 1)) | |
- break; | |
- } | |
- | |
- if (dsi_data->panels[i]) { | |
- dsi_data->panel = dsi_data->panels[i]; | |
- dsi_data->nvrw_panel_detective = true; | |
- dev_info(dev, "%s: Found panel: %s\n", __func__, | |
- dsi_data->panel->name); | |
- } else { | |
- if (default_panel) | |
- dsi_data->panel = default_panel; | |
- dev_warn(dev, "%s: Failed to detect panel!\n", __func__); | |
- } | |
- | |
- if (!dsi_data->panel) { | |
- mutex_unlock(&dsi_data->lock); | |
- return NULL; | |
- } | |
- | |
- if (dsi_data->panel->send_video_data_before_display_on) { | |
- dev_info(dev, "%s: send_video_data_before_display_on\n", | |
- __func__); | |
- dsi_data->panel_data.controller_on_panel_on = panel_on; | |
- dsi_data->panel_data.power_on_panel_at_pan = 0; | |
- /* Also need to update platform data since that is */ | |
- /* used in msm_fb */ | |
- pdata = mfd->pdev->dev.platform_data; | |
- pdata->controller_on_panel_on = panel_on; | |
- pdata->power_on_panel_at_pan = 0; | |
- } | |
- | |
- dsi_data->panel_data.panel_info = | |
- *dsi_data->panel->pctrl->get_panel_info(); | |
- dsi_data->panel_data.panel_info.width = dsi_data->panel->width; | |
- dsi_data->panel_data.panel_info.height = dsi_data->panel->height; | |
- dsi_data->panel_data.panel_info.mipi.dsi_pclk_rate = | |
- mfd->panel_info.mipi.dsi_pclk_rate; | |
- | |
- mipi_dsi_op_mode_config(dsi_data->panel_data.panel_info.mipi.mode); | |
- | |
- mutex_unlock(&dsi_data->lock); | |
- return &dsi_data->panel_data.panel_info; | |
-} | |
- | |
-static int find_subdivision_area(int u_data, int v_data) | |
-{ | |
- int row, col; | |
- int num_area = 0; | |
- | |
- if (v_data < CLR_SUB_AREA_V_START || CLR_RESOLUTION <= v_data) | |
- return 0; | |
- | |
- row = v_data / CLR_SUB_V_BLOCK_HEIGHT - 1; | |
- for (col = 0; col < CLR_SUB_COL_MAX; col++) { | |
- if (clr_sub_tbl[row][col].sub_area == 0) | |
- break; | |
- if (clr_sub_tbl[row][col].u_min <= u_data | |
- && u_data <= clr_sub_tbl[row][col].u_max) { | |
- num_area = clr_sub_tbl[row][col].sub_area; | |
- break; | |
- } | |
- } | |
- return num_area; | |
-} | |
- | |
-static int get_pcc_data(struct msm_fb_data_type *mfd) | |
-{ | |
- int ret; | |
- struct mipi_dsi_data *dsi_data; | |
- struct device *dev; | |
- enum color_type color_type = 0; | |
- int u_data, v_data; | |
- int u, v; | |
- int num_area = 0; | |
- const struct mdp_pcc_cfg_rgb *cfg_rgb = NULL; | |
- | |
- dev = &mfd->panel_pdev->dev; | |
- dev_dbg(dev, "%s\n", __func__); | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data) { | |
- dev_err(dev, "%s: Failed to get pcc data\n", __func__); | |
- goto exit; | |
- } | |
- if (!dsi_data->panel->color_correction_tbl) | |
- goto exit; | |
- | |
- mipi_dsi_op_mode_config(DSI_CMD_MODE); | |
- mutex_lock(&mfd->dma->ov_mutex); | |
- if (dsi_data->panel->id_num >= 2 && | |
- (dsi_data->panel->id[0] == PANEL_SKIP_ID && | |
- dsi_data->panel->id[1] == PANEL_SKIP_ID)) | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- dsi_data->panel->pctrl->read_id, | |
- dsi_data->panel->id_num); | |
- else | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- dsi_data->panel->pctrl->read_color, | |
- CLR_REG_DATA_NUM); | |
- mutex_unlock(&mfd->dma->ov_mutex); | |
- mipi_dsi_op_mode_config(dsi_data->panel_data.panel_info.mipi.mode); | |
- if (ret) { | |
- dev_err(dev, "%s: read color type failed\n", __func__); | |
- goto exit; | |
- } | |
- | |
- u_data = ((dsi_data->rx_buf.data[0] & 0x0F) << 2) | | |
- ((dsi_data->rx_buf.data[1] >> 6) & 0x03); | |
- v_data = (dsi_data->rx_buf.data[1] & 0x3F); | |
- if (u_data == 0 && v_data == 0) | |
- goto exit; | |
- | |
- if (dsi_data->panel->color_subdivision_tbl) | |
- num_area = find_subdivision_area(u_data, v_data); | |
- if (num_area > 0) { | |
- cfg_rgb = &dsi_data->panel->color_subdivision_tbl[num_area - 1]; | |
- } else { | |
- u = calc_coltype_num(u_data, CLR_NUM_PART, CLR_RESOLUTION); | |
- v = calc_coltype_num(v_data, CLR_NUM_PART, CLR_RESOLUTION); | |
- color_type = panel_color_type[v][u]; | |
- if (color_type != CLR15_WHT) | |
- cfg_rgb = &dsi_data->panel-> | |
- color_correction_tbl[color_type]; | |
- } | |
- | |
- if (cfg_rgb != NULL && color_calib == NULL) { | |
- color_calib = kzalloc(sizeof(struct mdp_pcc_cfg_data), | |
- GFP_KERNEL); | |
- if (color_calib == NULL) | |
- return -ENOMEM; | |
- | |
- color_calib->block = MDP_BLOCK_DMA_P; | |
- color_calib->ops = 0x05; | |
- color_calib->r.r = cfg_rgb->r; | |
- color_calib->g.g = cfg_rgb->g; | |
- color_calib->b.b = cfg_rgb->b; | |
- dsi_data->pcc_config = color_calib; | |
- pcc_cfg_ptr = color_calib; | |
- | |
- dev_dbg(dev, "%s (%d): r=%x g=%x b=%x area=%d ct=%d ud=%d vd=%d", | |
- __func__, __LINE__, cfg_rgb->r, cfg_rgb->g, cfg_rgb->b, | |
- num_area, color_type, u_data, v_data); | |
- } | |
- | |
-exit: | |
- return 0; | |
-} | |
- | |
-#ifdef CONFIG_FB_MSM_RECOVER_PANEL | |
-static struct msm_panel_info *nvm_detect_panel( | |
- struct msm_fb_data_type *mfd, char *id, int id_num) | |
-{ | |
- struct mipi_dsi_data *dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- struct msm_fb_panel_data *pdata; | |
- struct device *dev; | |
- int i, n; | |
- int min; | |
- | |
- dev = &mfd->panel_pdev->dev; | |
- dev_dbg(dev, "%s\n", __func__); | |
- for (i = 0; dsi_data->panels[i]; i++) { | |
- if (dsi_data->panels[i]->id[0] == PANEL_SKIP_ID | |
- && dsi_data->panels[i]->id_num == 1) | |
- continue; /* skip default panel */ | |
- | |
- min = MIN(dsi_data->panels[i]->id_num, id_num); | |
- for (n = 0; n < min; n++) | |
- if (dsi_data->panels[i]->id[n] != id[n] && | |
- dsi_data->panels[i]->id[n] != PANEL_SKIP_ID) | |
- break; | |
- if (n >= min) | |
- break; | |
- } | |
- if (!dsi_data->panels[i]) | |
- return NULL; | |
- | |
- dsi_data->panel = dsi_data->panels[i]; | |
- if (dsi_data->panel->send_video_data_before_display_on) { | |
- dsi_data->panel_data.controller_on_panel_on = panel_on; | |
- dsi_data->panel_data.power_on_panel_at_pan = 0; | |
- | |
- pdata = mfd->pdev->dev.platform_data; | |
- pdata->controller_on_panel_on = panel_on; | |
- pdata->power_on_panel_at_pan = 0; | |
- } | |
- dev_info(dev, "%s: Found panel: %s\n", __func__, dsi_data->panel->name); | |
- | |
- dsi_data->panel_data.panel_info = | |
- *dsi_data->panel->pctrl->get_panel_info(); | |
- dsi_data->panel_data.panel_info.width = dsi_data->panel->width; | |
- dsi_data->panel_data.panel_info.height = dsi_data->panel->height; | |
- dsi_data->panel_data.panel_info.mipi.dsi_pclk_rate = | |
- mfd->panel_info.mipi.dsi_pclk_rate; | |
- | |
- return &dsi_data->panel_data.panel_info; | |
-} | |
- | |
-static int nvm_update_panel(struct msm_fb_data_type *mfd, | |
- const char *buf, size_t count) | |
-{ | |
- struct msm_panel_info *pinfo; | |
- const int num_ssv_id = NVRW_NUM_E6_PARAM * NVRW_ONE_PARAM_SIZE; | |
- char ssv_id[num_ssv_id]; | |
- char *pos = ssv_id; | |
- char id[NVRW_NUM_E6_PARAM]; | |
- int n, rc = -EINVAL; | |
- ulong dat; | |
- | |
- if (count < NVRW_DATA_SIZE - 1) | |
- goto err_exit; | |
- | |
- buf += (NVRW_NUM_E7_PARAM + NVRW_NUM_DE_PARAM) * NVRW_ONE_PARAM_SIZE; | |
- memcpy(ssv_id, buf, num_ssv_id - 1); | |
- ssv_id[num_ssv_id - 1] = 0; | |
- | |
- for (n = 0; n < NVRW_NUM_E6_PARAM; n++, pos += NVRW_ONE_PARAM_SIZE) { | |
- pos[NVRW_SEPARATOR_POS] = 0; | |
- rc = kstrtoul(pos, 16, &dat); | |
- if (rc < 0) | |
- goto err_exit; | |
- id[n] = dat & 0xff; | |
- } | |
- pinfo = nvm_detect_panel(mfd, id, NVRW_NUM_E6_PARAM); | |
- if (!pinfo) | |
- goto err_exit; | |
- | |
- mutex_lock(&mfd->power_lock); | |
- rc = panel_next_off(mfd->pdev); | |
- if (rc) | |
- goto err_exit; | |
- mfd->panel_info = *pinfo; | |
- panel_update_config(mfd->pdev); | |
- rc = panel_next_on(mfd->pdev); | |
- mutex_unlock(&mfd->power_lock); | |
- | |
-err_exit: | |
- return rc; | |
-} | |
-#endif | |
- | |
-static int nvm_override_param(struct dsi_cmd_payload *pcmdp, char reg, | |
- int num_param, char *buf) | |
-{ | |
- ulong dat; | |
- int i, n; | |
- int cnt = 0; | |
- int rc; | |
- | |
- for (i = 0; i < pcmdp->cnt; i++) { | |
- if (pcmdp->dsi[i].payload[0] == reg) | |
- break; | |
- } | |
- if (i >= pcmdp->cnt) | |
- goto err_exit; | |
- for (n = 0; n < num_param; n++, buf += NVRW_ONE_PARAM_SIZE, cnt++) { | |
- buf[NVRW_SEPARATOR_POS] = 0; | |
- rc = kstrtoul(buf, 16, &dat); | |
- if (rc < 0) | |
- goto err_exit; | |
- pcmdp->dsi[i].payload[n + 1] = dat & 0xff; | |
- } | |
- return cnt; | |
-err_exit: | |
- return 0; | |
-} | |
- | |
-static int nvm_override_data(struct msm_fb_data_type *mfd, | |
- const char *buf, int count) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- struct dsi_cmd_payload *pcmdp; | |
- char work[NVRW_DATA_SIZE]; | |
- char *pos = work; | |
- int cnt; | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- if (!dsi_data->panel->pnvrw_ctl) | |
- goto err_exit; | |
- if (count < NVRW_DATA_SIZE - 1) | |
- goto err_exit; | |
- memcpy(work, buf, NVRW_DATA_SIZE - 1); | |
- work[NVRW_DATA_SIZE - 1] = 0; | |
- /* override E7 register data */ | |
- pcmdp = &dsi_data->panel->pnvrw_ctl->nvm_write_rsp->payload.dsi_payload; | |
- cnt = nvm_override_param(pcmdp, 0xE7, NVRW_NUM_E7_PARAM, pos); | |
- if (cnt == 0) { | |
- pr_err("%s:Override failure of the E7 parameters.\n", __func__); | |
- goto err_exit; | |
- } | |
- pos += cnt * NVRW_ONE_PARAM_SIZE; | |
- /* override DE register data */ | |
- pcmdp = &dsi_data->panel->pnvrw_ctl-> | |
- nvm_write_user->payload.dsi_payload; | |
- cnt = nvm_override_param(pcmdp, 0xDE, NVRW_NUM_DE_PARAM, pos); | |
- if (cnt == 0) { | |
- pr_err("%s:Override failure of the DE parameters.\n", __func__); | |
- goto err_exit; | |
- } | |
- pos += cnt * NVRW_ONE_PARAM_SIZE; | |
- /* override E6 register data */ | |
- cnt = nvm_override_param(pcmdp, 0xE6, NVRW_NUM_E6_PARAM, pos); | |
- if (cnt == 0) { | |
- pr_err("%s:Override failure of the E6 parameters.\n", __func__); | |
- goto err_exit; | |
- } | |
- | |
- return 0; | |
-err_exit: | |
- return -EINVAL; | |
-} | |
- | |
-static int nvm_read(struct msm_fb_data_type *mfd, char *buf) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- struct dsi_nvm_rewrite_ctl *pnvrw_ctl; | |
- int n; | |
- int len = 0; | |
- char *pos = buf; | |
- int ret; | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- pnvrw_ctl = dsi_data->panel->pnvrw_ctl; | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_mcap, 0); | |
- if (ret) { | |
- pr_err("%s: nvm_mcap failed\n", __func__); | |
- goto err_exit; | |
- } | |
- | |
- /* E7 register data */ | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_read_rsp, NVRW_NUM_E7_PARAM); | |
- if (ret) { | |
- pr_err("%s: nvm_read_rsp failed\n", __func__); | |
- goto err_exit; | |
- } | |
- for (n = 0; n < NVRW_NUM_E7_PARAM; n++) | |
- len += snprintf(pos + len, PAGE_SIZE - len, "%02x ", | |
- dsi_data->rx_buf.data[n]); | |
- | |
- /* DE register data */ | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_read_vcomdc, NVRW_NUM_DE_PARAM); | |
- if (ret) { | |
- pr_err("%s: nvm_read_vcomdc failed\n", __func__); | |
- goto err_exit; | |
- } | |
- for (n = 0; n < NVRW_NUM_DE_PARAM; n++) { | |
- if (n < NVRW_USEFUL_DE_PARAM) | |
- len += snprintf(pos + len, PAGE_SIZE - len, "%02x ", | |
- dsi_data->rx_buf.data[n]); | |
- else | |
- len += snprintf(pos + len, PAGE_SIZE - len, "00 "); | |
- } | |
- | |
- /* E6 register data */ | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_read_ddb_write, NVRW_NUM_E6_PARAM); | |
- if (ret) { | |
- pr_err("%s: nvm_read_vcomdc failed\n", __func__); | |
- goto err_exit; | |
- } | |
- for (n = 0; n < NVRW_NUM_E6_PARAM; n++) | |
- len += snprintf(pos + len, PAGE_SIZE - len, "%02x ", | |
- dsi_data->rx_buf.data[n]); | |
- *(pos + len) = 0; | |
- | |
- panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_mcap_lock, 0); | |
- | |
- return len; | |
-err_exit: | |
- return 0; | |
-} | |
- | |
-static int nvm_erase(struct msm_fb_data_type *mfd) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- struct dsi_nvm_rewrite_ctl *pnvrw_ctl; | |
- int i; | |
- int ret; | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- pnvrw_ctl = dsi_data->panel->pnvrw_ctl; | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_disp_off, 0); | |
- if (ret) { | |
- pr_err("%s: nvm_disp_off failed\n", __func__); | |
- goto err_exit; | |
- } | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_mcap, 0); | |
- if (ret) { | |
- pr_err("%s: nvm_mcap failed\n", __func__); | |
- goto err_exit; | |
- } | |
- | |
- for (i = 0; i < NVRW_RETRY; i++) { | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_open, 0); | |
- if (ret) | |
- pr_err("%s: nvm_open failed\n", __func__); | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_write_rsp, 0); | |
- if (ret) | |
- pr_err("%s: nvm_write_rsp failed\n", __func__); | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_write_user, 0); | |
- if (ret) | |
- pr_err("%s: nvm_write_user failed\n", __func__); | |
- | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_erase, 0); | |
- if (ret) | |
- pr_err("%s: nvm_erase failed\n", __func__); | |
- | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_erase_res, 1); | |
- if (ret) | |
- pr_err("%s: nvm_erase_res failed\n", __func__); | |
- if (dsi_data->rx_buf.data[0] != NVRW_ERASE_RES_OK) { | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_disp_off, 0); | |
- if (ret) | |
- pr_err("%s: nvm_disp_off failed\n", __func__); | |
- pr_err("%s (%d): RETRY %d", __func__, __LINE__, i+1); | |
- dsi_data->nvrw_retry_cnt++; | |
- continue; | |
- } | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_close, 0); | |
- if (ret) | |
- pr_err("%s: nvm_close failed\n", __func__); | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_status, 1); | |
- if (ret) | |
- pr_err("%s: nvm_status failed\n", __func__); | |
- if (dsi_data->rx_buf.data[0] == NVRW_STATUS_RES_NG) { | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_disp_off, 1); | |
- if (ret) | |
- pr_err("%s: nvm_disp_off failed\n", __func__); | |
- pr_err("%s (%d): RETRY %d", __func__, __LINE__, i+1); | |
- dsi_data->nvrw_retry_cnt++; | |
- continue; | |
- } | |
- break; | |
- } | |
- if (i >= NVRW_RETRY) | |
- goto err_exit; | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_mcap_lock, 0); | |
- if (ret) | |
- pr_err("%s: nvm_mcap_lock failed\n", __func__); | |
- if (pnvrw_ctl->nvm_term_seq) { | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_term_seq, 0); | |
- if (ret) | |
- pr_err("%s: nvm_term_seq failed\n", __func__); | |
- } | |
- dsi_data->dsi_power_save(0); | |
- msleep(NVRW_PANEL_OFF_MSLEEP); | |
- | |
- return 0; | |
-err_exit: | |
- return ret; | |
-} | |
-static int nvm_rsp_write(struct msm_fb_data_type *mfd) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- struct dsi_nvm_rewrite_ctl *pnvrw_ctl; | |
- int i; | |
- int ret; | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- pnvrw_ctl = dsi_data->panel->pnvrw_ctl; | |
- dsi_data->dsi_power_save(1); | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_mcap, 0); | |
- if (ret) { | |
- pr_err("%s: nvm_mcap failed\n", __func__); | |
- goto err_exit; | |
- } | |
- for (i = 0; i < NVRW_RETRY; i++) { | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_open, 0); | |
- if (ret) | |
- pr_err("%s: nvm_open failed\n", __func__); | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_write_rsp, 0); | |
- if (ret) | |
- pr_err("%s: nvm_write_rsp failed\n", __func__); | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_flash_rsp, 0); | |
- if (ret) | |
- pr_err("%s: nvm_flash_rsp failed\n", __func__); | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_status, 1); | |
- if (ret) | |
- pr_err("%s: nvm_status failed\n", __func__); | |
- if (dsi_data->rx_buf.data[0] == NVRW_STATUS_RES_NG) { | |
- pr_err("%s (%d): RETRY %d", __func__, __LINE__, i+1); | |
- dsi_data->nvrw_retry_cnt++; | |
- continue; | |
- } | |
- break; | |
- } | |
- if (i >= NVRW_RETRY) { | |
- ret = -EAGAIN; | |
- goto err_exit; | |
- } | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_mcap_lock, 0); | |
- if (ret) | |
- pr_err("%s: nvm_mcap_lock failed\n", __func__); | |
- dsi_data->dsi_power_save(0); | |
- msleep(NVRW_PANEL_OFF_MSLEEP); | |
- | |
- return 0; | |
-err_exit: | |
- return ret; | |
-} | |
- | |
-static int nvm_user_write(struct msm_fb_data_type *mfd) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- struct dsi_nvm_rewrite_ctl *pnvrw_ctl; | |
- int ret; | |
- | |
- dsi_data = platform_get_drvdata(mfd->panel_pdev); | |
- pnvrw_ctl = dsi_data->panel->pnvrw_ctl; | |
- dsi_data->dsi_power_save(1); | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_mcap, 0); | |
- if (ret) { | |
- pr_err("%s: nvm_mcap failed\n", __func__); | |
- goto err_exit; | |
- } | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_write_user, 0); | |
- if (ret) { | |
- pr_err("%s: nvm_write_user_cmds failed\n", __func__); | |
- goto err_exit; | |
- } | |
- ret = panel_execute_cmd(mfd, dsi_data, | |
- pnvrw_ctl->nvm_flash_user, 0); | |
- if (ret) { | |
- pr_err("%s: nvm_flash_user_cmds failed\n", __func__); | |
- goto err_exit; | |
- } | |
- | |
- ret = panel_execute_cmd(mfd, dsi_data, pnvrw_ctl->nvm_mcap_lock, 0); | |
- if (ret) | |
- pr_err("%s: nvm_mcap_lock failed\n", __func__); | |
- dsi_data->dsi_power_save(0); | |
- msleep(NVRW_PANEL_OFF_MSLEEP); | |
- dsi_data->dsi_power_save(1); | |
- | |
- return 0; | |
-err_exit: | |
- return ret; | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_id_show(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- struct mipi_dsi_data *dsi_data = dev_get_drvdata(dev); | |
- char const *id = dsi_data->panel->panel_id ? | |
- dsi_data->panel->panel_id : "generic"; | |
- return scnprintf(buf, PAGE_SIZE, "%s\n", id); | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_rev_show(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- struct mipi_dsi_data *dsi_data = dev_get_drvdata(dev); | |
- char const *rev = dsi_data->panel->panel_rev ? | |
- dsi_data->panel->panel_rev : "generic"; | |
- return scnprintf(buf, PAGE_SIZE, "%s\n", rev); | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_frame_counter(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- return scnprintf(buf, PAGE_SIZE, "%i\n", fpsd.frame_counter); | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_frames_per_ksecs(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- return scnprintf(buf, PAGE_SIZE, "%i\n", fpsd.fpks); | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_interval_ms_show(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- return scnprintf(buf, PAGE_SIZE, "%i\n", fpsd.interval_ms); | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_log_interval_show(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- return scnprintf(buf, PAGE_SIZE, "%i\n", fpsd.log_interval); | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_log_interval_store(struct device *dev, | |
- struct device_attribute *attr, const char *buf, size_t count) | |
-{ | |
- int ret = count; | |
- | |
- if (sscanf(buf, "%4i", &fpsd.log_interval) != 1) { | |
- pr_err("%s: Error, buf = %s\n", __func__, buf); | |
- ret = -EINVAL; | |
- } | |
- return ret; | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_interval_array_ms(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- u16 i, len, rc = 0; | |
- char *tmp = buf; | |
- | |
- mutex_lock(&fpsd.fps_lock); | |
- len = fpsd.fa_last_array_pos; | |
- /* Get the first frames from the buffer */ | |
- for (i = len + 1; i < DEFAULT_FPS_ARRAY_SIZE; i++) { | |
- if (fpsd.fa[i].time_delta) { | |
- rc += scnprintf(tmp + rc, PAGE_SIZE - rc , | |
- "%i, ", fpsd.fa[i].time_delta); | |
- } | |
- } | |
- /* Get the rest frames from the buffer */ | |
- if (len) { | |
- for (i = 0; i <= len; i++) { | |
- if (fpsd.fa[i].time_delta) { | |
- rc += scnprintf(tmp + rc, PAGE_SIZE - rc , | |
- "%i, ", fpsd.fa[i].time_delta); | |
- } | |
- } | |
- } | |
- rc += scnprintf(tmp + rc, PAGE_SIZE - rc , "\n"); | |
- | |
- /* Clear the buffer once it is read */ | |
- mipi_dsi_panel_fps_array_clear(&fpsd); | |
- mutex_unlock(&fpsd.fps_lock); | |
- | |
- return rc; | |
-} | |
- | |
-#ifdef CONFIG_FB_MSM_RECOVER_PANEL | |
-static ssize_t mipi_dsi_panel_nvm_is_read_show(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- struct mipi_dsi_data *dsi_data = dev_get_drvdata(dev); | |
- | |
- if (!dsi_data->panel) | |
- return snprintf(buf, PAGE_SIZE, "NG"); | |
- if (dsi_data->panel->pnvrw_ctl == NULL) | |
- return snprintf(buf, PAGE_SIZE, "skip"); | |
- | |
- if (dsi_data->nvrw_panel_detective) | |
- return snprintf(buf, PAGE_SIZE, "OK"); | |
- else | |
- return snprintf(buf, PAGE_SIZE, "NG"); | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_nvm_result_show(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- struct mipi_dsi_data *dsi_data = dev_get_drvdata(dev); | |
- | |
- return snprintf(buf, PAGE_SIZE, "%d", dsi_data->nvrw_result); | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_nvm_show(struct device *dev, | |
- struct device_attribute *attr, char *buf) | |
-{ | |
- struct mipi_dsi_data *dsi_data = dev_get_drvdata(dev); | |
- struct msm_fb_data_type *mfd = dsi_data->nvrw_private; | |
- enum power_state old_state = PANEL_OFF; | |
- int rc = 0; | |
- | |
- if (!dsi_data->nvrw_panel_detective) | |
- goto exit; | |
- if (dsi_data->panel->pnvrw_ctl == NULL) | |
- goto exit; | |
- | |
- if (prepare_for_reg_access(mfd, &old_state)) | |
- goto exit; | |
- mipi_set_tx_power_mode(1); | |
- if (dsi_data->seq_nvm_read) | |
- rc = dsi_data->seq_nvm_read(mfd, buf); | |
- post_reg_access(mfd, old_state); | |
-exit: | |
- return rc; | |
-} | |
- | |
-static ssize_t mipi_dsi_panel_nvm_store(struct device *dev, | |
- struct device_attribute *attr, const char *buf, size_t count) | |
-{ | |
- struct mipi_dsi_data *dsi_data = dev_get_drvdata(dev); | |
- struct msm_fb_data_type *mfd = dsi_data->nvrw_private; | |
- int rc; | |
- enum power_state old_state = PANEL_OFF; | |
- | |
- dev_dbg(dev, "%s\n", __func__); | |
- dsi_data->nvrw_result = -1; | |
- dsi_data->nvrw_retry_cnt = 0; | |
- if (dsi_data->nvrw_panel_detective) | |
- goto exit; | |
- | |
- /* update panel information from miscTA */ | |
- rc = nvm_update_panel(mfd, buf, count); | |
- if (rc) | |
- goto exit; | |
- if (!dsi_data->panel->pnvrw_ctl || !dsi_data->dsi_power_save) | |
- goto exit; | |
- | |
- mfd->nvrw_prohibit_draw = true; | |
- rc = prepare_for_reg_access(mfd, &old_state); | |
- if (rc) | |
- goto exit; | |
- mipi_set_tx_power_mode(1); | |
- | |
- if (dsi_data->seq_nvm_read) { | |
- char nvm[NVRW_DATA_SIZE + 1]; | |
- /* Does not NVM disappear? */ | |
- dev_dbg(dev, "%s:seq_nvm_read\n", __func__); | |
- dsi_data->seq_nvm_read(mfd, nvm); | |
- if (0 == strncasecmp(buf, nvm, NVRW_DATA_SIZE - 1)) { | |
- dev_dbg(dev, "%s:skip_recover\n", __func__); | |
- dsi_data->nvrw_result = 0; | |
- goto skip_recover; | |
- } | |
- } | |
- if (dsi_data->override_nvm_data) { | |
- dev_dbg(dev, "%s:override_nvm_data\n", __func__); | |
- rc = dsi_data->override_nvm_data(mfd, buf, count); | |
- if (rc) { | |
- dev_err(dev, "%s : nvm data format error.<%s>\n", | |
- __func__, buf); | |
- goto release_exit; | |
- } | |
- } | |
- | |
- if (dsi_data->seq_nvm_erase) { | |
- dev_dbg(dev, "%s:seq_nvm_erase\n", __func__); | |
- rc = dsi_data->seq_nvm_erase(mfd); | |
- if (rc) { | |
- dev_err(dev, | |
- "%s : nvm data erase fail.\n", __func__); | |
- goto release_exit; | |
- } | |
- } | |
- if (dsi_data->seq_nvm_rsp_write) { | |
- dev_dbg(dev, "%s:seq_nvm_rsp_write\n", __func__); | |
- rc = dsi_data->seq_nvm_rsp_write(mfd); | |
- if (rc) { | |
- dev_err(dev, | |
- "%s : rsp write fail.\n", __func__); | |
- goto release_exit; | |
- } | |
- } | |
- | |
- if (dsi_data->seq_nvm_user_write) { | |
- dev_dbg(dev, "%s:seq_nvm_user_write\n", __func__); | |
- rc = dsi_data->seq_nvm_user_write(mfd); | |
- if (rc) { | |
- dev_err(dev, | |
- "%s : user write fail.\n", __func__); | |
- goto release_exit; | |
- } | |
- } | |
- dsi_data->nvrw_result = dsi_data->nvrw_retry_cnt + 1; | |
- | |
-skip_recover: | |
- dsi_data->nvrw_panel_detective = true; | |
-release_exit: | |
- post_reg_access(mfd, old_state); | |
- mfd->nvrw_prohibit_draw = false; | |
- | |
- if (dsi_data->nvrw_panel_detective) { | |
- struct fb_info *fbi = mfd->fbi; | |
- if (fbi && fbi->fbops && fbi->fbops->fb_blank) { | |
- fbi->fbops->fb_blank(FB_BLANK_POWERDOWN, fbi); | |
- fbi->fbops->fb_blank(FB_BLANK_UNBLANK, fbi); | |
- } | |
- } | |
-exit: | |
- return count; | |
-} | |
-#endif | |
- | |
-static struct device_attribute panel_attributes[] = { | |
- __ATTR(panel_id, S_IRUGO, mipi_dsi_panel_id_show, NULL), | |
- __ATTR(panel_rev, S_IRUGO, mipi_dsi_panel_rev_show, NULL), | |
- __ATTR(frame_counter, S_IRUGO, mipi_dsi_panel_frame_counter, NULL), | |
- __ATTR(frames_per_ksecs, S_IRUGO, | |
- mipi_dsi_panel_frames_per_ksecs, NULL), | |
- __ATTR(interval_ms, S_IRUGO, mipi_dsi_panel_interval_ms_show, NULL), | |
- __ATTR(log_interval, S_IRUGO|S_IWUSR|S_IWGRP, | |
- mipi_dsi_panel_log_interval_show, | |
- mipi_dsi_panel_log_interval_store), | |
- __ATTR(interval_array, S_IRUGO, | |
- mipi_dsi_panel_interval_array_ms, NULL), | |
-#ifdef CONFIG_FB_MSM_RECOVER_PANEL | |
- __ATTR(nvm_is_read, S_IRUGO, mipi_dsi_panel_nvm_is_read_show, NULL), | |
- __ATTR(nvm_result, S_IRUGO, mipi_dsi_panel_nvm_result_show, NULL), | |
- __ATTR(nvm, S_IRUSR | S_IWUSR, | |
- mipi_dsi_panel_nvm_show, mipi_dsi_panel_nvm_store), | |
-#endif | |
-}; | |
- | |
-static int register_attributes(struct device *dev) | |
-{ | |
- int i; | |
- for (i = 0; i < ARRAY_SIZE(panel_attributes); i++) | |
- if (device_create_file(dev, panel_attributes + i)) | |
- goto error; | |
- return 0; | |
-error: | |
- dev_err(dev, "%s: Unable to create interface\n", __func__); | |
- for (--i; i >= 0 ; i--) | |
- device_remove_file(dev, panel_attributes + i); | |
- return -ENODEV; | |
-} | |
- | |
-static void remove_attributes(struct device *dev) | |
-{ | |
- int i; | |
- for (i = 0; i < ARRAY_SIZE(panel_attributes); i++) | |
- device_remove_file(dev, panel_attributes + i); | |
-} | |
- | |
-static int __devexit mipi_dsi_panel_remove(struct platform_device *pdev) | |
-{ | |
- struct mipi_dsi_data *dsi_data; | |
- | |
- dsi_data = platform_get_drvdata(pdev); | |
- remove_attributes(&pdev->dev); | |
- | |
-#ifdef CONFIG_DEBUG_FS | |
- mipi_dsi_panel_remove_debugfs(pdev); | |
-#endif | |
- | |
- platform_set_drvdata(pdev, NULL); | |
- mipi_dsi_buf_release(&dsi_data->tx_buf); | |
- mipi_dsi_buf_release(&dsi_data->rx_buf); | |
- kfree(dsi_data); | |
- pcc_cfg_ptr = NULL; | |
- kfree(color_calib); | |
- return 0; | |
-} | |
- | |
-static int __devinit mipi_dsi_panel_probe(struct platform_device *pdev) | |
-{ | |
- int ret; | |
- struct panel_platform_data *platform_data; | |
- struct mipi_dsi_data *dsi_data; | |
- struct platform_device *mipi_dsi_pdev; | |
- | |
- pr_info("%s: pdev = %p, pdev->name = %s\n", __func__, pdev, pdev->name); | |
- | |
- platform_data = pdev->dev.platform_data; | |
- if (platform_data == NULL) | |
- return -EINVAL; | |
- | |
- dsi_data = kzalloc(sizeof(struct mipi_dsi_data), GFP_KERNEL); | |
- if (dsi_data == NULL) | |
- return -ENOMEM; | |
- | |
- mutex_init(&dsi_data->lock); | |
- dsi_data->panels = platform_data->panels; | |
- dsi_data->lcd_power = platform_data->platform_power; | |
- dsi_data->lcd_reset = platform_data->platform_reset; | |
- dsi_data->panel_data.panel_detect = detect_panel; | |
- dsi_data->panel_data.update_panel = panel_update_config; | |
- dsi_data->panel_detected = false; | |
- | |
- ret = mipi_dsi_buf_alloc(&dsi_data->tx_buf, DSI_BUF_SIZE); | |
- if (ret <= 0) { | |
- dev_err(&pdev->dev, "mipi_dsi_buf_alloc(tx) failed!\n"); | |
- ret = -ENOMEM; | |
- goto out_free; | |
- } | |
- | |
- ret = mipi_dsi_buf_alloc(&dsi_data->rx_buf, DSI_BUF_SIZE); | |
- if (ret <= 0) { | |
- dev_err(&pdev->dev, "mipi_dsi_buf_alloc(rx) failed!\n"); | |
- ret = -ENOMEM; | |
- goto out_rx_release; | |
- } | |
- | |
- platform_set_drvdata(pdev, dsi_data); | |
- dsi_data->panel_data.get_pcc_data = get_pcc_data; | |
- dsi_data->pcc_config = NULL; | |
- dsi_data->panel_data.panel_info = default_pinfo; | |
- dsi_data->panel_data.on = panel_on; | |
- dsi_data->panel_data.off = panel_off; | |
- dsi_data->override_nvm_data = nvm_override_data; | |
- dsi_data->seq_nvm_read = nvm_read; | |
- dsi_data->seq_nvm_erase = nvm_erase; | |
- dsi_data->seq_nvm_rsp_write = nvm_rsp_write; | |
- dsi_data->seq_nvm_user_write = nvm_user_write; | |
- dsi_data->nvrw_panel_detective = false; | |
- | |
- mipi_dsi_panel_fps_data_init(&fpsd); | |
- | |
- ret = platform_device_add_data(pdev, &dsi_data->panel_data, | |
- sizeof(dsi_data->panel_data)); | |
- if (ret) { | |
- dev_err(&pdev->dev, "platform_device_add_data failed!\n"); | |
- goto out_tx_release; | |
- } | |
- ret = register_attributes(&pdev->dev); | |
- if (ret) | |
- goto out_tx_release; | |
- mipi_dsi_pdev = msm_fb_add_device(pdev); | |
-#ifdef CONFIG_DEBUG_FS | |
- mipi_dsi_panel_create_debugfs(mipi_dsi_pdev); | |
-#endif | |
- dsi_data->nvrw_private = platform_get_drvdata(mipi_dsi_pdev); | |
- | |
- dev_info(&pdev->dev, "%s: Probe success\n", __func__); | |
- return 0; | |
-out_tx_release: | |
- mipi_dsi_buf_release(&dsi_data->rx_buf); | |
-out_rx_release: | |
- mipi_dsi_buf_release(&dsi_data->tx_buf); | |
-out_free: | |
- platform_set_drvdata(pdev, NULL); | |
- kfree(dsi_data); | |
- dev_info(&pdev->dev, "%s: Probe fail\n", __func__); | |
- return ret; | |
-} | |
- | |
-static struct platform_driver this_driver = { | |
- .probe = mipi_dsi_panel_probe, | |
- .remove = mipi_dsi_panel_remove, | |
- .driver = { | |
- .name = MIPI_DSI_PANEL_NAME, | |
- }, | |
-}; | |
- | |
-static int __init mipi_dsi_panel_init(void) | |
-{ | |
- return platform_driver_register(&this_driver); | |
-} | |
- | |
-static void __exit mipi_dsi_panel_exit(void) | |
-{ | |
- platform_driver_unregister(&this_driver); | |
-} | |
- | |
-module_init(mipi_dsi_panel_init); | |
-module_exit(mipi_dsi_panel_exit); | |
diff --git a/drivers/video/msm/mipi_dsi_panel_driver.h b/drivers/video/msm/mipi_dsi_panel_driver.h | |
deleted file mode 100644 | |
index c7947dc..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_driver.h | |
+++ /dev/null | |
@@ -1,143 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_driver.h | |
- * | |
- * Copyright (C) 2012-2013 Sony Mobile Communications AB. | |
- * | |
- * Author: Yosuke Hatanaka <[email protected]> | |
- * Author: Johan Olson <[email protected]> | |
- * Author: Joakim Wesslen <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2, as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
- | |
-#ifndef MIPI_DSI_PANEL_DRIVER_H | |
-#define MIPI_DSI_PANEL_DRIVER_H | |
- | |
-#include <linux/types.h> | |
-#include "mipi_dsi.h" | |
-#include <video/mipi_dsi_panel.h> | |
- | |
-#define ONE_FRAME_TRANSMIT_WAIT_MS 20 | |
-#define CLR_REG_DATA_NUM 2 | |
-#define CLR_RESOLUTION 60 | |
-#define CLR_NUM_PART 6 | |
-#define NVRW_NUM_E6_PARAM 8 | |
-#define NVRW_NUM_E7_PARAM 4 | |
-#define NVRW_NUM_DE_PARAM 12 | |
-#define PANEL_SKIP_ID 0xff | |
- | |
-enum power_state { | |
- PANEL_OFF, | |
- DEBUGFS_POWER_OFF, | |
- DEBUGFS_POWER_ON, | |
- PANEL_INITIALIZED, | |
- PANEL_SLEEP_OUT, | |
- PANEL_ON | |
-}; | |
- | |
-enum color_type { | |
- CLR01_GRN, | |
- CLR02_GRN, | |
- CLR03_LG, /* light green */ | |
- CLR04_LG, | |
- CLR05_YEL, | |
- CLR06_YEL, | |
- CLR07_GRN, | |
- CLR08_GRN, | |
- CLR09_LG, | |
- CLR10_LG, | |
- CLR11_YEL, | |
- CLR12_YEL, | |
- CLR13_LB, /* light blue */ | |
- CLR14_LB, | |
- CLR15_WHT, | |
- CLR16_ORG, | |
- CLR17_ORG, | |
- CLR18_BLE, | |
- CLR19_BLE, | |
- CLR20_PUR, | |
- CLR21_PUR, | |
- CLR22_RED, | |
- CLR23_RED, | |
- CLR24_RED, | |
- CLR25_RED, | |
-}; | |
- | |
-static const enum color_type panel_color_type[CLR_NUM_PART][CLR_NUM_PART] = { | |
- {CLR18_BLE, CLR19_BLE, CLR21_PUR, CLR21_PUR, CLR24_RED, CLR25_RED}, | |
- {CLR19_BLE, CLR19_BLE, CLR20_PUR, CLR20_PUR, CLR22_RED, CLR23_RED}, | |
- {CLR13_LB, CLR14_LB, CLR15_WHT, CLR15_WHT, CLR16_ORG, CLR17_ORG}, | |
- {CLR13_LB, CLR14_LB, CLR15_WHT, CLR15_WHT, CLR16_ORG, CLR17_ORG}, | |
- {CLR07_GRN, CLR08_GRN, CLR09_LG, CLR10_LG, CLR11_YEL, CLR12_YEL}, | |
- {CLR01_GRN, CLR02_GRN, CLR03_LG, CLR04_LG, CLR05_YEL, CLR06_YEL}, | |
-}; | |
- | |
-#define CLR_SUB_AREA_V_START 4 | |
-#define CLR_SUB_V_BLOCK_HEIGHT 4 | |
-#define CLR_SUB_COL_MAX 6 | |
-static const struct { | |
- uint8 u_min; | |
- uint8 u_max; | |
- uint8 sub_area; | |
-} clr_sub_tbl[][CLR_SUB_COL_MAX] = { | |
- {{22, 25, 50}, }, /* Area50 */ | |
- {{22, 25, 48}, {26, 29, 49}, }, /* Area48/49 */ | |
- {{22, 25, 45}, {26, 29, 46}, {30, 33, 47}, }, | |
- {{22, 25, 41}, {26, 29, 42}, {30, 33, 43}, {34, 37, 44}, }, | |
- {{22, 25, 37}, {26, 29, 38}, {30, 33, 39}, {34, 37, 40}, }, | |
- {{22, 23, 31}, {24, 27, 32}, {28, 31, 33}, {32, 35, 34}, {36, 39, 35}, | |
- {40, 41, 36}, }, | |
- {{22, 23, 26}, {24, 27, 27}, {32, 35, 28}, {36, 39, 29}, {40, 41, 30},}, | |
- {{22, 23, 20}, {24, 27, 21}, {28, 31, 22}, {32, 35, 23}, {36, 39, 24}, | |
- {40, 41, 25}, }, | |
- {{24, 27, 15}, {28, 31, 16}, {32, 35, 17}, {36, 39, 18}, {40, 41, 19},}, | |
- {{26, 29, 11}, {30, 33, 12}, {34, 37, 13}, {38, 41, 14}, }, | |
- {{29, 32, 7}, {33, 36, 8}, {37, 40, 9}, {41, 44, 10}, }, | |
- {{32, 35, 4}, {36, 39, 5}, {40, 43, 6}, }, | |
- {{35, 38, 2}, {39, 42, 3}, }, | |
- {{39, 42, 1}, }, /* Area1 */ | |
-}; | |
- | |
-struct mipi_dsi_data { | |
- struct dsi_buf tx_buf; | |
- struct dsi_buf rx_buf; | |
- struct msm_fb_panel_data panel_data; | |
- const struct panel *panel; | |
- const struct panel **panels; | |
- int (*lcd_power)(bool on); | |
- int (*lcd_reset)(bool on); | |
-#ifdef CONFIG_DEBUG_FS | |
- struct dentry *dir; | |
-#endif | |
- bool panel_detected; | |
- enum power_state panel_state; | |
- struct mutex lock; | |
- struct mdp_pcc_cfg_data *pcc_config; | |
- | |
- bool nvrw_panel_detective; | |
- int nvrw_result; | |
- int nvrw_retry_cnt; | |
- void *nvrw_private; | |
- | |
- int (*override_nvm_data)(struct msm_fb_data_type *mfd, | |
- const char *buf, int count); | |
- int (*seq_nvm_read)(struct msm_fb_data_type *mfd, char *buf); | |
- int (*seq_nvm_erase)(struct msm_fb_data_type *mfd); | |
- int (*seq_nvm_rsp_write)(struct msm_fb_data_type *mfd); | |
- int (*seq_nvm_user_write)(struct msm_fb_data_type *mfd); | |
- int (*dsi_power_save) (int on); | |
-}; | |
-extern struct mdp_pcc_cfg_data *pcc_cfg_ptr; | |
- | |
-void mipi_dsi_panel_fps_data_update(struct msm_fb_data_type *mfd); | |
-#ifdef CONFIG_DEBUG_FS | |
-extern void mipi_dsi_panel_create_debugfs(struct platform_device *pdev); | |
-extern void mipi_dsi_panel_remove_debugfs(struct platform_device *pdev); | |
-#endif | |
-int prepare_for_reg_access(struct msm_fb_data_type *mfd, | |
- enum power_state *old_state); | |
-void post_reg_access(struct msm_fb_data_type *mfd, enum power_state old_state); | |
-#endif /* MIPI_DSI_PANEL_DRIVER_H */ | |
diff --git a/drivers/video/msm/mipi_dsi_panel_nt71391_panasonic_vvx10f008b00.c b/drivers/video/msm/mipi_dsi_panel_nt71391_panasonic_vvx10f008b00.c | |
deleted file mode 100644 | |
index 5a707c9..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_nt71391_panasonic_vvx10f008b00.c | |
+++ /dev/null | |
@@ -1,150 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_nt71391_panasonic_vvx10f008b00.c | |
- * | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
- * | |
- * Author: Yutaka Seijyou <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2; as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
- | |
-#include "msm_fb.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-/* Initial Sequence */ | |
- | |
-/* Display ON Sequence */ | |
- | |
-/* Display OFF Sequence */ | |
- | |
-/* Reading DDB Sequence */ | |
-static char read_ddb_start[] = { | |
- 0xA1, 0x00 | |
-}; | |
- | |
- | |
-static struct dsi_cmd_desc read_ddb_cmd_seq[] = { | |
- {DTYPE_DCS_READ, 1, 0, 1, 5, sizeof(read_ddb_start), read_ddb_start}, | |
-}; | |
- | |
-static const struct panel_cmd display_init_cmds[] = { | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_on_cmds[] = { | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_off_cmds[] = { | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_ddb_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_ddb_cmd_seq, | |
- ARRAY_SIZE(read_ddb_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db[] = { | |
- /* 1920*1200, RGB888, 4 Lane 60 fps video mode */ | |
- { | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0xed, 0x3a, 0x28, 0x00, 0x6c, 0x77, 0x2c, 0x3e, | |
- 0x43, 0x03, 0x04, 0xa0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0xbc, 0x31, 0xd9, 0x00, 0x50, 0x48, 0x63, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
- }, | |
-}; | |
- | |
-static struct msm_panel_info pinfo; | |
- | |
-static struct msm_panel_info *get_panel_info(void) | |
-{ | |
- pinfo.xres = 1920; | |
- pinfo.yres = 1200; | |
- pinfo.type = MIPI_VIDEO_PANEL; | |
- pinfo.pdest = DISPLAY_1; | |
- pinfo.wait_cycle = 0; | |
- pinfo.bpp = 24; | |
- pinfo.lcdc.h_back_porch = 48; | |
- pinfo.lcdc.h_front_porch = 96; | |
- pinfo.lcdc.h_pulse_width = 16; | |
- pinfo.lcdc.v_back_porch = 10; | |
- pinfo.lcdc.v_front_porch = 23; | |
- pinfo.lcdc.v_pulse_width = 2; | |
- pinfo.lcdc.border_clr = 0; /* blk */ | |
- pinfo.lcdc.underflow_clr = 0x0; /* black */ | |
- pinfo.lcdc.hsync_skew = 0; | |
- pinfo.bl_max = 15; | |
- pinfo.bl_min = 1; | |
- pinfo.fb_num = 2; | |
- pinfo.clk_rate = 924000000; | |
- | |
- pinfo.mipi.mode = DSI_VIDEO_MODE; | |
- pinfo.mipi.pulse_mode_hsa_he = TRUE; | |
- pinfo.mipi.hfp_power_stop = FALSE; | |
- pinfo.mipi.hbp_power_stop = FALSE; | |
- pinfo.mipi.hsa_power_stop = FALSE; | |
- pinfo.mipi.eof_bllp_power_stop = TRUE; | |
- pinfo.mipi.bllp_power_stop = TRUE; | |
- pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; | |
- pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; | |
- pinfo.mipi.vc = 0; | |
- pinfo.mipi.dlane_swap = 0x00; | |
- pinfo.mipi.rgb_swap = DSI_RGB_SWAP_RGB; | |
- pinfo.mipi.r_sel = 0; | |
- pinfo.mipi.g_sel = 0; | |
- pinfo.mipi.b_sel = 0; | |
- pinfo.mipi.data_lane0 = TRUE; | |
- pinfo.mipi.data_lane1 = TRUE; | |
- pinfo.mipi.data_lane2 = TRUE; | |
- pinfo.mipi.data_lane3 = TRUE; | |
- pinfo.mipi.tx_eot_append = TRUE; | |
- pinfo.mipi.t_clk_post = 0x02; | |
- pinfo.mipi.t_clk_pre = 0x2e; | |
- pinfo.mipi.esc_byte_ratio = 9; | |
- pinfo.mipi.stream = 0; /* dma_p */ | |
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.frame_rate = 60; | |
- pinfo.mipi.dsi_phy_db = | |
- (struct mipi_dsi_phy_ctrl *)dsi_video_mode_phy_db; | |
- | |
- return &pinfo; | |
-} | |
- | |
-static struct dsi_controller dsi_video_controller_panel = { | |
- .get_panel_info = get_panel_info, | |
- .display_init = display_init_cmds, | |
- .display_on = display_on_cmds, | |
- .display_off = display_off_cmds, | |
- .read_id = read_ddb_cmds, | |
-}; | |
- | |
-static char ddb_val[] = { | |
- 0xff | |
-}; | |
- | |
-const struct panel panasonic_vvx10f008b00_panel_id = { | |
- .name = "mipi_video_panasonic_wuxga_vvx10f008b00", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val, | |
- .id_num = ARRAY_SIZE(ddb_val), | |
- .width = 217, | |
- .height = 136, | |
- .disable_dsi_timing_genarator_at_off = true, | |
- .panel_id = "vvx10f008b00", | |
- .panel_rev = "generic", | |
-}; | |
diff --git a/drivers/video/msm/mipi_dsi_panel_r63306_sharp_ls043k3sx04.c b/drivers/video/msm/mipi_dsi_panel_r63306_sharp_ls043k3sx04.c | |
deleted file mode 100644 | |
index e3167f1..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_r63306_sharp_ls043k3sx04.c | |
+++ /dev/null | |
@@ -1,246 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_r63306_sharp_ls043k3sx04.c | |
- * | |
- * Copyright (c) 2012 Sony Mobile Communications AB. | |
- * | |
- * Author: Johan Olson <[email protected]> | |
- * Author: Joakim Wesslen <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2; as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
- | |
-#include "msm_fb.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-/* Initial Sequence */ | |
-static char mcap[] = { | |
- 0xB0, 0x00 | |
-}; | |
-static char ltps_if_ctrl[] = { | |
- 0xC4, 0xC3, 0x29 | |
-}; | |
-static char gamma_ctrl[] = { | |
- 0xC8, 0x10, 0x00, 0x1F, 0x00 | |
-}; | |
-static char gamma_ctrl_set_r_pos[] = { | |
- 0xC9, 0x08, 0x03, 0x01, 0x01, 0x02, 0x05, 0x11, | |
- 0x18, 0x10, 0x0C, 0x1F, 0x10, 0x20 | |
-}; | |
-static char gamma_ctrl_set_r_neg[] = { | |
- 0xCA, 0x26, 0x2B, 0x50, 0x4F, 0x4E, 0x49, 0x3F, | |
- 0x36, 0x3E, 0x41, 0x34, 0x29, 0x19 | |
-}; | |
-static char gamma_ctrl_set_g_pos[] = { | |
- 0xCB, 0x29, 0x21, 0x1F, 0x1E, 0x1A, 0x13, 0x19, | |
- 0x1C, 0x15, 0x11, 0x24, 0x14, 0x20 | |
-}; | |
-static char gamma_ctrl_set_g_neg[] = { | |
- 0xCC, 0x09, 0x11, 0x32, 0x33, 0x36, 0x3D, 0x36, | |
- 0x33, 0x39, 0x3C, 0x2C, 0x21, 0x19 | |
-}; | |
-static char gamma_ctrl_set_b_pos[] = { | |
- 0xCD, 0x3C, 0x33, 0x32, 0x2A, 0x26, 0x14, 0x1B, | |
- 0x1F, 0x19, 0x16, 0x26, 0x10, 0x20 | |
-}; | |
-static char gamma_ctrl_set_b_neg[] = { | |
- 0xCE, 0x00, 0x00, 0x1F, 0x26, 0x2A, 0x3B, 0x34, | |
- 0x2E, 0x34, 0x38, 0x28, 0x22, 0x19 | |
-}; | |
-static char mcap_lock[] = { | |
- 0xB0, 0x03 | |
-}; | |
- | |
-/* Display ON Sequence */ | |
-static char exit_sleep[] = { | |
- 0x11 | |
-}; | |
-static char display_on[] = { | |
- 0x29 | |
-}; | |
- | |
-/* Display OFF Sequence */ | |
-static char display_off[] = { | |
- 0x28 | |
-}; | |
- | |
-static char enter_sleep[] = { | |
- 0x10 | |
-}; | |
- | |
-/* Reading DDB Sequence */ | |
-static char read_ddb_start[] = { | |
- 0xA1, 0x00 | |
-}; | |
- | |
-static struct dsi_cmd_desc display_init_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 120, sizeof(exit_sleep), exit_sleep}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, sizeof(mcap), mcap}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(ltps_if_ctrl), ltps_if_ctrl}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(gamma_ctrl), gamma_ctrl}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(gamma_ctrl_set_r_pos), | |
- gamma_ctrl_set_r_pos}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(gamma_ctrl_set_r_neg), | |
- gamma_ctrl_set_r_neg}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(gamma_ctrl_set_g_pos), | |
- gamma_ctrl_set_g_pos}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(gamma_ctrl_set_g_neg), | |
- gamma_ctrl_set_g_neg}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(gamma_ctrl_set_b_pos), | |
- gamma_ctrl_set_b_pos}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, sizeof(gamma_ctrl_set_b_neg), | |
- gamma_ctrl_set_b_neg}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, sizeof(mcap_lock), mcap_lock}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_on_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(display_on), display_on}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_off_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(display_off), display_off}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 120, sizeof(enter_sleep), enter_sleep} | |
-}; | |
- | |
-static struct dsi_cmd_desc read_ddb_cmd_seq[] = { | |
- {DTYPE_DCS_READ, 1, 0, 1, 5, sizeof(read_ddb_start), read_ddb_start}, | |
-}; | |
- | |
-static const struct panel_cmd display_init_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_init_cmd_seq, | |
- ARRAY_SIZE(display_init_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_on_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_on_cmd_seq, | |
- ARRAY_SIZE(display_on_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_off_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_off_cmd_seq, | |
- ARRAY_SIZE(display_off_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_ddb_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_ddb_cmd_seq, | |
- ARRAY_SIZE(read_ddb_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db[] = { | |
- /* 720*1280, RGB888, 4 Lane 60 fps video mode */ | |
- { | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0x78, 0x1a, 0x11, 0x00, 0x3e, 0x43, 0x16, 0x1d, | |
- 0x1d, 0x03, 0x04, 0xa0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0x8f, 0x31, 0xd9, 0x00, 0x50, 0x48, 0x63, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
- }, | |
-}; | |
- | |
-static struct msm_panel_info pinfo; | |
- | |
-static struct msm_panel_info *get_panel_info(void) | |
-{ | |
- pinfo.xres = 720; | |
- pinfo.yres = 1280; | |
- pinfo.type = MIPI_VIDEO_PANEL; | |
- pinfo.pdest = DISPLAY_1; | |
- pinfo.wait_cycle = 0; | |
- pinfo.bpp = 24; | |
- pinfo.lcdc.h_back_porch = 45; | |
- pinfo.lcdc.h_front_porch = 128; | |
- pinfo.lcdc.h_pulse_width = 3; | |
- pinfo.lcdc.v_back_porch = 4; | |
- pinfo.lcdc.v_front_porch = 5; | |
- pinfo.lcdc.v_pulse_width = 1; | |
- pinfo.lcdc.border_clr = 0; /* blk */ | |
- pinfo.lcdc.underflow_clr = 0; /* black */ | |
- pinfo.lcdc.hsync_skew = 0; | |
- pinfo.bl_max = 15; | |
- pinfo.bl_min = 1; | |
- pinfo.fb_num = 2; | |
- pinfo.clk_rate = 416000000; | |
- | |
- pinfo.mipi.mode = DSI_VIDEO_MODE; | |
- pinfo.mipi.pulse_mode_hsa_he = TRUE; | |
- pinfo.mipi.hfp_power_stop = FALSE; | |
- pinfo.mipi.hbp_power_stop = FALSE; | |
- pinfo.mipi.hsa_power_stop = FALSE; | |
- pinfo.mipi.eof_bllp_power_stop = TRUE; | |
- pinfo.mipi.bllp_power_stop = TRUE; | |
- pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; | |
- pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; | |
- pinfo.mipi.vc = 0; | |
- pinfo.mipi.rgb_swap = DSI_RGB_SWAP_BGR; | |
- pinfo.mipi.r_sel = 0; | |
- pinfo.mipi.g_sel = 0; | |
- pinfo.mipi.b_sel = 0; | |
- pinfo.mipi.data_lane0 = TRUE; | |
- pinfo.mipi.data_lane1 = TRUE; | |
- pinfo.mipi.data_lane2 = TRUE; | |
- pinfo.mipi.data_lane3 = TRUE; | |
- pinfo.mipi.tx_eot_append = TRUE; | |
- pinfo.mipi.t_clk_post = 0x04; | |
- pinfo.mipi.t_clk_pre = 0x1B; | |
- pinfo.mipi.stream = 0; /* dma_p */ | |
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.frame_rate = 60; | |
- pinfo.mipi.dsi_phy_db = | |
- (struct mipi_dsi_phy_ctrl *)dsi_video_mode_phy_db; | |
- | |
- return &pinfo; | |
-} | |
- | |
-static struct dsi_controller dsi_video_controller_panel = { | |
- .get_panel_info = get_panel_info, | |
- .display_init = display_init_cmds, | |
- .display_on = display_on_cmds, | |
- .display_off = display_off_cmds, | |
- .read_id = read_ddb_cmds, | |
-}; | |
- | |
-static char ddb_val_1a[] = { | |
- 0x12, 0x61, 0x41, 0x46, 0x1a, 0x01, 0x00, 0xff | |
-}; | |
- | |
-static char ddb_val[] = { | |
- 0x12, 0x61, 0x41, 0x46, 0xff, 0x01, 0x00, 0xff | |
-}; | |
- | |
-const struct panel sharp_ls043k3sx04_panel_id_1a = { | |
- .name = "mipi_video_sharp_wxga_ls043k3sx04_id_1a", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_1a, | |
- .id_num = ARRAY_SIZE(ddb_val_1a), | |
- .width = 53, | |
- .height = 95, | |
- .panel_id = "ls043k3sx04", | |
- .panel_rev = "1a", | |
-}; | |
- | |
-const struct panel sharp_ls043k3sx04_panel_id = { | |
- .name = "mipi_video_sharp_wxga_ls043k3sx04", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val, | |
- .id_num = ARRAY_SIZE(ddb_val), | |
- .width = 53, | |
- .height = 95, | |
- .panel_id = "ls043k3sx04", | |
- .panel_rev = "generic", | |
-}; | |
diff --git a/drivers/video/msm/mipi_dsi_panel_r63306_tmd_mdw30.c b/drivers/video/msm/mipi_dsi_panel_r63306_tmd_mdw30.c | |
deleted file mode 100644 | |
index a684825..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_r63306_tmd_mdw30.c | |
+++ /dev/null | |
@@ -1,415 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_r63306_tmd_mdw30.c | |
- * | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
- * | |
- * Author: Yosuke Hatanaka <[email protected]> | |
- * Author: Yutaka Seijyou <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2; as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
- | |
-#include "msm_fb.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-/* Initial Sequence */ | |
-static char set_address_mode[] = { | |
- 0x36, 0x50 | |
-}; | |
-static char mcap[] = { | |
- 0xB0, 0x00 | |
-}; | |
-static char acr[] = { | |
- 0xB2, 0x00 | |
-}; | |
-static char clk_and_if[] = { | |
- 0xB3, 0x0C | |
-}; | |
-static char pixform[] = { | |
- 0xB4, 0x02 | |
-}; | |
-static char pfm_pwm_ctrl[] = { | |
- 0xB9, 0x01, 0x00, 0x75, 0x00, 0xBA, 0xBB, 0xBF, | |
- 0xCC, 0xE3, 0x46, 0x81, 0xC2 | |
-}; | |
-static char cabc_on_off[] = { | |
- 0xBB, 0x00 | |
-}; | |
-static char cabc_user_param[] = { | |
- 0xBE, 0xFF, 0x0F, 0x1A, 0x18, 0x02, 0x40, 0x00, | |
- 0x5D, 0x00, 0x00, 0x80, 0x32 | |
-}; | |
-static char panel_driving[] = { | |
- 0xC0, 0x40, 0x02, 0x7F, 0xC8, 0x08 | |
-}; | |
-static char h_timing[] = { | |
- 0xC1, 0x00, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x00, | |
- 0x9C, 0x08, 0x24, 0x0B, 0x00, 0x00, 0x00, 0x00 | |
-}; | |
-static char src_out[] = { | |
- 0xC2, 0x00, 0x00, 0x0B, 0x00, 0x00 | |
-}; | |
-static char gate_ic_ctrl[] = { | |
- 0xC3, 0x04 | |
-}; | |
-static char ltps_if_ctrl_1[] = { | |
- 0xC4, 0x4D, 0x83, 0x00 | |
-}; | |
-static char src_out_mode[] = { | |
- 0xC6, 0x12, 0x00, 0x08, 0x71, 0x00, 0x00, 0x00, | |
- 0x80, 0x00, 0x04 | |
-}; | |
-static char ltps_if_ctrl_2[] = { | |
- 0xC7, 0x22 | |
-}; | |
-static char gamma_ctrl[] = { | |
- 0xC8, 0x4C, 0x0C, 0x0C, 0x0C | |
-}; | |
-static char gamma_ctrl_set_r_pos[] = { | |
- 0xC9, 0x00, 0x63, 0x3B, 0x3A, 0x33, 0x25, 0x2A, | |
- 0x30, 0x2B, 0x2F, 0x47, 0x79, 0x3F | |
-}; | |
-static char gamma_ctrl_set_r_neg[] = { | |
- 0xCA, 0x00, 0x46, 0x1A, 0x31, 0x35, 0x2F, 0x36, | |
- 0x3A, 0x2D, 0x25, 0x28, 0x5C, 0x3F | |
-}; | |
-static char gamma_ctrl_set_g_pos[] = { | |
- 0xCB, 0x00, 0x63, 0x3B, 0x3A, 0x33, 0x25, 0x2A, | |
- 0x30, 0x2B, 0x2F, 0x47, 0x79, 0x3F | |
-}; | |
-static char gamma_ctrl_set_g_neg[] = { | |
- 0xCC, 0x00, 0x46, 0x1A, 0x31, 0x35, 0x2F, 0x36, | |
- 0x3A, 0x2D, 0x25, 0x28, 0x5C, 0x3F | |
-}; | |
-static char gamma_ctrl_set_b_pos[] = { | |
- 0xCD, 0x00, 0x63, 0x3B, 0x3A, 0x33, 0x25, 0x2A, | |
- 0x30, 0x2B, 0x2F, 0x47, 0x79, 0x3F | |
-}; | |
-static char gamma_ctrl_set_b_neg[] = { | |
- 0xCE, 0x00, 0x46, 0x1A, 0x31, 0x35, 0x2F, 0x36, | |
- 0x3A, 0x2D, 0x25, 0x28, 0x5C, 0x3F | |
-}; | |
-static char power_setting_1[] = { | |
- 0xD0, 0x6A, 0x64, 0x01 | |
-}; | |
-static char power_setting_2[] = { | |
- 0xD1, 0x77, 0xD4 | |
-}; | |
-static char power_setting_internal[] = { | |
- 0xD3, 0x33 | |
-}; | |
-static char vplvl_vnlvl_setting[] = { | |
- 0xD5, 0x0C, 0x0C | |
-}; | |
-static char vcom_dc_setting_1[] = { | |
- 0xD8, 0x34, 0x64, 0x23, 0x25, 0x62, 0x32 | |
-}; | |
-static char vcom_dc_setting_2[] = { | |
- 0xDE, 0x10, 0xA8, 0x11, 0x08, 0x00, 0x00, 0x00, | |
- 0x00, 0x00, 0x00, 0x00 | |
-}; | |
-static char nvm_load_ctrl[] = { | |
- 0xE2, 0x00 | |
-}; | |
- | |
-/* Display ON Sequence */ | |
-static char exit_sleep[] = { | |
- 0x11 | |
-}; | |
-static char display_on[] = { | |
- 0x29 | |
-}; | |
- | |
-/* Display OFF Sequence */ | |
-static char enter_sleep[] = { | |
- 0x10 | |
-}; | |
- | |
-/* Reading DDB Sequence */ | |
-static char read_ddb_start[] = { | |
- 0xA1, 0x00 | |
-}; | |
- | |
-static struct dsi_cmd_desc display_init_cmd_seq_id_old[] = { | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(mcap), mcap}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(acr), acr}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(clk_and_if), clk_and_if}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(pixform), pixform}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(pfm_pwm_ctrl), pfm_pwm_ctrl}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(cabc_on_off), cabc_on_off}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(cabc_user_param), cabc_user_param}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(panel_driving), panel_driving}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(h_timing), h_timing}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(src_out), src_out}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(gate_ic_ctrl), gate_ic_ctrl}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(ltps_if_ctrl_1), ltps_if_ctrl_1}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(src_out_mode), src_out_mode}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(ltps_if_ctrl_2), ltps_if_ctrl_2}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(gamma_ctrl), gamma_ctrl}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(gamma_ctrl_set_r_pos), gamma_ctrl_set_r_pos}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(gamma_ctrl_set_r_neg), gamma_ctrl_set_r_neg}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(gamma_ctrl_set_g_pos), gamma_ctrl_set_g_pos}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(gamma_ctrl_set_g_neg), gamma_ctrl_set_g_neg}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(gamma_ctrl_set_b_pos), gamma_ctrl_set_b_pos}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(gamma_ctrl_set_b_neg), gamma_ctrl_set_b_neg}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(power_setting_1), power_setting_1}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(power_setting_2), power_setting_2}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(power_setting_internal), power_setting_internal}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(vplvl_vnlvl_setting), vplvl_vnlvl_setting}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(vcom_dc_setting_1), vcom_dc_setting_1}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(vcom_dc_setting_2), vcom_dc_setting_2}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(nvm_load_ctrl), nvm_load_ctrl}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_init_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE1, 1, 0, 0, 0, | |
- sizeof(set_address_mode), set_address_mode}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(mcap), mcap}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_on_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 120, | |
- sizeof(exit_sleep), exit_sleep}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, | |
- sizeof(display_on), display_on}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_off_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 120, | |
- sizeof(enter_sleep), enter_sleep} | |
-}; | |
- | |
-static struct dsi_cmd_desc read_ddb_cmd_seq[] = { | |
- {DTYPE_DCS_READ, 1, 0, 1, 5, sizeof(read_ddb_start), read_ddb_start}, | |
-}; | |
- | |
-static const struct panel_cmd display_init_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_init_cmd_seq, | |
- ARRAY_SIZE(display_init_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_init_cmds_id_old[] = { | |
- {CMD_DSI, {.dsi_payload = {display_init_cmd_seq_id_old, | |
- ARRAY_SIZE(display_init_cmd_seq_id_old)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_on_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_on_cmd_seq, | |
- ARRAY_SIZE(display_on_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_off_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_off_cmd_seq, | |
- ARRAY_SIZE(display_off_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_ddb_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_ddb_cmd_seq, | |
- ARRAY_SIZE(read_ddb_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db[] = { | |
- /* 720*1280, RGB888, 4 Lane 60 fps video mode */ | |
- { | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0x7b, 0x1b, 0x12, 0x00, 0x40, 0x49, 0x17, 0x1e, | |
- 0x1e, 0x03, 0x04, 0xa0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0x9e, 0x31, 0xd9, 0x00, 0x50, 0x48, 0x63, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
- }, | |
-}; | |
- | |
-static struct msm_panel_info pinfo; | |
- | |
-static struct msm_panel_info *get_panel_info(void) | |
-{ | |
- pinfo.xres = 720; | |
- pinfo.yres = 1280; | |
- pinfo.type = MIPI_VIDEO_PANEL; | |
- pinfo.pdest = DISPLAY_1; | |
- pinfo.wait_cycle = 0; | |
- pinfo.bpp = 24; | |
- pinfo.lcdc.h_back_porch = 45; | |
- pinfo.lcdc.h_front_porch = 156; | |
- pinfo.lcdc.h_pulse_width = 3; | |
- pinfo.lcdc.v_back_porch = 3; | |
- pinfo.lcdc.v_front_porch = 9; | |
- pinfo.lcdc.v_pulse_width = 4; | |
- pinfo.lcdc.border_clr = 0; /* blk */ | |
- pinfo.lcdc.underflow_clr = 0xff; /* blue */ | |
- pinfo.lcdc.hsync_skew = 0; | |
- pinfo.bl_max = 15; | |
- pinfo.bl_min = 1; | |
- pinfo.fb_num = 2; | |
- pinfo.clk_rate = 431000000; | |
- | |
- pinfo.mipi.mode = DSI_VIDEO_MODE; | |
- pinfo.mipi.pulse_mode_hsa_he = TRUE; | |
- pinfo.mipi.hfp_power_stop = FALSE; | |
- pinfo.mipi.hbp_power_stop = FALSE; | |
- pinfo.mipi.hsa_power_stop = FALSE; | |
- pinfo.mipi.eof_bllp_power_stop = TRUE; | |
- pinfo.mipi.bllp_power_stop = TRUE; | |
- pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; | |
- pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; | |
- pinfo.mipi.vc = 0; | |
- pinfo.mipi.dlane_swap = 0x00; | |
- pinfo.mipi.rgb_swap = DSI_RGB_SWAP_RGB; | |
- pinfo.mipi.r_sel = 0; | |
- pinfo.mipi.g_sel = 0; | |
- pinfo.mipi.b_sel = 0; | |
- pinfo.mipi.data_lane0 = TRUE; | |
- pinfo.mipi.data_lane1 = TRUE; | |
- pinfo.mipi.data_lane2 = TRUE; | |
- pinfo.mipi.data_lane3 = TRUE; | |
- pinfo.mipi.tx_eot_append = TRUE; | |
- pinfo.mipi.t_clk_post = 0x04; | |
- pinfo.mipi.t_clk_pre = 0x1b; | |
- pinfo.mipi.stream = 0; /* dma_p */ | |
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.frame_rate = 60; | |
- pinfo.mipi.dsi_phy_db = | |
- (struct mipi_dsi_phy_ctrl *)dsi_video_mode_phy_db; | |
- | |
- return &pinfo; | |
-} | |
- | |
-static struct dsi_controller dsi_video_controller_panel_id_old = { | |
- .get_panel_info = get_panel_info, | |
- .display_init = display_init_cmds_id_old, | |
- .display_on = display_on_cmds, | |
- .display_off = display_off_cmds, | |
- .read_id = read_ddb_cmds, | |
-}; | |
- | |
-static struct dsi_controller dsi_video_controller_panel = { | |
- .get_panel_info = get_panel_info, | |
- .display_init = display_init_cmds, | |
- .display_on = display_on_cmds, | |
- .display_off = display_off_cmds, | |
- .read_id = read_ddb_cmds, | |
-}; | |
- | |
-static char ddb_val_id_old[] = { | |
- 0x01, 0xFF, 0xFF | |
-}; | |
- | |
-static char ddb_val_1a[] = { | |
- 0x12, 0x56, 0x81, 0x72, 0x1a, 0x01, 0x00, 0xff | |
-}; | |
- | |
-static char ddb_val_1c[] = { | |
- 0x12, 0x56, 0x81, 0x72, 0x1c, 0x01, 0x00, 0xff | |
-}; | |
- | |
-static char ddb_val_1e[] = { | |
- 0x12, 0x56, 0x81, 0x72, 0x1e, 0x01, 0x00, 0xff | |
-}; | |
- | |
-static char ddb_val[] = { | |
- 0x12, 0x56, 0x81, 0x72, 0xff, 0x01, 0x00, 0xff | |
-}; | |
- | |
-const struct panel tmd_mdw30_panel_id_old = { | |
- .name = "mipi_video_tmd_wxga_mdw30_id_old_struct", | |
- .pctrl = &dsi_video_controller_panel_id_old, | |
- .id = ddb_val_id_old, | |
- .id_num = ARRAY_SIZE(ddb_val_id_old), | |
- .width = 57, | |
- .height = 101, | |
- .panel_id = "mdw30", | |
- .panel_rev = "old", | |
-}; | |
- | |
-const struct panel tmd_mdw30_panel_id_1a = { | |
- .name = "mipi_video_tmd_wxga_mdw30_id_1a", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_1a, | |
- .id_num = ARRAY_SIZE(ddb_val_1a), | |
- .width = 57, | |
- .height = 101, | |
- .panel_id = "mdw30", | |
- .panel_rev = "1a", | |
-}; | |
- | |
-const struct panel tmd_mdw30_panel_id_1c = { | |
- .name = "mipi_video_tmd_wxga_mdw30_id_1c", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_1c, | |
- .id_num = ARRAY_SIZE(ddb_val_1c), | |
- .width = 57, | |
- .height = 101, | |
- .panel_id = "mdw30", | |
- .panel_rev = "1c", | |
-}; | |
- | |
-const struct panel tmd_mdw30_panel_id_1e = { | |
- .name = "mipi_video_tmd_wxga_mdw30_id_1e", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_1e, | |
- .id_num = ARRAY_SIZE(ddb_val_1e), | |
- .width = 57, | |
- .height = 101, | |
- .panel_id = "mdw30", | |
- .panel_rev = "1e", | |
-}; | |
- | |
-const struct panel tmd_mdw30_panel_id = { | |
- .name = "mipi_video_tmd_wxga_mdw30", | |
- .pctrl = &dsi_video_controller_panel, | |
- .width = 57, | |
- .height = 101, | |
- .id = ddb_val, | |
- .id_num = ARRAY_SIZE(ddb_val), | |
- .width = 57, | |
- .height = 101, | |
- .panel_id = "mdw30", | |
- .panel_rev = "generic", | |
-}; | |
diff --git a/drivers/video/msm/mipi_dsi_panel_r63311_jdc_mdy70.c b/drivers/video/msm/mipi_dsi_panel_r63311_jdc_mdy70.c | |
deleted file mode 100644 | |
index e5ab079..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_r63311_jdc_mdy70.c | |
+++ /dev/null | |
@@ -1,443 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_r63311_jdc_mdy70.c | |
- * | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
- * | |
- * Author: Yutaka Seijyou <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2; as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
- | |
-#include "msm_fb.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-/* Initial Sequence */ | |
-static char soft_reset[] = { | |
- 0x01 | |
-}; | |
-static char mcap[] = { | |
- 0xB0, 0x00 | |
-}; | |
-static char sequencer_test_ctrl[] = { | |
- 0xD6, 0x01 | |
-}; | |
-static char interface_setting[] = { | |
- 0xB3, 0x14, 0x00, 0x00, 0x20, 0x00, 0x00 | |
-}; | |
-static char interface_id_setting[] = { | |
- 0xB4, 0x0C, 0x00 | |
-}; | |
-static char dsi_control[] = { | |
- 0xB6, 0x3A, 0xD3 | |
-}; | |
- | |
-/* Display ON Sequence */ | |
-static char exit_sleep[] = { | |
- 0x11 | |
-}; | |
-static char display_on[] = { | |
- 0x29 | |
-}; | |
- | |
-/* Display OFF Sequence */ | |
-static char display_off[] = { | |
- 0x28 | |
-}; | |
-static char enter_sleep[] = { | |
- 0x10 | |
-}; | |
- | |
-/* Reading DDB Sequence */ | |
-static char read_ddb_start[] = { | |
- 0xA1, 0x00 | |
-}; | |
- | |
-/* Reading Color */ | |
-static char read_color[] = { | |
- 0xEF, 0x00 | |
-}; | |
- | |
-static struct dsi_cmd_desc display_init_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 5, | |
- sizeof(soft_reset), soft_reset}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(mcap), mcap}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(sequencer_test_ctrl), sequencer_test_ctrl}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(interface_setting), interface_setting}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(interface_id_setting), interface_id_setting}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(dsi_control), dsi_control}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_on_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 120, | |
- sizeof(exit_sleep), exit_sleep}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, | |
- sizeof(display_on), display_on}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_off_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 20, | |
- sizeof(display_off), display_off}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 80, | |
- sizeof(enter_sleep), enter_sleep}, | |
-}; | |
- | |
-static struct dsi_cmd_desc read_ddb_cmd_seq[] = { | |
- {DTYPE_DCS_READ, 1, 0, 1, 5, sizeof(read_ddb_start), read_ddb_start}, | |
-}; | |
- | |
-static struct dsi_cmd_desc read_color_init_cmd[] = { | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, sizeof(mcap), mcap}, | |
-}; | |
- | |
-static struct dsi_cmd_desc read_color_cmd[] = { | |
- {DTYPE_GEN_READ1, 1, 0, 1, 5, sizeof(read_color), read_color}, | |
-}; | |
- | |
-static const struct panel_cmd display_init_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_init_cmd_seq, | |
- ARRAY_SIZE(display_init_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_on_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_on_cmd_seq, | |
- ARRAY_SIZE(display_on_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_off_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_off_cmd_seq, | |
- ARRAY_SIZE(display_off_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_ddb_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_ddb_cmd_seq, | |
- ARRAY_SIZE(read_ddb_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_color_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_color_init_cmd, | |
- ARRAY_SIZE(read_color_init_cmd)} } }, | |
- {CMD_DSI, {.dsi_payload = {read_color_cmd, | |
- ARRAY_SIZE(read_color_cmd)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db[] = { | |
- /* 1080*1920, RGB888, 4 Lane 60 fps video mode */ | |
- { | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0xe6, 0x38, 0x27, 0x00, 0x69, 0x72, 0x2b, 0x3c, | |
- 0x41, 0x03, 0x04, 0xa0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0xaf, 0x31, 0xd9, 0x00, 0x50, 0x48, 0x63, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
- }, | |
-}; | |
- | |
-static const struct mdp_pcc_cfg_rgb color_correction_data[] = { | |
- {0x08000, 0x06D00, 0x08000}, /* CLR01_GRN */ | |
- {0x07A00, 0x07100, 0x08000}, /* CLR02_GRN */ | |
- {0x07400, 0x07180, 0x08000}, /* CLR03_LG */ | |
- {0x07100, 0x07200, 0x08000}, /* CLR04_LG */ | |
- {0x06C80, 0x07180, 0x08000}, /* CLR05_YEL */ | |
- {0x06680, 0x07300, 0x08000}, /* CLR06_YEL */ | |
- {0x08000, 0x06B80, 0x07080}, /* CLR07_GRN */ | |
- {0x08000, 0x07400, 0x08000}, /* CLR08_GRN */ | |
- {0x07A00, 0x07700, 0x08000}, /* CLR09_LG */ | |
- {0x07600, 0x07780, 0x08000}, /* CLR10_LG */ | |
- {0x06F80, 0x07980, 0x08000}, /* CLR11_YEL */ | |
- {0x07080, 0x07E80, 0x08000}, /* CLR12_YEL */ | |
- {0x08000, 0x06B80, 0x06D00}, /* CLR13_LB */ | |
- {0x08000, 0x07380, 0x07480}, /* CLR14_LB */ | |
- {0x08000, 0x08000, 0x08000}, /* CLR15_WHT */ | |
- {0x07500, 0x08000, 0x07E80}, /* CLR16_ORG */ | |
- {0x07100, 0x08000, 0x07C80}, /* CLR17_ORG */ | |
- {0x08000, 0x06900, 0x06500}, /* CLR18_BLE */ | |
- {0x08000, 0x07300, 0x06F00}, /* CLR19_BLE */ | |
- {0x07F00, 0x08000, 0x07900}, /* CLR20_PUR */ | |
- {0x07E80, 0x08000, 0x07680}, /* CLR21_PUR */ | |
- {0x07380, 0x08000, 0x07600}, /* CLR22_RED */ | |
- {0x07080, 0x08000, 0x07900}, /* CLR23_RED */ | |
- {0x07A00, 0x08000, 0x07580}, /* CLR24_RED */ | |
- {0x06F00, 0x08000, 0x07200}, /* CLR25_RED */ | |
-}; | |
- | |
-static const struct mdp_pcc_cfg_rgb color_sub_area[] = { | |
- {0x05f00, 0x06900, 0x08000}, /* Area1 */ | |
- {0x06600, 0x06c00, 0x08000}, | |
- {0x06200, 0x06d00, 0x08000}, | |
- {0x06b80, 0x06d80, 0x08000}, | |
- {0x06700, 0x06f80, 0x08000}, | |
- {0x06400, 0x07100, 0x08000}, | |
- {0x07200, 0x07180, 0x08000}, | |
- {0x06d80, 0x07280, 0x08000}, | |
- {0x06a00, 0x07280, 0x08000}, | |
- {0x06680, 0x07500, 0x08000}, | |
- | |
- {0x07800, 0x07500, 0x08000}, | |
- {0x07400, 0x07580, 0x08000}, | |
- {0x06f00, 0x07600, 0x08000}, | |
- {0x06b80, 0x07700, 0x08000}, | |
- {0x07f00, 0x07880, 0x08000}, | |
- {0x07980, 0x07900, 0x08000}, | |
- {0x07500, 0x07980, 0x08000}, | |
- {0x07000, 0x07a00, 0x08000}, | |
- {0x06d00, 0x07a80, 0x08000}, | |
- {0x08000, 0x07500, 0x07900}, | |
- | |
- {0x08000, 0x07900, 0x07d00}, | |
- {0x07c00, 0x07b80, 0x07f00}, | |
- {0x07200, 0x07780, 0x07980}, | |
- {0x07100, 0x07c00, 0x07e00}, | |
- {0x06f00, 0x07d80, 0x07f00}, | |
- {0x08000, 0x07500, 0x07600}, | |
- {0x08000, 0x07980, 0x07a00}, | |
- {0x07900, 0x08000, 0x07e80}, | |
- {0x07400, 0x08000, 0x07e00}, | |
- {0x07000, 0x08000, 0x07d80}, | |
- | |
- {0x08000, 0x07500, 0x07280}, | |
- {0x08000, 0x07a00, 0x07600}, | |
- {0x07e80, 0x08000, 0x07b80}, | |
- {0x07900, 0x08000, 0x07b00}, | |
- {0x07400, 0x08000, 0x07a00}, | |
- {0x07000, 0x08000, 0x07a00}, | |
- {0x08000, 0x07780, 0x07000}, | |
- {0x08000, 0x07e00, 0x07500}, | |
- {0x07b00, 0x08000, 0x07500}, | |
- {0x07580, 0x08000, 0x07600}, | |
- | |
- {0x08000, 0x07900, 0x06c80}, | |
- {0x08000, 0x07f00, 0x07200}, | |
- {0x07a00, 0x08000, 0x07180}, | |
- {0x07500, 0x08000, 0x07200}, | |
- {0x08000, 0x07900, 0x06a00}, | |
- {0x08000, 0x08000, 0x06f00}, | |
- {0x07980, 0x08000, 0x06e00}, | |
- {0x08000, 0x07900, 0x06800}, | |
- {0x08000, 0x08000, 0x06c00}, | |
- {0x08000, 0x07880, 0x06580}, | |
-}; | |
- | |
- | |
-static const struct mipi_dsi_lane_cfg lncfg = { | |
- /* DSI1_DSIPHY_LN_CFG */ | |
- .ln_cfg = { | |
- {0x80, 0xEF, 0x00}, | |
- {0x80, 0xEF, 0x00}, | |
- {0x80, 0xEF, 0x00}, | |
- {0x80, 0xEF, 0x00} | |
- }, | |
- /* DSI1_DSIPHY_LN_TEST_DATAPATH */ | |
- .ln_dpath = {0x00, 0x00, 0x00, 0x00}, | |
- /* DSI1_DSIPHY_LN_TEST_STR */ | |
- .ln_str = { | |
- {0x01, 0x66}, | |
- {0x01, 0x66}, | |
- {0x01, 0x66}, | |
- {0x01, 0x66} | |
- }, | |
- /* DSI1_DSIPHY_LNCK_CFG */ | |
- .lnck_cfg = {0x40, 0x67, 0x00}, | |
- /* DSI1_DSIPHY_LNCK_TEST_DATAPATH */ | |
- .lnck_dpath = 0x0, | |
- /* DSI1_DSIPHY_LNCK_TEST_STR */ | |
- .lnck_str = {0x01, 0x88}, | |
-}; | |
- | |
-static struct msm_panel_info pinfo; | |
- | |
-static struct msm_panel_info *get_panel_info(void) | |
-{ | |
- pinfo.xres = 1080; | |
- pinfo.yres = 1920; | |
- pinfo.type = MIPI_VIDEO_PANEL; | |
- pinfo.pdest = DISPLAY_1; | |
- pinfo.wait_cycle = 0; | |
- pinfo.bpp = 24; | |
- pinfo.lcdc.h_back_porch = 75; | |
- pinfo.lcdc.h_front_porch = 129; | |
- pinfo.lcdc.h_pulse_width = 5; | |
- pinfo.lcdc.v_back_porch = 4; | |
- pinfo.lcdc.v_front_porch = 8; | |
- pinfo.lcdc.v_pulse_width = 4; | |
- pinfo.lcdc.border_clr = 0; /* blk */ | |
- pinfo.lcdc.underflow_clr = 0x0; /* black */ | |
- pinfo.lcdc.hsync_skew = 0; | |
- pinfo.bl_max = 15; | |
- pinfo.bl_min = 1; | |
- pinfo.fb_num = 2; | |
- pinfo.clk_rate = 898000000; | |
- | |
- pinfo.mipi.mode = DSI_VIDEO_MODE; | |
- pinfo.mipi.pulse_mode_hsa_he = TRUE; | |
- pinfo.mipi.hfp_power_stop = FALSE; | |
- pinfo.mipi.hbp_power_stop = FALSE; | |
- pinfo.mipi.hsa_power_stop = FALSE; | |
- pinfo.mipi.eof_bllp_power_stop = TRUE; | |
- pinfo.mipi.bllp_power_stop = TRUE; | |
- pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; | |
- pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; | |
- pinfo.mipi.vc = 0; | |
- pinfo.mipi.dlane_swap = 0x00; | |
- pinfo.mipi.rgb_swap = DSI_RGB_SWAP_RGB; | |
- pinfo.mipi.r_sel = 0; | |
- pinfo.mipi.g_sel = 0; | |
- pinfo.mipi.b_sel = 0; | |
- pinfo.mipi.data_lane0 = TRUE; | |
- pinfo.mipi.data_lane1 = TRUE; | |
- pinfo.mipi.data_lane2 = TRUE; | |
- pinfo.mipi.data_lane3 = TRUE; | |
- pinfo.mipi.tx_eot_append = TRUE; | |
- pinfo.mipi.t_clk_post = 0x02; | |
- pinfo.mipi.t_clk_pre = 0x2d; | |
- pinfo.mipi.esc_byte_ratio = 9; | |
- pinfo.mipi.stream = 0; /* dma_p */ | |
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.frame_rate = 60; | |
- pinfo.mipi.dsi_phy_db = | |
- (struct mipi_dsi_phy_ctrl *)dsi_video_mode_phy_db; | |
- | |
- return &pinfo; | |
-} | |
- | |
-static struct dsi_controller dsi_video_controller_panel = { | |
- .get_panel_info = get_panel_info, | |
- .display_init = display_init_cmds, | |
- .display_on = display_on_cmds, | |
- .display_off = display_off_cmds, | |
- .read_id = read_ddb_cmds, | |
- .read_color = read_color_cmds, | |
-}; | |
- | |
-static char ddb_val_dlogo_02[] = { | |
- 0x12, 0x68, 0x69, 0x90, 0x02, 0x01, 0x00 | |
-}; | |
- | |
-static char ddb_val_dlogo_2a[] = { | |
- 0x12, 0x68, 0x69, 0x90, 0x2a, 0x01, 0x00 | |
-}; | |
- | |
-static char ddb_val_dlogo[] = { | |
- 0x12, 0x68, 0x69, 0x90, 0xff | |
-}; | |
- | |
-static char ddb_val_1a[] = { | |
- 0x12, 0x63, 0x94, 0x05, 0x1a, 0x01, 0x00 | |
-}; | |
- | |
-static char ddb_val_1a_02[] = { | |
- 0x12, 0x63, 0x94, 0x05, 0x1a, 0x02, 0x00 | |
-}; | |
- | |
-static char ddb_val[] = { | |
- 0x12, 0x63, 0x94, 0x05, 0xff | |
-}; | |
- | |
-const struct panel jdc_mdy70_panel_id_dlogo_02 = { | |
- .name = "mipi_video_jdc_Full_HD_mdy70_id_dlogo_02", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_dlogo_02, | |
- .id_num = ARRAY_SIZE(ddb_val_dlogo_02), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "mdy70", | |
- .panel_rev = "dlogo_02", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
- | |
-const struct panel jdc_mdy70_panel_id_dlogo_2a = { | |
- .name = "mipi_video_jdc_Full_HD_mdy70_id_dlogo_2a", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_dlogo_2a, | |
- .id_num = ARRAY_SIZE(ddb_val_dlogo_2a), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "mdy70", | |
- .panel_rev = "dlogo_2a", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
- | |
-const struct panel jdc_mdy70_panel_id_dlogo = { | |
- .name = "mipi_video_jdc_Full_HD_mdy70_id_dlogo", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_dlogo, | |
- .id_num = ARRAY_SIZE(ddb_val_dlogo), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "mdy70", | |
- .panel_rev = "dlogo", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
- | |
-const struct panel jdc_mdy70_panel_id_1a = { | |
- .name = "mipi_video_jdc_Full_HD_mdy70_id_1a", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_1a, | |
- .id_num = ARRAY_SIZE(ddb_val_1a), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "mdy70", | |
- .panel_rev = "1a", | |
- .plncfg = &lncfg, | |
-}; | |
- | |
-const struct panel jdc_mdy70_panel_id_1a_02 = { | |
- .name = "mipi_video_jdc_Full_HD_mdy70_id_1a_02", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_1a_02, | |
- .id_num = ARRAY_SIZE(ddb_val_1a_02), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "mdy70", | |
- .panel_rev = "1a_02", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
- | |
-const struct panel jdc_mdy70_panel_id = { | |
- .name = "mipi_video_jdc_Full_HD_mdy70", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val, | |
- .id_num = ARRAY_SIZE(ddb_val), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "mdy70", | |
- .panel_rev = "generic", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
diff --git a/drivers/video/msm/mipi_dsi_panel_r63311_jdc_mdy80.c b/drivers/video/msm/mipi_dsi_panel_r63311_jdc_mdy80.c | |
deleted file mode 100644 | |
index 2c175e7..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_r63311_jdc_mdy80.c | |
+++ /dev/null | |
@@ -1,239 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_r63311_jdc_mdy80.c | |
- * | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
- * | |
- * Author: Perumal Jayamani<[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2; as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
- | |
-#include "msm_fb.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-/* Initial Sequence */ | |
-static char soft_reset[] = { | |
- 0x01 | |
-}; | |
-static char mcap[] = { | |
- 0xB0, 0x00 | |
-}; | |
- | |
-static char set_addr_mode[] = { | |
- 0x36, 0xC0 | |
-}; | |
- | |
-static char exit_sleep[] = { | |
- 0x11 | |
-}; | |
- | |
-static char interface_setting[] = { | |
- 0xB3, 0x14, 0x00, 0x00, 0x20, 0x00, 0x00 | |
-}; | |
-static char interface_id_setting[] = { | |
- 0xB4, 0x0C, 0x00 | |
-}; | |
-static char dsi_control[] = { | |
- 0xB6, 0x3A, 0xD3 | |
-}; | |
- | |
-static char adaptive_brightness[] = { | |
- 0x55, 0x00 | |
-}; | |
- | |
-/* Display ON Sequence */ | |
-static char display_on[] = { | |
- 0x29 | |
-}; | |
- | |
-/* Display OFF Sequence */ | |
-static char display_off[] = { | |
- 0x28 | |
-}; | |
-static char enter_sleep[] = { | |
- 0x10 | |
-}; | |
- | |
-/* Reading DDB Sequence */ | |
-static char read_ddb_start[] = { | |
- 0xA1, 0x00 | |
-}; | |
- | |
-static struct dsi_cmd_desc display_init_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 5, | |
- sizeof(soft_reset), soft_reset}, | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, | |
- sizeof(mcap), mcap}, | |
- {DTYPE_DCS_WRITE1, 1, 0, 0, 0, | |
- sizeof(set_addr_mode), set_addr_mode}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 5, | |
- sizeof(exit_sleep), exit_sleep}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(interface_setting), interface_setting}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(interface_id_setting), interface_id_setting}, | |
- {DTYPE_GEN_LWRITE, 1, 0, 0, 0, | |
- sizeof(dsi_control), dsi_control}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_on_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE1, 1, 0, 0, 0, | |
- sizeof(adaptive_brightness), adaptive_brightness}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, | |
- sizeof(display_on), display_on}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_off_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 20, | |
- sizeof(display_off), display_off}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 80, | |
- sizeof(enter_sleep), enter_sleep}, | |
-}; | |
- | |
-static struct dsi_cmd_desc read_ddb_cmd_seq[] = { | |
- {DTYPE_DCS_READ, 1, 0, 1, 5, sizeof(read_ddb_start), read_ddb_start}, | |
-}; | |
- | |
-static const struct panel_cmd display_init_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_init_cmd_seq, | |
- ARRAY_SIZE(display_init_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_on_cmds[] = { | |
- {CMD_WAIT_MS, {.data = 120} }, | |
- {CMD_DSI, {.dsi_payload = {display_on_cmd_seq, | |
- ARRAY_SIZE(display_on_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_off_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_off_cmd_seq, | |
- ARRAY_SIZE(display_off_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_ddb_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_ddb_cmd_seq, | |
- ARRAY_SIZE(read_ddb_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db[] = { | |
- /* 1080*1920, RGB888, 4 Lane 60 fps video mode */ | |
- { | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0xe7, 0x39, 0x27, 0x00, 0x6a, 0x71, 0x2c, 0x3c, | |
- 0x41, 0x03, 0x04, 0xa0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0xb1, 0x31, 0xd9, 0x00, 0x50, 0x48, 0x63, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
- }, | |
-}; | |
- | |
-static struct msm_panel_info pinfo; | |
- | |
-static struct msm_panel_info *get_panel_info(void) | |
-{ | |
- pinfo.xres = 1080; | |
- pinfo.yres = 1920; | |
- pinfo.type = MIPI_VIDEO_PANEL; | |
- pinfo.pdest = DISPLAY_1; | |
- pinfo.wait_cycle = 0; | |
- pinfo.bpp = 24; | |
- pinfo.lcdc.h_back_porch = 80; | |
- pinfo.lcdc.h_front_porch = 125; | |
- pinfo.lcdc.h_pulse_width = 10; | |
- pinfo.lcdc.v_back_porch = 4; | |
- pinfo.lcdc.v_front_porch = 8; | |
- pinfo.lcdc.v_pulse_width = 4; | |
- pinfo.lcdc.border_clr = 0; /* blk */ | |
- pinfo.lcdc.underflow_clr = 0xff; /* blue */ | |
- pinfo.lcdc.hsync_skew = 0; | |
- pinfo.bl_max = 15; | |
- pinfo.bl_min = 1; | |
- pinfo.fb_num = 2; | |
- pinfo.clk_rate = 901384616; | |
- | |
- pinfo.mipi.mode = DSI_VIDEO_MODE; | |
- pinfo.mipi.pulse_mode_hsa_he = TRUE; | |
- pinfo.mipi.hfp_power_stop = FALSE; | |
- pinfo.mipi.hbp_power_stop = FALSE; | |
- pinfo.mipi.hsa_power_stop = FALSE; | |
- pinfo.mipi.eof_bllp_power_stop = TRUE; | |
- pinfo.mipi.bllp_power_stop = TRUE; | |
- pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; | |
- pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; | |
- pinfo.mipi.vc = 0; | |
- pinfo.mipi.rgb_swap = DSI_RGB_SWAP_BGR; | |
- pinfo.mipi.r_sel = 0; | |
- pinfo.mipi.g_sel = 0; | |
- pinfo.mipi.b_sel = 0; | |
- pinfo.mipi.data_lane0 = TRUE; | |
- pinfo.mipi.data_lane1 = TRUE; | |
- pinfo.mipi.data_lane2 = TRUE; | |
- pinfo.mipi.data_lane3 = TRUE; | |
- pinfo.mipi.tx_eot_append = TRUE; | |
- pinfo.mipi.t_clk_post = 0x02; | |
- pinfo.mipi.t_clk_pre = 0x2d; | |
- pinfo.mipi.esc_byte_ratio = 9; | |
- pinfo.mipi.stream = 0; /* dma_p */ | |
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.frame_rate = 60; | |
- pinfo.mipi.dsi_phy_db = | |
- (struct mipi_dsi_phy_ctrl *)dsi_video_mode_phy_db; | |
- | |
- return &pinfo; | |
-} | |
- | |
-static struct dsi_controller dsi_video_controller_panel = { | |
- .get_panel_info = get_panel_info, | |
- .display_init = display_init_cmds, | |
- .display_on = display_on_cmds, | |
- .display_off = display_off_cmds, | |
- .read_id = read_ddb_cmds, | |
-}; | |
- | |
-static char ddb_val_black[] = { | |
- 0x12, 0x62, 0x47, 0x90 | |
-}; | |
- | |
-static char ddb_val_white[] = { | |
- 0x12, 0x69, 0x45, 0x63 | |
-}; | |
- | |
-const struct panel jdc_mdy80_black_panel_id = { | |
- .name = "mipi_video_jdc_Full_HD_mdy80 black", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_black, | |
- .id_num = ARRAY_SIZE(ddb_val_black), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "1262-4790", | |
- .panel_rev = "generic", | |
-}; | |
- | |
-const struct panel jdc_mdy80_white_panel_id = { | |
- .name = "mipi_video_jdc_Full_HD_mdy80 white", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_white, | |
- .id_num = ARRAY_SIZE(ddb_val_white), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "1269-4563", | |
- .panel_rev = "generic", | |
-}; | |
diff --git a/drivers/video/msm/mipi_dsi_panel_r63311_sharp_ls050t3sx01.c b/drivers/video/msm/mipi_dsi_panel_r63311_sharp_ls050t3sx01.c | |
deleted file mode 100644 | |
index 50a3087..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_r63311_sharp_ls050t3sx01.c | |
+++ /dev/null | |
@@ -1,397 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_r63311_sharp_ls050t3sx01.c | |
- * | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
- * | |
- * Author: Yutaka Seijyou <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2; as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
- | |
-#include "msm_fb.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-/* Initial Sequence */ | |
-static char mcap[] = { | |
- 0xB0, 0x00 | |
-}; | |
-static char exit_sleep[] = { | |
- 0x11 | |
-}; | |
- | |
-/* Display ON Sequence */ | |
-static char display_on[] = { | |
- 0x29 | |
-}; | |
- | |
-/* Display OFF Sequence */ | |
-static char display_off[] = { | |
- 0x28 | |
-}; | |
-static char enter_sleep[] = { | |
- 0x10 | |
-}; | |
- | |
-/* Reading DDB Sequence */ | |
-static char read_ddb_start[] = { | |
- 0xA1, 0x00 | |
-}; | |
- | |
-/* Reading Color */ | |
-static char read_color[] = { | |
- 0xEF, 0x00 | |
-}; | |
- | |
-static struct dsi_cmd_desc display_init_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, | |
- sizeof(exit_sleep), exit_sleep}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_on_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, | |
- sizeof(display_on), display_on}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_off_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 20, | |
- sizeof(display_off), display_off}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 100, | |
- sizeof(enter_sleep), enter_sleep}, | |
-}; | |
- | |
-static struct dsi_cmd_desc read_ddb_cmd_seq[] = { | |
- {DTYPE_DCS_READ, 1, 0, 1, 5, sizeof(read_ddb_start), read_ddb_start}, | |
-}; | |
- | |
-static struct dsi_cmd_desc read_color_init_cmd[] = { | |
- {DTYPE_GEN_WRITE2, 1, 0, 0, 0, sizeof(mcap), mcap}, | |
-}; | |
- | |
-static struct dsi_cmd_desc read_color_cmd[] = { | |
- {DTYPE_GEN_READ1, 1, 0, 1, 5, sizeof(read_color), read_color}, | |
-}; | |
- | |
-static const struct panel_cmd display_init_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_init_cmd_seq, | |
- ARRAY_SIZE(display_init_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_on_cmds[] = { | |
- {CMD_WAIT_MS, {.data = 150} }, | |
- {CMD_DSI, {.dsi_payload = {display_on_cmd_seq, | |
- ARRAY_SIZE(display_on_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_off_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_off_cmd_seq, | |
- ARRAY_SIZE(display_off_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_ddb_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_ddb_cmd_seq, | |
- ARRAY_SIZE(read_ddb_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_color_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_color_init_cmd, | |
- ARRAY_SIZE(read_color_init_cmd)} } }, | |
- {CMD_DSI, {.dsi_payload = {read_color_cmd, | |
- ARRAY_SIZE(read_color_cmd)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db[] = { | |
- /* 1080*1920, RGB888, 4 Lane 60 fps video mode */ | |
- { | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0xe6, 0x38, 0x27, 0x00, 0x69, 0x72, 0x2b, 0x3c, | |
- 0x41, 0x03, 0x04, 0xa0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0xaf, 0x31, 0xd9, 0x00, 0x50, 0x48, 0x63, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
- }, | |
-}; | |
- | |
-static const struct mdp_pcc_cfg_rgb color_correction_data[] = { | |
- {0x08000, 0x06D00, 0x08000}, /* CLR01_GRN */ | |
- {0x07A00, 0x07100, 0x08000}, /* CLR02_GRN */ | |
- {0x07400, 0x07180, 0x08000}, /* CLR03_LG */ | |
- {0x07100, 0x07200, 0x08000}, /* CLR04_LG */ | |
- {0x06C80, 0x07180, 0x08000}, /* CLR05_YEL */ | |
- {0x06680, 0x07300, 0x08000}, /* CLR06_YEL */ | |
- {0x08000, 0x06B80, 0x07080}, /* CLR07_GRN */ | |
- {0x08000, 0x07400, 0x08000}, /* CLR08_GRN */ | |
- {0x07A00, 0x07700, 0x08000}, /* CLR09_LG */ | |
- {0x07600, 0x07780, 0x08000}, /* CLR10_LG */ | |
- {0x06F80, 0x07980, 0x08000}, /* CLR11_YEL */ | |
- {0x07080, 0x07E80, 0x08000}, /* CLR12_YEL */ | |
- {0x08000, 0x06B80, 0x06D00}, /* CLR13_LB */ | |
- {0x08000, 0x07380, 0x07480}, /* CLR14_LB */ | |
- {0x08000, 0x08000, 0x08000}, /* CLR15_WHT */ | |
- {0x07500, 0x08000, 0x07E80}, /* CLR16_ORG */ | |
- {0x07100, 0x08000, 0x07C80}, /* CLR17_ORG */ | |
- {0x08000, 0x06900, 0x06500}, /* CLR18_BLE */ | |
- {0x08000, 0x07300, 0x06F00}, /* CLR19_BLE */ | |
- {0x07F00, 0x08000, 0x07900}, /* CLR20_PUR */ | |
- {0x07E80, 0x08000, 0x07680}, /* CLR21_PUR */ | |
- {0x07380, 0x08000, 0x07600}, /* CLR22_RED */ | |
- {0x07080, 0x08000, 0x07900}, /* CLR23_RED */ | |
- {0x07A00, 0x08000, 0x07580}, /* CLR24_RED */ | |
- {0x06F00, 0x08000, 0x07200}, /* CLR25_RED */ | |
-}; | |
- | |
-static const struct mdp_pcc_cfg_rgb color_sub_area[] = { | |
- {0x05f00, 0x06900, 0x08000}, /* Area1 */ | |
- {0x06600, 0x06c00, 0x08000}, | |
- {0x06200, 0x06d00, 0x08000}, | |
- {0x06b80, 0x06d80, 0x08000}, | |
- {0x06700, 0x06f80, 0x08000}, | |
- {0x06400, 0x07100, 0x08000}, | |
- {0x07200, 0x07180, 0x08000}, | |
- {0x06d80, 0x07280, 0x08000}, | |
- {0x06a00, 0x07280, 0x08000}, | |
- {0x06680, 0x07500, 0x08000}, | |
- | |
- {0x07800, 0x07500, 0x08000}, | |
- {0x07400, 0x07580, 0x08000}, | |
- {0x06f00, 0x07600, 0x08000}, | |
- {0x06b80, 0x07700, 0x08000}, | |
- {0x07f00, 0x07880, 0x08000}, | |
- {0x07980, 0x07900, 0x08000}, | |
- {0x07500, 0x07980, 0x08000}, | |
- {0x07000, 0x07a00, 0x08000}, | |
- {0x06d00, 0x07a80, 0x08000}, | |
- {0x08000, 0x07500, 0x07900}, | |
- | |
- {0x08000, 0x07900, 0x07d00}, | |
- {0x07c00, 0x07b80, 0x07f00}, | |
- {0x07200, 0x07780, 0x07980}, | |
- {0x07100, 0x07c00, 0x07e00}, | |
- {0x06f00, 0x07d80, 0x07f00}, | |
- {0x08000, 0x07500, 0x07600}, | |
- {0x08000, 0x07980, 0x07a00}, | |
- {0x07900, 0x08000, 0x07e80}, | |
- {0x07400, 0x08000, 0x07e00}, | |
- {0x07000, 0x08000, 0x07d80}, | |
- | |
- {0x08000, 0x07500, 0x07280}, | |
- {0x08000, 0x07a00, 0x07600}, | |
- {0x07e80, 0x08000, 0x07b80}, | |
- {0x07900, 0x08000, 0x07b00}, | |
- {0x07400, 0x08000, 0x07a00}, | |
- {0x07000, 0x08000, 0x07a00}, | |
- {0x08000, 0x07780, 0x07000}, | |
- {0x08000, 0x07e00, 0x07500}, | |
- {0x07b00, 0x08000, 0x07500}, | |
- {0x07580, 0x08000, 0x07600}, | |
- | |
- {0x08000, 0x07900, 0x06c80}, | |
- {0x08000, 0x07f00, 0x07200}, | |
- {0x07a00, 0x08000, 0x07180}, | |
- {0x07500, 0x08000, 0x07200}, | |
- {0x08000, 0x07900, 0x06a00}, | |
- {0x08000, 0x08000, 0x06f00}, | |
- {0x07980, 0x08000, 0x06e00}, | |
- {0x08000, 0x07900, 0x06800}, | |
- {0x08000, 0x08000, 0x06c00}, | |
- {0x08000, 0x07880, 0x06580}, | |
-}; | |
- | |
-static const struct mipi_dsi_lane_cfg lncfg = { | |
- /* DSI1_DSIPHY_LN_CFG */ | |
- .ln_cfg = { | |
- {0x80, 0xEF, 0x00}, | |
- {0x80, 0xEF, 0x00}, | |
- {0x80, 0xEF, 0x00}, | |
- {0x80, 0xEF, 0x00} | |
- }, | |
- /* DSI1_DSIPHY_LN_TEST_DATAPATH */ | |
- .ln_dpath = {0x00, 0x00, 0x00, 0x00}, | |
- /* DSI1_DSIPHY_LN_TEST_STR */ | |
- .ln_str = { | |
- {0x01, 0x66}, | |
- {0x01, 0x66}, | |
- {0x01, 0x66}, | |
- {0x01, 0x66} | |
- }, | |
- /* DSI1_DSIPHY_LNCK_CFG */ | |
- .lnck_cfg = {0x40, 0x67, 0x00}, | |
- /* DSI1_DSIPHY_LNCK_TEST_DATAPATH */ | |
- .lnck_dpath = 0x0, | |
- /* DSI1_DSIPHY_LNCK_TEST_STR */ | |
- .lnck_str = {0x01, 0x88}, | |
-}; | |
- | |
-static struct msm_panel_info pinfo; | |
- | |
-static struct msm_panel_info *get_panel_info(void) | |
-{ | |
- pinfo.xres = 1080; | |
- pinfo.yres = 1920; | |
- pinfo.type = MIPI_VIDEO_PANEL; | |
- pinfo.pdest = DISPLAY_1; | |
- pinfo.wait_cycle = 0; | |
- pinfo.bpp = 24; | |
- pinfo.lcdc.h_back_porch = 64; | |
- pinfo.lcdc.h_front_porch = 134; | |
- pinfo.lcdc.h_pulse_width = 16; | |
- pinfo.lcdc.v_back_porch = 4; | |
- pinfo.lcdc.v_front_porch = 4; | |
- pinfo.lcdc.v_pulse_width = 2; | |
- pinfo.lcdc.border_clr = 0; /* blk */ | |
- pinfo.lcdc.underflow_clr = 0x0; /* black */ | |
- pinfo.lcdc.hsync_skew = 0; | |
- pinfo.bl_max = 15; | |
- pinfo.bl_min = 1; | |
- pinfo.fb_num = 2; | |
- pinfo.clk_rate = 899000000; | |
- | |
- pinfo.mipi.mode = DSI_VIDEO_MODE; | |
- pinfo.mipi.pulse_mode_hsa_he = TRUE; | |
- pinfo.mipi.hfp_power_stop = FALSE; | |
- pinfo.mipi.hbp_power_stop = FALSE; | |
- pinfo.mipi.hsa_power_stop = FALSE; | |
- pinfo.mipi.eof_bllp_power_stop = TRUE; | |
- pinfo.mipi.bllp_power_stop = TRUE; | |
- pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; | |
- pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; | |
- pinfo.mipi.vc = 0; | |
- pinfo.mipi.dlane_swap = 0x00; | |
- pinfo.mipi.rgb_swap = DSI_RGB_SWAP_RGB; | |
- pinfo.mipi.r_sel = 0; | |
- pinfo.mipi.g_sel = 0; | |
- pinfo.mipi.b_sel = 0; | |
- pinfo.mipi.data_lane0 = TRUE; | |
- pinfo.mipi.data_lane1 = TRUE; | |
- pinfo.mipi.data_lane2 = TRUE; | |
- pinfo.mipi.data_lane3 = TRUE; | |
- pinfo.mipi.tx_eot_append = TRUE; | |
- pinfo.mipi.t_clk_post = 0x02; | |
- pinfo.mipi.t_clk_pre = 0x2d; | |
- pinfo.mipi.esc_byte_ratio = 9; | |
- pinfo.mipi.stream = 0; /* dma_p */ | |
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.frame_rate = 60; | |
- pinfo.mipi.dsi_phy_db = | |
- (struct mipi_dsi_phy_ctrl *)dsi_video_mode_phy_db; | |
- | |
- return &pinfo; | |
-} | |
- | |
-static struct dsi_controller dsi_video_controller_panel = { | |
- .get_panel_info = get_panel_info, | |
- .display_init = display_init_cmds, | |
- .display_on = display_on_cmds, | |
- .display_off = display_off_cmds, | |
- .read_id = read_ddb_cmds, | |
- .read_color = read_color_cmds, | |
-}; | |
- | |
-static char ddb_val_dlogo_01[] = { | |
- 0x12, 0x68, 0x69, 0x92, 0x01, 0x01, 0x00 | |
-}; | |
- | |
-static char ddb_val_dlogo[] = { | |
- 0x12, 0x68, 0x69, 0x92, 0xff | |
-}; | |
- | |
-static char ddb_val_1a[] = { | |
- 0x12, 0x63, 0x94, 0x06, 0x1a, 0x01, 0x00 | |
-}; | |
- | |
-static char ddb_val_1a_02[] = { | |
- 0x12, 0x63, 0x94, 0x06, 0x1a, 0x02, 0x00 | |
-}; | |
- | |
-static char ddb_val[] = { | |
- 0x12, 0x63, 0x94, 0x06, 0xff | |
-}; | |
- | |
-const struct panel sharp_ls050t3sx01_panel_id_dlogo_01 = { | |
- .name = "mipi_video_sharp_Full_HD_ls050t3sx01_id_dlogo_01", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_dlogo_01, | |
- .id_num = ARRAY_SIZE(ddb_val_dlogo_01), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "ls050t3sx01", | |
- .panel_rev = "dlogo_01", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
- | |
-const struct panel sharp_ls050t3sx01_panel_id_dlogo = { | |
- .name = "mipi_video_sharp_Full_HD_ls050t3sx01_id_dlogo", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_dlogo, | |
- .id_num = ARRAY_SIZE(ddb_val_dlogo), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "ls050t3sx01", | |
- .panel_rev = "dlogo", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
- | |
-const struct panel sharp_ls050t3sx01_panel_id_1a = { | |
- .name = "mipi_video_sharp_Full_HD_ls050t3sx01_id_1a", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_1a, | |
- .id_num = ARRAY_SIZE(ddb_val_1a), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "ls050t3sx01", | |
- .panel_rev = "1a", | |
- .plncfg = &lncfg, | |
-}; | |
- | |
-const struct panel sharp_ls050t3sx01_panel_id_1a_02 = { | |
- .name = "mipi_video_sharp_Full_HD_ls050t3sx01_id_1a_02", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_1a_02, | |
- .id_num = ARRAY_SIZE(ddb_val_1a_02), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "ls050t3sx01", | |
- .panel_rev = "1a_02", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
- | |
-const struct panel sharp_ls050t3sx01_panel_id = { | |
- .name = "mipi_video_sharp_Full_HD_ls050t3sx01", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val, | |
- .id_num = ARRAY_SIZE(ddb_val), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "ls050t3sx01", | |
- .panel_rev = "generic", | |
- .plncfg = &lncfg, | |
- .color_correction_tbl = color_correction_data, | |
- .color_subdivision_tbl = color_sub_area, | |
-}; | |
diff --git a/drivers/video/msm/mipi_dsi_panel_r63311_sharp_ls050t3sx02.c b/drivers/video/msm/mipi_dsi_panel_r63311_sharp_ls050t3sx02.c | |
deleted file mode 100644 | |
index 088127d..0000000 | |
--- a/drivers/video/msm/mipi_dsi_panel_r63311_sharp_ls050t3sx02.c | |
+++ /dev/null | |
@@ -1,218 +0,0 @@ | |
-/* drivers/video/msm/mipi_dsi_panel_r63306_sharp_ls043k3sx04.c | |
- * | |
- * Copyright (c) 2012 Sony Mobile Communications AB. | |
- * | |
- * Author: Johan Olson <[email protected]> | |
- * Author: Joakim Wesslen <[email protected]> | |
- * Author: Perumal Jayamani <[email protected]> | |
- * | |
- * This program is free software; you can redistribute it and/or modify | |
- * it under the terms of the GNU General Public License version 2; as | |
- * published by the Free Software Foundation; either version 2 | |
- * of the License, or (at your option) any later version. | |
- */ | |
- | |
- | |
-#include "msm_fb.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_dsi_panel_driver.h" | |
- | |
-static char exit_sleep[] = { | |
- 0x11 | |
-}; | |
- | |
-static char display_on[] = { | |
- 0x29 | |
-}; | |
- | |
-static char display_off[] = { | |
- 0x28 | |
-}; | |
- | |
-static char enter_sleep[] = { | |
- 0x10 | |
-}; | |
- | |
-static char read_ddb_start[] = { | |
- 0xA1, 0x00 | |
-}; | |
- | |
-static char adaptive_brightness[] = { | |
- 0x55, 0x00 | |
-}; | |
- | |
-static struct dsi_cmd_desc display_init_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(exit_sleep), exit_sleep}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_on_cmd_seq[] = { | |
- {DTYPE_DCS_WRITE1, 1, 0, 0, 0, | |
- sizeof(adaptive_brightness), adaptive_brightness}, | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(display_on), display_on}, | |
-}; | |
- | |
-static struct dsi_cmd_desc display_off_cmd_seq[] = { | |
- /* Spec says delay > 20 ms */ | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 21, sizeof(display_off), display_off}, | |
- /* Spec says delay > 101 ms */ | |
- {DTYPE_DCS_WRITE, 1, 0, 0, 101, sizeof(enter_sleep), enter_sleep} | |
-}; | |
- | |
-static struct dsi_cmd_desc read_ddb_cmd_seq[] = { | |
- {DTYPE_DCS_READ, 1, 0, 1, 5, sizeof(read_ddb_start), read_ddb_start}, | |
-}; | |
- | |
-static const struct panel_cmd display_init_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_init_cmd_seq, | |
- ARRAY_SIZE(display_init_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_on_cmds[] = { | |
- {CMD_WAIT_MS, {.data = 151} }, /* Spec says > 150 ms */ | |
- {CMD_DSI, {.dsi_payload = {display_on_cmd_seq, | |
- ARRAY_SIZE(display_on_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd display_off_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {display_off_cmd_seq, | |
- ARRAY_SIZE(display_off_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct panel_cmd read_ddb_cmds[] = { | |
- {CMD_DSI, {.dsi_payload = {read_ddb_cmd_seq, | |
- ARRAY_SIZE(read_ddb_cmd_seq)} } }, | |
- {CMD_END, {} }, | |
-}; | |
- | |
-static const struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db[] = { | |
- { | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0xDE, 0x36, 0x24, 0x00, 0x66, 0x6E, 0x2A, 0x39, | |
- 0x3E, 0x03, 0x04, 0xA0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0x9D, 0x31, 0xd9, 0x00, 0x50, 0x48, 0x63, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
- }, | |
-}; | |
- | |
-static struct msm_panel_info pinfo; | |
- | |
-static struct msm_panel_info *get_panel_info(void) | |
-{ | |
- pinfo.xres = 1080; | |
- pinfo.yres = 1920; | |
- pinfo.type = MIPI_VIDEO_PANEL; | |
- pinfo.pdest = DISPLAY_1; | |
- pinfo.wait_cycle = 0; | |
- pinfo.bpp = 24; | |
- pinfo.lcdc.h_back_porch = 48; | |
- pinfo.lcdc.h_front_porch = 100; | |
- pinfo.lcdc.h_pulse_width = 12; | |
- pinfo.lcdc.v_back_porch = 4; | |
- pinfo.lcdc.v_front_porch = 4; | |
- pinfo.lcdc.v_pulse_width = 2; | |
- pinfo.lcdc.border_clr = 0; /* black */ | |
- pinfo.lcdc.underflow_clr = 0x0; | |
- pinfo.lcdc.hsync_skew = 0; | |
- pinfo.bl_max = 15; | |
- pinfo.bl_min = 1; | |
- pinfo.fb_num = 2; | |
- pinfo.clk_rate = 859846200; | |
- | |
- pinfo.mipi.mode = DSI_VIDEO_MODE; | |
- pinfo.mipi.pulse_mode_hsa_he = TRUE; | |
- pinfo.mipi.hfp_power_stop = FALSE; | |
- pinfo.mipi.hbp_power_stop = FALSE; | |
- pinfo.mipi.hsa_power_stop = FALSE; | |
- pinfo.mipi.eof_bllp_power_stop = TRUE; | |
- pinfo.mipi.bllp_power_stop = TRUE; | |
- pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; | |
- pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; | |
- pinfo.mipi.vc = 0; | |
- pinfo.mipi.rgb_swap = DSI_RGB_SWAP_BGR; | |
- pinfo.mipi.r_sel = 0; | |
- pinfo.mipi.g_sel = 0; | |
- pinfo.mipi.b_sel = 0; | |
- pinfo.mipi.data_lane0 = TRUE; | |
- pinfo.mipi.data_lane1 = TRUE; | |
- pinfo.mipi.data_lane2 = TRUE; | |
- pinfo.mipi.data_lane3 = TRUE; | |
- pinfo.mipi.tx_eot_append = TRUE; | |
- pinfo.mipi.t_clk_post = 0x02; | |
- pinfo.mipi.t_clk_pre = 0x2c; | |
- pinfo.mipi.esc_byte_ratio = 9; | |
- pinfo.mipi.stream = 0; /* dma_p */ | |
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.frame_rate = 60; | |
- pinfo.mipi.dsi_phy_db = | |
- (struct mipi_dsi_phy_ctrl *)dsi_video_mode_phy_db; | |
- | |
- return &pinfo; | |
-} | |
- | |
-static struct dsi_controller dsi_video_controller_panel = { | |
- .get_panel_info = get_panel_info, | |
- .display_init = display_init_cmds, | |
- .display_on = display_on_cmds, | |
- .display_off = display_off_cmds, | |
- .read_id = read_ddb_cmds, | |
-}; | |
- | |
-static char ddb_val_12624797[] = { | |
- 0x12, 0x62, 0x47, 0x97 | |
-}; | |
- | |
-const struct panel sharp_ls050t3sx02_r63311_12624797 = { | |
- .name = "Sharp LS050T3SX02 R63311, 1262-4797 black", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_12624797, | |
- .id_num = ARRAY_SIZE(ddb_val_12624797), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "1262-4791", | |
- .panel_rev = "generic", | |
-}; | |
- | |
-static char ddb_val_black[] = { | |
- 0x12, 0x62, 0x47, 0x91 | |
-}; | |
- | |
-const struct panel sharp_ls050t3sx02_r63311_black_panel_id = { | |
- .name = "Sharp LS050T3SX02 R63311 black", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_black, | |
- .id_num = ARRAY_SIZE(ddb_val_black), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "1262-4791", | |
- .panel_rev = "generic", | |
-}; | |
- | |
-static char ddb_val_white[] = { | |
- 0x12, 0x69, 0x65, 0x61 | |
-}; | |
- | |
-const struct panel sharp_ls050t3sx02_r63311_white_panel_id = { | |
- .name = "Sharp LS050T3SX02 R63311 white", | |
- .pctrl = &dsi_video_controller_panel, | |
- .id = ddb_val_white, | |
- .id_num = ARRAY_SIZE(ddb_val_white), | |
- .width = 62, | |
- .height = 110, | |
- .send_video_data_before_display_on = true, | |
- .panel_id = "1269-6561", | |
- .panel_rev = "generic", | |
-}; | |
diff --git a/drivers/video/msm/mipi_renesas.c b/drivers/video/msm/mipi_renesas.c | |
index 9888fa8..3fa2606 100644 | |
--- a/drivers/video/msm/mipi_renesas.c | |
+++ b/drivers/video/msm/mipi_renesas.c | |
@@ -16,8 +16,7 @@ | |
#include <mach/socinfo.h> | |
#define RENESAS_CMD_DELAY 0 /* 50 */ | |
-#define RENESAS_SLEEP_OFF_DELAY 120 | |
-#define RENESAS_SLEEP_ON_DELAY 120 | |
+#define RENESAS_SLEEP_OFF_DELAY 50 | |
static struct msm_panel_common_pdata *mipi_renesas_pdata; | |
static struct dsi_buf renesas_tx_buf; | |
@@ -25,16 +24,162 @@ static struct dsi_buf renesas_rx_buf; | |
static int mipi_renesas_lcd_init(void); | |
-static char config_sleep_in[2] = {0x10, 0x00}; | |
static char config_sleep_out[2] = {0x11, 0x00}; | |
+static char config_CMD_MODE[2] = {0x40, 0x01}; | |
+static char config_WRTXHT[7] = {0x92, 0x16, 0x08, 0x08, 0x00, 0x01, 0xe0}; | |
+static char config_WRTXVT[7] = {0x8b, 0x02, 0x02, 0x02, 0x00, 0x03, 0x60}; | |
+static char config_PLL2NR[2] = {0xa0, 0x24}; | |
+static char config_PLL2NF1[2] = {0xa2, 0xd0}; | |
+static char config_PLL2NF2[2] = {0xa4, 0x00}; | |
+static char config_PLL2BWADJ1[2] = {0xa6, 0xd0}; | |
+static char config_PLL2BWADJ2[2] = {0xa8, 0x00}; | |
+static char config_PLL2CTL[2] = {0xaa, 0x00}; | |
+static char config_DBICBR[2] = {0x48, 0x03}; | |
+static char config_DBICTYPE[2] = {0x49, 0x00}; | |
+static char config_DBICSET1[2] = {0x4a, 0x1c}; | |
+static char config_DBICADD[2] = {0x4b, 0x00}; | |
+static char config_DBICCTL[2] = {0x4e, 0x01}; | |
+/* static char config_COLMOD_565[2] = {0x3a, 0x05}; */ | |
+/* static char config_COLMOD_666PACK[2] = {0x3a, 0x06}; */ | |
+static char config_COLMOD_888[2] = {0x3a, 0x07}; | |
+static char config_MADCTL[2] = {0x36, 0x00}; | |
+static char config_DBIOC[2] = {0x82, 0x40}; | |
+static char config_CASET[7] = {0x2a, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdf }; | |
+static char config_PASET[7] = {0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x5f }; | |
+static char config_TXON[2] = {0x81, 0x00}; | |
+static char config_BLSET_TM[2] = {0xff, 0x6c}; | |
+static char config_DSIRXCTL[2] = {0x41, 0x01}; | |
+static char config_TEON[2] = {0x35, 0x00}; | |
+static char config_TEOFF[1] = {0x34}; | |
-static char config_display_off[2] = {0x28, 0x00}; | |
-static char config_display_on[2] = {0x29, 0x00}; | |
+static char config_AGCPSCTL_TM[2] = {0x56, 0x08}; | |
-static struct dsi_cmd_desc renesas_sleep_on_cmds[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, RENESAS_SLEEP_ON_DELAY, | |
- sizeof(config_sleep_in), config_sleep_in } | |
-}; | |
+static char config_DBICADD70[2] = {0x4b, 0x70}; | |
+static char config_DBICSET_15[2] = {0x4a, 0x15}; | |
+static char config_DBICADD72[2] = {0x4b, 0x72}; | |
+ | |
+static char config_Power_Ctrl_2a_cmd[3] = {0x4c, 0x40, 0x10}; | |
+static char config_Auto_Sequencer_Setting_a_cmd[3] = {0x4c, 0x00, 0x00}; | |
+static char Driver_Output_Ctrl_indx[3] = {0x4c, 0x00, 0x01}; | |
+static char Driver_Output_Ctrl_cmd[3] = {0x4c, 0x03, 0x10}; | |
+static char config_LCD_drive_AC_Ctrl_indx[3] = {0x4c, 0x00, 0x02}; | |
+static char config_LCD_drive_AC_Ctrl_cmd[3] = {0x4c, 0x01, 0x00}; | |
+static char config_Entry_Mode_indx[3] = {0x4c, 0x00, 0x03}; | |
+static char config_Entry_Mode_cmd[3] = {0x4c, 0x00, 0x00}; | |
+static char config_Display_Ctrl_1_indx[3] = {0x4c, 0x00, 0x07}; | |
+static char config_Display_Ctrl_1_cmd[3] = {0x4c, 0x00, 0x00}; | |
+static char config_Display_Ctrl_2_indx[3] = {0x4c, 0x00, 0x08}; | |
+static char config_Display_Ctrl_2_cmd[3] = {0x4c, 0x00, 0x04}; | |
+static char config_Display_Ctrl_3_indx[3] = {0x4c, 0x00, 0x09}; | |
+static char config_Display_Ctrl_3_cmd[3] = {0x4c, 0x00, 0x0c}; | |
+static char config_Display_IF_Ctrl_1_indx[3] = {0x4c, 0x00, 0x0c}; | |
+static char config_Display_IF_Ctrl_1_cmd[3] = {0x4c, 0x40, 0x10}; | |
+static char config_Display_IF_Ctrl_2_indx[3] = {0x4c, 0x00, 0x0e}; | |
+static char config_Display_IF_Ctrl_2_cmd[3] = {0x4c, 0x00, 0x00}; | |
+ | |
+static char config_Panel_IF_Ctrl_1_indx[3] = {0x4c, 0x00, 0x20}; | |
+static char config_Panel_IF_Ctrl_1_cmd[3] = {0x4c, 0x01, 0x3f}; | |
+static char config_Panel_IF_Ctrl_3_indx[3] = {0x4c, 0x00, 0x22}; | |
+static char config_Panel_IF_Ctrl_3_cmd[3] = {0x4c, 0x76, 0x00}; | |
+static char config_Panel_IF_Ctrl_4_indx[3] = {0x4c, 0x00, 0x23}; | |
+static char config_Panel_IF_Ctrl_4_cmd[3] = {0x4c, 0x1c, 0x0a}; | |
+static char config_Panel_IF_Ctrl_5_indx[3] = {0x4c, 0x00, 0x24}; | |
+static char config_Panel_IF_Ctrl_5_cmd[3] = {0x4c, 0x1c, 0x2c}; | |
+static char config_Panel_IF_Ctrl_6_indx[3] = {0x4c, 0x00, 0x25}; | |
+static char config_Panel_IF_Ctrl_6_cmd[3] = {0x4c, 0x1c, 0x4e}; | |
+static char config_Panel_IF_Ctrl_8_indx[3] = {0x4c, 0x00, 0x27}; | |
+static char config_Panel_IF_Ctrl_8_cmd[3] = {0x4c, 0x00, 0x00}; | |
+static char config_Panel_IF_Ctrl_9_indx[3] = {0x4c, 0x00, 0x28}; | |
+static char config_Panel_IF_Ctrl_9_cmd[3] = {0x4c, 0x76, 0x0c}; | |
+ | |
+ | |
+static char config_gam_adjust_00_indx[3] = {0x4c, 0x03, 0x00}; | |
+static char config_gam_adjust_00_cmd[3] = {0x4c, 0x00, 0x00}; | |
+static char config_gam_adjust_01_indx[3] = {0x4c, 0x03, 0x01}; | |
+static char config_gam_adjust_01_cmd[3] = {0x4c, 0x05, 0x02}; | |
+static char config_gam_adjust_02_indx[3] = {0x4c, 0x03, 0x02}; | |
+static char config_gam_adjust_02_cmd[3] = {0x4c, 0x07, 0x05}; | |
+static char config_gam_adjust_03_indx[3] = {0x4c, 0x03, 0x03}; | |
+static char config_gam_adjust_03_cmd[3] = {0x4c, 0x00, 0x00}; | |
+static char config_gam_adjust_04_indx[3] = {0x4c, 0x03, 0x04}; | |
+static char config_gam_adjust_04_cmd[3] = {0x4c, 0x02, 0x00}; | |
+static char config_gam_adjust_05_indx[3] = {0x4c, 0x03, 0x05}; | |
+static char config_gam_adjust_05_cmd[3] = {0x4c, 0x07, 0x07}; | |
+static char config_gam_adjust_06_indx[3] = {0x4c, 0x03, 0x06}; | |
+static char config_gam_adjust_06_cmd[3] = {0x4c, 0x10, 0x10}; | |
+static char config_gam_adjust_07_indx[3] = {0x4c, 0x03, 0x07}; | |
+static char config_gam_adjust_07_cmd[3] = {0x4c, 0x02, 0x02}; | |
+static char config_gam_adjust_08_indx[3] = {0x4c, 0x03, 0x08}; | |
+static char config_gam_adjust_08_cmd[3] = {0x4c, 0x07, 0x04}; | |
+static char config_gam_adjust_09_indx[3] = {0x4c, 0x03, 0x09}; | |
+static char config_gam_adjust_09_cmd[3] = {0x4c, 0x07, 0x07}; | |
+static char config_gam_adjust_0A_indx[3] = {0x4c, 0x03, 0x0a}; | |
+static char config_gam_adjust_0A_cmd[3] = {0x4c, 0x00, 0x00}; | |
+static char config_gam_adjust_0B_indx[3] = {0x4c, 0x03, 0x0b}; | |
+static char config_gam_adjust_0B_cmd[3] = {0x4c, 0x00, 0x00}; | |
+static char config_gam_adjust_0C_indx[3] = {0x4c, 0x03, 0x0c}; | |
+static char config_gam_adjust_0C_cmd[3] = {0x4c, 0x07, 0x07}; | |
+static char config_gam_adjust_0D_indx[3] = {0x4c, 0x03, 0x0d}; | |
+static char config_gam_adjust_0D_cmd[3] = {0x4c, 0x10, 0x10}; | |
+static char config_gam_adjust_10_indx[3] = {0x4c, 0x03, 0x10}; | |
+static char config_gam_adjust_10_cmd[3] = {0x4c, 0x01, 0x04}; | |
+static char config_gam_adjust_11_indx[3] = {0x4c, 0x03, 0x11}; | |
+static char config_gam_adjust_11_cmd[3] = {0x4c, 0x05, 0x03}; | |
+static char config_gam_adjust_12_indx[3] = {0x4c, 0x03, 0x12}; | |
+static char config_gam_adjust_12_cmd[3] = {0x4c, 0x03, 0x04}; | |
+static char config_gam_adjust_15_indx[3] = {0x4c, 0x03, 0x15}; | |
+static char config_gam_adjust_15_cmd[3] = {0x4c, 0x03, 0x04}; | |
+static char config_gam_adjust_16_indx[3] = {0x4c, 0x03, 0x16}; | |
+static char config_gam_adjust_16_cmd[3] = {0x4c, 0x03, 0x1c}; | |
+static char config_gam_adjust_17_indx[3] = {0x4c, 0x03, 0x17}; | |
+static char config_gam_adjust_17_cmd[3] = {0x4c, 0x02, 0x04}; | |
+static char config_gam_adjust_18_indx[3] = {0x4c, 0x03, 0x18}; | |
+static char config_gam_adjust_18_cmd[3] = {0x4c, 0x04, 0x02}; | |
+static char config_gam_adjust_19_indx[3] = {0x4c, 0x03, 0x19}; | |
+static char config_gam_adjust_19_cmd[3] = {0x4c, 0x03, 0x05}; | |
+static char config_gam_adjust_1C_indx[3] = {0x4c, 0x03, 0x1c}; | |
+static char config_gam_adjust_1C_cmd[3] = {0x4c, 0x07, 0x07}; | |
+static char config_gam_adjust_1D_indx[3] = {0x4c, 0x03, 0x1D}; | |
+static char config_gam_adjust_1D_cmd[3] = {0x4c, 0x02, 0x1f}; | |
+static char config_gam_adjust_20_indx[3] = {0x4c, 0x03, 0x20}; | |
+static char config_gam_adjust_20_cmd[3] = {0x4c, 0x05, 0x07}; | |
+static char config_gam_adjust_21_indx[3] = {0x4c, 0x03, 0x21}; | |
+static char config_gam_adjust_21_cmd[3] = {0x4c, 0x06, 0x04}; | |
+static char config_gam_adjust_22_indx[3] = {0x4c, 0x03, 0x22}; | |
+static char config_gam_adjust_22_cmd[3] = {0x4c, 0x04, 0x05}; | |
+static char config_gam_adjust_27_indx[3] = {0x4c, 0x03, 0x27}; | |
+static char config_gam_adjust_27_cmd[3] = {0x4c, 0x02, 0x03}; | |
+static char config_gam_adjust_28_indx[3] = {0x4c, 0x03, 0x28}; | |
+static char config_gam_adjust_28_cmd[3] = {0x4c, 0x03, 0x00}; | |
+static char config_gam_adjust_29_indx[3] = {0x4c, 0x03, 0x29}; | |
+static char config_gam_adjust_29_cmd[3] = {0x4c, 0x00, 0x02}; | |
+ | |
+static char config_Power_Ctrl_1_indx[3] = {0x4c, 0x01, 0x00}; | |
+static char config_Power_Ctrl_1b_cmd[3] = {0x4c, 0x36, 0x3c}; | |
+static char config_Power_Ctrl_2_indx[3] = {0x4c, 0x01, 0x01}; | |
+static char config_Power_Ctrl_2b_cmd[3] = {0x4c, 0x40, 0x03}; | |
+static char config_Power_Ctrl_3_indx[3] = {0x4c, 0x01, 0x02}; | |
+static char config_Power_Ctrl_3a_cmd[3] = {0x4c, 0x00, 0x01}; | |
+static char config_Power_Ctrl_4_indx[3] = {0x4c, 0x01, 0x03}; | |
+static char config_Power_Ctrl_4a_cmd[3] = {0x4c, 0x3c, 0x58}; | |
+static char config_Power_Ctrl_6_indx[3] = {0x4c, 0x01, 0x0c}; | |
+static char config_Power_Ctrl_6a_cmd[3] = {0x4c, 0x01, 0x35}; | |
+ | |
+static char config_Auto_Sequencer_Setting_b_cmd[3] = {0x4c, 0x00, 0x02}; | |
+ | |
+static char config_Panel_IF_Ctrl_10_indx[3] = {0x4c, 0x00, 0x29}; | |
+static char config_Panel_IF_Ctrl_10a_cmd[3] = {0x4c, 0x03, 0xbf}; | |
+static char config_Auto_Sequencer_Setting_indx[3] = {0x4c, 0x01, 0x06}; | |
+static char config_Auto_Sequencer_Setting_c_cmd[3] = {0x4c, 0x00, 0x03}; | |
+static char config_Power_Ctrl_2c_cmd[3] = {0x4c, 0x40, 0x10}; | |
+ | |
+static char config_VIDEO[2] = {0x40, 0x00}; | |
+ | |
+static char config_Panel_IF_Ctrl_10_indx_off[3] = {0x4C, 0x00, 0x29}; | |
+ | |
+static char config_Panel_IF_Ctrl_10b_cmd_off[3] = {0x4C, 0x00, 0x02}; | |
+ | |
+static char config_Power_Ctrl_1a_cmd[3] = {0x4C, 0x30, 0x00}; | |
static struct dsi_cmd_desc renesas_sleep_off_cmds[] = { | |
{DTYPE_DCS_WRITE, 1, 0, 0, RENESAS_SLEEP_OFF_DELAY, | |
@@ -42,16 +187,937 @@ static struct dsi_cmd_desc renesas_sleep_off_cmds[] = { | |
}; | |
static struct dsi_cmd_desc renesas_display_off_cmds[] = { | |
- {DTYPE_DCS_WRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
- sizeof(config_display_off), config_display_off }, | |
+ /* Choosing Command Mode */ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_CMD_MODE), config_CMD_MODE }, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_indx), | |
+ config_Auto_Sequencer_Setting_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_b_cmd), | |
+ config_Auto_Sequencer_Setting_b_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY * 2, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ /* After waiting >= 5 frames, turn OFF RGB signals | |
+ This is done by on DSI/MDP (depends on Vid/Cmd Mode. */ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_indx), | |
+ config_Auto_Sequencer_Setting_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_a_cmd), | |
+ config_Auto_Sequencer_Setting_a_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_10_indx_off), | |
+ config_Panel_IF_Ctrl_10_indx_off}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_10b_cmd_off), | |
+ config_Panel_IF_Ctrl_10b_cmd_off}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_1_indx), | |
+ config_Power_Ctrl_1_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_1a_cmd), | |
+ config_Power_Ctrl_1a_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_TEOFF), config_TEOFF}, | |
}; | |
static struct dsi_cmd_desc renesas_display_on_cmds[] = { | |
+ /* Choosing Command Mode */ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_CMD_MODE), config_CMD_MODE }, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_WRTXHT), config_WRTXHT }, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_WRTXVT), config_WRTXVT }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_PLL2NR), config_PLL2NR }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_PLL2NF1), config_PLL2NF1 }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_PLL2NF2), config_PLL2NF2 }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_PLL2BWADJ1), config_PLL2BWADJ1}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_PLL2BWADJ2), config_PLL2BWADJ2}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_PLL2CTL), config_PLL2CTL}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICBR), config_DBICBR}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICTYPE), config_DBICTYPE}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET1), config_DBICSET1}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD), config_DBICADD}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICCTL), config_DBICCTL}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_COLMOD_888), config_COLMOD_888}, | |
+ /* Choose config_COLMOD_565 or config_COLMOD_666PACK for other modes */ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_MADCTL), config_MADCTL}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBIOC), config_DBIOC}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_CASET), config_CASET}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_PASET), config_PASET}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DSIRXCTL), config_DSIRXCTL}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_TEON), config_TEON}, | |
{DTYPE_DCS_WRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
- sizeof(config_display_on), config_display_on }, | |
+ sizeof(config_TXON), config_TXON}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_BLSET_TM), config_BLSET_TM}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_AGCPSCTL_TM), config_AGCPSCTL_TM}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_1_indx), config_Power_Ctrl_1_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_1a_cmd), config_Power_Ctrl_1a_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_2_indx), config_Power_Ctrl_2_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_2a_cmd), config_Power_Ctrl_2a_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_indx), | |
+ config_Auto_Sequencer_Setting_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_a_cmd), | |
+ config_Auto_Sequencer_Setting_a_cmd }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(Driver_Output_Ctrl_indx), Driver_Output_Ctrl_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(Driver_Output_Ctrl_cmd), | |
+ Driver_Output_Ctrl_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_LCD_drive_AC_Ctrl_indx), | |
+ config_LCD_drive_AC_Ctrl_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_LCD_drive_AC_Ctrl_cmd), | |
+ config_LCD_drive_AC_Ctrl_cmd }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Entry_Mode_indx), | |
+ config_Entry_Mode_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Entry_Mode_cmd), | |
+ config_Entry_Mode_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_Ctrl_1_indx), | |
+ config_Display_Ctrl_1_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_Ctrl_1_cmd), | |
+ config_Display_Ctrl_1_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_Ctrl_2_indx), | |
+ config_Display_Ctrl_2_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_Ctrl_2_cmd), | |
+ config_Display_Ctrl_2_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_Ctrl_3_indx), | |
+ config_Display_Ctrl_3_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_Ctrl_3_cmd), | |
+ config_Display_Ctrl_3_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_IF_Ctrl_1_indx), | |
+ config_Display_IF_Ctrl_1_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_IF_Ctrl_1_cmd), | |
+ config_Display_IF_Ctrl_1_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_IF_Ctrl_2_indx), | |
+ config_Display_IF_Ctrl_2_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Display_IF_Ctrl_2_cmd), | |
+ config_Display_IF_Ctrl_2_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_1_indx), | |
+ config_Panel_IF_Ctrl_1_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_1_cmd), | |
+ config_Panel_IF_Ctrl_1_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_3_indx), | |
+ config_Panel_IF_Ctrl_3_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_3_cmd), | |
+ config_Panel_IF_Ctrl_3_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_4_indx), | |
+ config_Panel_IF_Ctrl_4_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_4_cmd), | |
+ config_Panel_IF_Ctrl_4_cmd }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_5_indx), | |
+ config_Panel_IF_Ctrl_5_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_5_cmd), | |
+ config_Panel_IF_Ctrl_5_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_6_indx), | |
+ config_Panel_IF_Ctrl_6_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_6_cmd), | |
+ config_Panel_IF_Ctrl_6_cmd }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_8_indx), | |
+ config_Panel_IF_Ctrl_8_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_8_cmd), | |
+ config_Panel_IF_Ctrl_8_cmd }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_9_indx), | |
+ config_Panel_IF_Ctrl_9_indx }, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_9_cmd), | |
+ config_Panel_IF_Ctrl_9_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_00_indx), | |
+ config_gam_adjust_00_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_00_cmd), | |
+ config_gam_adjust_00_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_01_indx), | |
+ config_gam_adjust_01_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_01_cmd), | |
+ config_gam_adjust_01_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_02_indx), | |
+ config_gam_adjust_02_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_02_cmd), | |
+ config_gam_adjust_02_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_03_indx), | |
+ config_gam_adjust_03_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_03_cmd), | |
+ config_gam_adjust_03_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_04_indx), config_gam_adjust_04_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_04_cmd), config_gam_adjust_04_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_05_indx), config_gam_adjust_05_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_05_cmd), config_gam_adjust_05_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_06_indx), config_gam_adjust_06_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_06_cmd), config_gam_adjust_06_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_07_indx), config_gam_adjust_07_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_07_cmd), config_gam_adjust_07_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_08_indx), config_gam_adjust_08_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_08_cmd), config_gam_adjust_08_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_09_indx), config_gam_adjust_09_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_09_cmd), config_gam_adjust_09_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_0A_indx), config_gam_adjust_0A_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_0A_cmd), config_gam_adjust_0A_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_0B_indx), config_gam_adjust_0B_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_0B_cmd), config_gam_adjust_0B_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_0C_indx), config_gam_adjust_0C_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_0C_cmd), config_gam_adjust_0C_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_0D_indx), config_gam_adjust_0D_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_0D_cmd), config_gam_adjust_0D_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_10_indx), config_gam_adjust_10_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_10_cmd), config_gam_adjust_10_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_11_indx), config_gam_adjust_11_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_11_cmd), config_gam_adjust_11_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_12_indx), config_gam_adjust_12_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_12_cmd), config_gam_adjust_12_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_15_indx), config_gam_adjust_15_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_15_cmd), config_gam_adjust_15_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_16_indx), config_gam_adjust_16_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_16_cmd), config_gam_adjust_16_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_17_indx), config_gam_adjust_17_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_17_cmd), config_gam_adjust_17_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_18_indx), config_gam_adjust_18_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_18_cmd), config_gam_adjust_18_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_19_indx), config_gam_adjust_19_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_19_cmd), config_gam_adjust_19_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_1C_indx), config_gam_adjust_1C_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_1C_cmd), config_gam_adjust_1C_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_1D_indx), config_gam_adjust_1D_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_1D_cmd), config_gam_adjust_1D_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_20_indx), config_gam_adjust_20_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_20_cmd), config_gam_adjust_20_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_21_indx), config_gam_adjust_21_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_21_cmd), config_gam_adjust_21_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_22_indx), config_gam_adjust_22_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_22_cmd), config_gam_adjust_22_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_27_indx), config_gam_adjust_27_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_27_cmd), config_gam_adjust_27_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_28_indx), config_gam_adjust_28_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_28_cmd), config_gam_adjust_28_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_29_indx), config_gam_adjust_29_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_gam_adjust_29_cmd), config_gam_adjust_29_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_1_indx), config_Power_Ctrl_1_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_1b_cmd), config_Power_Ctrl_1b_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_2_indx), config_Power_Ctrl_2_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_2b_cmd), config_Power_Ctrl_2b_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_3_indx), config_Power_Ctrl_3_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_3a_cmd), config_Power_Ctrl_3a_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_4_indx), config_Power_Ctrl_4_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_4a_cmd), config_Power_Ctrl_4a_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_6_indx), config_Power_Ctrl_6_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_6a_cmd), config_Power_Ctrl_6a_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_indx), | |
+ config_Auto_Sequencer_Setting_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_b_cmd), | |
+ config_Auto_Sequencer_Setting_b_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_10_indx), | |
+ config_Panel_IF_Ctrl_10_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Panel_IF_Ctrl_10a_cmd), | |
+ config_Panel_IF_Ctrl_10a_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_indx), | |
+ config_Auto_Sequencer_Setting_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Auto_Sequencer_Setting_c_cmd), | |
+ config_Auto_Sequencer_Setting_c_cmd}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD70), config_DBICADD70}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_2_indx), | |
+ config_Power_Ctrl_2_indx}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_DBICADD72), config_DBICADD72}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_Power_Ctrl_2c_cmd), | |
+ config_Power_Ctrl_2c_cmd}, | |
+ | |
+ {DTYPE_DCS_WRITE1, 1, 0, 0, 0/* RENESAS_CMD_DELAY */, | |
+ sizeof(config_DBICSET_15), config_DBICSET_15}, | |
}; | |
+static char config_WRTXHT2[7] = {0x92, 0x15, 0x05, 0x0F, 0x00, 0x01, 0xe0}; | |
+static char config_WRTXVT2[7] = {0x8b, 0x14, 0x01, 0x14, 0x00, 0x03, 0x60}; | |
+ | |
+static struct dsi_cmd_desc renesas_hvga_on_cmds[] = { | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_WRTXHT2), config_WRTXHT2}, | |
+ {DTYPE_DCS_LWRITE, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_WRTXVT2), config_WRTXVT2}, | |
+}; | |
+ | |
+static struct dsi_cmd_desc renesas_video_on_cmds[] = { | |
+{DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_VIDEO), config_VIDEO} | |
+}; | |
+ | |
+static struct dsi_cmd_desc renesas_cmd_on_cmds[] = { | |
+{DTYPE_DCS_WRITE1, 1, 0, 0, RENESAS_CMD_DELAY, | |
+ sizeof(config_CMD_MODE), config_CMD_MODE}, | |
+}; | |
+ | |
static int mipi_renesas_lcd_on(struct platform_device *pdev) | |
{ | |
struct msm_fb_data_type *mfd; | |
@@ -71,6 +1137,18 @@ static int mipi_renesas_lcd_on(struct platform_device *pdev) | |
mipi_set_tx_power_mode(1); | |
mipi_dsi_cmds_tx(&renesas_tx_buf, renesas_display_on_cmds, | |
ARRAY_SIZE(renesas_display_on_cmds)); | |
+ | |
+ if (cpu_is_msm7x25a() || cpu_is_msm7x25aa() || cpu_is_msm7x25ab()) { | |
+ mipi_dsi_cmds_tx(&renesas_tx_buf, renesas_hvga_on_cmds, | |
+ ARRAY_SIZE(renesas_hvga_on_cmds)); | |
+ } | |
+ | |
+ if (mipi->mode == DSI_VIDEO_MODE) | |
+ mipi_dsi_cmds_tx(&renesas_tx_buf, renesas_video_on_cmds, | |
+ ARRAY_SIZE(renesas_video_on_cmds)); | |
+ else | |
+ mipi_dsi_cmds_tx(&renesas_tx_buf, renesas_cmd_on_cmds, | |
+ ARRAY_SIZE(renesas_cmd_on_cmds)); | |
mipi_set_tx_power_mode(0); | |
return 0; | |
@@ -90,9 +1168,6 @@ static int mipi_renesas_lcd_off(struct platform_device *pdev) | |
mipi_dsi_cmds_tx(&renesas_tx_buf, renesas_display_off_cmds, | |
ARRAY_SIZE(renesas_display_off_cmds)); | |
- mipi_dsi_cmds_tx(mfd, &renesas_tx_buf, renesas_sleep_on_cmds, | |
- ARRAY_SIZE(renesas_sleep_on_cmds)); | |
- | |
return 0; | |
} | |
diff --git a/drivers/video/msm/mipi_renesas_video_sharp_ls043k3sx04_1a_pt.c b/drivers/video/msm/mipi_renesas_video_sharp_ls043k3sx04_1a_pt.c | |
deleted file mode 100644 | |
index ae15aee..0000000 | |
--- a/drivers/video/msm/mipi_renesas_video_sharp_ls043k3sx04_1a_pt.c | |
+++ /dev/null | |
@@ -1,100 +0,0 @@ | |
-/********************************************************************* | |
- * Copyright (C) 2012 Sony Mobile Communications AB. * | |
- * All rights, including trade secret rights, reserved. * | |
- *********************************************************************/ | |
- | |
- | |
-#include "msm_fb.h" | |
-#include "mipi_dsi.h" | |
-#include "mipi_renesas.h" | |
- | |
-static struct msm_panel_info pinfo; | |
- | |
-static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = { | |
- /* 720*1280, RGB888, 4 Lane 60 fps video mode */ | |
- /* regulator */ | |
- {0x03, 0x0a, 0x04, 0x00, 0x20}, | |
- /* timing */ | |
- {0x78, 0x1a, 0x11, 0x00, 0x3e, 0x43, 0x16, 0x1d, | |
- 0x1d, 0x03, 0x04, 0xa0}, | |
- /* phy ctrl */ | |
- {0x5f, 0x00, 0x00, 0x10}, | |
- /* strength */ | |
- {0xff, 0x00, 0x06, 0x00}, | |
- /* pll control */ | |
- {0x00, 0x8f, 0x01, 0x19, 0x00, 0x40, 0x03, 0x62, | |
- 0x41, 0x0f, 0x03, | |
- 0x00, 0x1a, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 }, | |
-}; | |
- | |
-static int __init mipi_video_renesas_sharp_sx04_1a_init(void) | |
-{ | |
- int ret; | |
- | |
- pr_err("%s: starting\n", __func__); | |
- | |
- if (msm_fb_detect_client("mipi_video_renesas_fwvga")) | |
- return 0; | |
- | |
- pr_err("%s: panel detected\n", __func__); | |
- | |
- pinfo.xres = 720; | |
- pinfo.yres = 1280; | |
- pinfo.type = MIPI_VIDEO_PANEL; | |
- pinfo.pdest = DISPLAY_1; | |
- pinfo.wait_cycle = 0; | |
- pinfo.bpp = 24; | |
- pinfo.lcdc.h_back_porch = 45; | |
- pinfo.lcdc.h_front_porch = 128; | |
- pinfo.lcdc.h_pulse_width = 3; | |
- pinfo.lcdc.v_back_porch = 4; | |
- pinfo.lcdc.v_front_porch = 5; | |
- pinfo.lcdc.v_pulse_width = 1; | |
- pinfo.lcdc.border_clr = 0; /* blk */ | |
- pinfo.lcdc.underflow_clr = 0; /* black */ | |
- pinfo.lcdc.hsync_skew = 0; | |
- pinfo.bl_max = 15; | |
- pinfo.bl_min = 1; | |
- pinfo.fb_num = 2; | |
- pinfo.clk_rate = 416000000; | |
- | |
- /* pinfo.mipi.xres_pad = 0; */ | |
- /* pinfo.mipi.yres_pad = 0; */ | |
- pinfo.mipi.mode = DSI_VIDEO_MODE; | |
- pinfo.mipi.pulse_mode_hsa_he = TRUE; | |
- pinfo.mipi.hfp_power_stop = FALSE; | |
- pinfo.mipi.hbp_power_stop = FALSE; | |
- pinfo.mipi.hsa_power_stop = FALSE; | |
- pinfo.mipi.eof_bllp_power_stop = TRUE; | |
- pinfo.mipi.bllp_power_stop = TRUE; | |
- /* pinfo.mipi.dlane_swap = 0x01; */ | |
- pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; | |
- pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; | |
- pinfo.mipi.vc = 0; | |
- pinfo.mipi.rgb_swap = DSI_RGB_SWAP_BGR; | |
- pinfo.mipi.r_sel = 0; | |
- pinfo.mipi.g_sel = 0; | |
- pinfo.mipi.b_sel = 0; | |
- pinfo.mipi.data_lane0 = TRUE; | |
- pinfo.mipi.data_lane1 = TRUE; | |
- pinfo.mipi.data_lane2 = TRUE; | |
- pinfo.mipi.data_lane3 = TRUE; | |
- pinfo.mipi.tx_eot_append = TRUE; | |
- pinfo.mipi.t_clk_post = 0x04; | |
- pinfo.mipi.t_clk_pre = 0x1B; | |
- pinfo.mipi.stream = 0; /* dma_p */ | |
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; | |
- pinfo.mipi.frame_rate = 60; | |
- pinfo.mipi.dsi_phy_db = &dsi_video_mode_phy_db; | |
- | |
- ret = mipi_renesas_device_register(&pinfo, MIPI_DSI_PRIM, | |
- MIPI_DSI_PANEL_FWVGA_PT); | |
- if (ret) | |
- pr_err("%s: failed to register device!\n", __func__); | |
- | |
- pr_err("%s: device registered\n", __func__); | |
- return ret; | |
-} | |
- | |
-module_init(mipi_video_renesas_sharp_sx04_1a_init); | |
diff --git a/drivers/video/msm/msm_dss_io_8960.c b/drivers/video/msm/msm_dss_io_8960.c | |
index 015703b..add4027 100644 | |
--- a/drivers/video/msm/msm_dss_io_8960.c | |
+++ b/drivers/video/msm/msm_dss_io_8960.c | |
@@ -704,16 +704,9 @@ void mipi_dsi_clk_enable(void) | |
if (clk_set_rate(dsi_byte_div_clk, 1) < 0) /* divided by 1 */ | |
pr_err("%s: dsi_byte_div_clk - " | |
"clk_set_rate failed\n", __func__); | |
- if(esc_byte_ratio) { | |
- if (clk_set_rate(dsi_esc_clk, esc_byte_ratio) < 0) /* divided by esc */ | |
- pr_err("%s: dsi_esc_clk - " /* clk ratio */ | |
- "clk_set_rate failed\n", __func__); | |
- } else { | |
- if (clk_set_rate(dsi_esc_clk, 2) < 0) /* divided by 2 */ | |
- pr_err("%s: dsi_esc_clk - " | |
- "clk_set_rate failed\n", __func__); | |
- } | |
- | |
+ if (clk_set_rate(dsi_esc_clk, esc_byte_ratio) < 0) /* divided by esc */ | |
+ pr_err("%s: dsi_esc_clk - " /* clk ratio */ | |
+ "clk_set_rate failed\n", __func__); | |
mipi_dsi_pclk_ctrl(&dsi_pclk, 1); | |
mipi_dsi_clk_ctrl(&dsicore_clk, 1); | |
clk_prepare_enable(dsi_byte_div_clk); | |
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c | |
index 49b5d5c..cc51b43 100644 | |
--- a/drivers/video/msm/msm_fb.c | |
+++ b/drivers/video/msm/msm_fb.c | |
@@ -4,8 +4,7 @@ | |
* Core MSM framebuffer driver. | |
* | |
* Copyright (C) 2007 Google Incorporated | |
- * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved. | |
- * Copyright (C) 2012-2013 Sony Mobile Communications AB. | |
+ * Copyright (c) 2008-2013, The Linux Foundation. All rights reserved. | |
* | |
* This software is licensed under the terms of the GNU General Public | |
* License version 2, as published by the Free Software Foundation, and | |
@@ -435,7 +434,6 @@ static int msm_fb_probe(struct platform_device *pdev) | |
#ifdef CONFIG_FB_MSM_OVERLAY | |
mfd->overlay_play_enable = 1; | |
#endif | |
- mfd->nvrw_prohibit_draw = false; | |
bf_supported = mdp4_overlay_borderfill_supported(); | |
@@ -574,28 +572,6 @@ static int msm_fb_suspend(struct platform_device *pdev, pm_message_t state) | |
#define msm_fb_suspend NULL | |
#endif | |
-static void msm_fb_shutdown(struct platform_device *pdev) | |
-{ | |
- struct msm_fb_data_type *mfd; | |
- int ret = 0; | |
- MSM_FB_DEBUG("msm_fb_shutdown\n"); | |
- | |
- mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev); | |
- if (mfd) { | |
- if (mfd->op_enable) { | |
- ret = msm_fb_blank_sub(FB_BLANK_POWERDOWN, mfd->fbi, | |
- mfd->op_enable); | |
- } | |
- | |
- if (ret) | |
- MSM_FB_INFO | |
- ("msm_fb_shutdown: can't turn off display!\n"); | |
- | |
- mfd->op_enable = FALSE; | |
- mdp_pipe_ctrl(MDP_MASTER_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); | |
- } | |
-} | |
- | |
static int msm_fb_suspend_sub(struct msm_fb_data_type *mfd) | |
{ | |
int ret = 0; | |
@@ -825,7 +801,7 @@ static struct platform_driver msm_fb_driver = { | |
.suspend = msm_fb_suspend, | |
.resume = msm_fb_resume, | |
#endif | |
- .shutdown = msm_fb_shutdown, | |
+ .shutdown = NULL, | |
.driver = { | |
/* Driver name must match the device name added in platform.c. */ | |
.name = "msm_fb", | |
@@ -978,7 +954,6 @@ static int msm_fb_blank_sub(int blank_mode, struct fb_info *info, | |
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par; | |
struct msm_fb_panel_data *pdata = NULL; | |
int ret = 0; | |
- struct fb_event event; | |
if (!op_enable) | |
return -EPERM; | |
@@ -989,37 +964,14 @@ static int msm_fb_blank_sub(int blank_mode, struct fb_info *info, | |
return -ENODEV; | |
} | |
- event.info = info; | |
- event.data = &blank_mode; | |
- | |
switch (blank_mode) { | |
case FB_BLANK_UNBLANK: | |
if (!mfd->panel_power_on) { | |
- if (pdata->controller_on_panel_on) | |
- pdata->power_on_panel_at_pan = 1; | |
-#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_FB_MSM_RECOVER_PANEL) | |
- mutex_lock(&mfd->power_lock); | |
-#endif | |
ret = pdata->on(mfd->pdev); | |
if (ret == 0) { | |
mfd->panel_power_on = TRUE; | |
mfd->panel_driver_on = mfd->op_enable; | |
} | |
-#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_FB_MSM_RECOVER_PANEL) | |
- mutex_unlock(&mfd->power_lock); | |
-#endif | |
-/* ToDo: possible conflict with android which doesn't expect sw refresher */ | |
-/* | |
- if (!mfd->hw_refresh) | |
- { | |
- if ((ret = msm_fb_resume_sw_refresher(mfd)) != 0) | |
- { | |
- MSM_FB_INFO("msm_fb_blank_sub: msm_fb_resume_sw_refresher failed = %d!\n",ret); | |
- } | |
- } | |
-*/ | |
- if ((ret == 0) && (mfd->index == 0)) | |
- fb_notifier_call_chain(FB_EVENT_BLANK, &event); | |
} | |
break; | |
@@ -1031,12 +983,6 @@ static int msm_fb_blank_sub(int blank_mode, struct fb_info *info, | |
if (mfd->panel_power_on) { | |
int curr_pwr_state; | |
- if (mfd->index == 0) | |
- fb_notifier_call_chain(FB_EVENT_BLANK, &event); | |
- | |
-#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_FB_MSM_RECOVER_PANEL) | |
- mutex_lock(&mfd->power_lock); | |
-#endif | |
mfd->op_enable = FALSE; | |
curr_pwr_state = mfd->panel_power_on; | |
mfd->panel_power_on = FALSE; | |
@@ -1055,9 +1001,6 @@ static int msm_fb_blank_sub(int blank_mode, struct fb_info *info, | |
ret = pdata->off(mfd->pdev); | |
if (ret) | |
mfd->panel_power_on = curr_pwr_state; | |
-#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_FB_MSM_RECOVER_PANEL) | |
- mutex_unlock(&mfd->power_lock); | |
-#endif | |
msm_fb_release_timeline(mfd); | |
mfd->op_enable = TRUE; | |
@@ -1320,20 +1263,9 @@ static int msm_fb_register(struct msm_fb_data_type *mfd) | |
var->yoffset = 0, /* resolution */ | |
var->grayscale = 0, /* No graylevels */ | |
var->nonstd = 0, /* standard pixel format */ | |
- var->activate = FB_ACTIVATE_VBL; /* activate it at vsync */ | |
- | |
- /* height of picture in mm */ | |
- if (panel_info && panel_info->height) | |
- var->height = panel_info->height; | |
- else | |
- var->height = -1; | |
- | |
- /* width of picture in mm */ | |
- if (panel_info && panel_info->width) | |
- var->width = panel_info->width; | |
- else | |
- var->width = -1; | |
- | |
+ var->activate = FB_ACTIVATE_VBL, /* activate it at vsync */ | |
+ var->height = -1, /* height of picture in mm */ | |
+ var->width = -1, /* width of picture in mm */ | |
var->accel_flags = 0, /* acceleration flags */ | |
var->sync = 0, /* see FB_SYNC_* */ | |
var->rotate = 0, /* angle we rotate counter clockwise */ | |
@@ -1668,10 +1600,14 @@ static int msm_fb_register(struct msm_fb_data_type *mfd) | |
} | |
MSM_FB_INFO | |
- ("FrameBuffer[%d] %dx%dx%d size=%d bytes is registered successfully!\n", | |
- mfd->index, fbi->var.xres, fbi->var.yres, fbi->var.bits_per_pixel, | |
- fbi->fix.smem_len); | |
+ ("FrameBuffer[%d] %dx%d size=%d bytes is registered successfully!\n", | |
+ mfd->index, fbi->var.xres, fbi->var.yres, fbi->fix.smem_len); | |
+#ifdef CONFIG_FB_MSM_LOGO | |
+ /* Flip buffer */ | |
+ if (!load_565rle_image(INIT_IMAGE_FILE, bf_supported)) | |
+ ; | |
+#endif | |
ret = 0; | |
#ifdef CONFIG_HAS_EARLYSUSPEND | |
@@ -1815,24 +1751,6 @@ static int msm_fb_register(struct msm_fb_data_type *mfd) | |
return ret; | |
} | |
-static void msm_fb_client_counter(struct fb_info *info, int user, bool open) | |
-{ | |
- static int cnt; | |
- int idx; | |
- | |
- if (user != 1) | |
- return; | |
- | |
- if (open) | |
- cnt++; | |
- else | |
- cnt--; | |
- | |
- if (!cnt) | |
- for (idx = 2; idx <= 4; idx++) | |
- mdp4_overlay_unset(info, idx); | |
-} | |
- | |
static int msm_fb_open(struct fb_info *info, int user) | |
{ | |
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par; | |
@@ -1846,7 +1764,6 @@ static int msm_fb_open(struct fb_info *info, int user) | |
} | |
if (info->node == 0 && !(mfd->cont_splash_done)) { /* primary */ | |
- msm_fb_client_counter(info, user, true); | |
mfd->ref_cnt++; | |
return 0; | |
} | |
@@ -1857,7 +1774,7 @@ static int msm_fb_open(struct fb_info *info, int user) | |
return 0; | |
} | |
- if (!mfd->ref_cnt && info->node != 1) { | |
+ if (!mfd->ref_cnt) { | |
if (!bf_supported || | |
(info->node != 1 && info->node != 2)) | |
mdp_set_dma_pan_info(info, NULL, TRUE); | |
@@ -1876,7 +1793,6 @@ static int msm_fb_open(struct fb_info *info, int user) | |
} | |
} | |
- msm_fb_client_counter(info, user, true); | |
mfd->ref_cnt++; | |
return 0; | |
} | |
@@ -1892,8 +1808,6 @@ static int msm_fb_release(struct fb_info *info, int user) | |
return -EINVAL; | |
} | |
msm_fb_pan_idle(mfd); | |
- | |
- msm_fb_client_counter(info, user, false); | |
mfd->ref_cnt--; | |
if ((!mfd->ref_cnt) && (mfd->op_enable)) { | |
@@ -2069,11 +1983,8 @@ static int msm_fb_pan_display_sub(struct fb_var_screeninfo *var, | |
struct mdp_dirty_region dirty; | |
struct mdp_dirty_region *dirtyPtr = NULL; | |
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par; | |
- struct msm_fb_panel_data *pdata = | |
- (struct msm_fb_panel_data *)mfd->pdev->dev.platform_data; | |
+ struct msm_fb_panel_data *pdata; | |
- if (mfd->nvrw_prohibit_draw) | |
- return 0; | |
/* | |
* If framebuffer is 2, io pen display is not allowed. | |
*/ | |
@@ -2192,7 +2103,6 @@ static void msm_fb_commit_wq_handler(struct work_struct *work) | |
struct fb_var_screeninfo *var; | |
struct fb_info *info; | |
struct msm_fb_backup_type *fb_backup; | |
- struct msm_fb_panel_data *pdata; | |
mfd = container_of(work, struct msm_fb_data_type, commit_work); | |
fb_backup = (struct msm_fb_backup_type *)mfd->msm_fb_backup; | |
@@ -2209,11 +2119,6 @@ static void msm_fb_commit_wq_handler(struct work_struct *work) | |
complete_all(&mfd->commit_comp); | |
mutex_unlock(&mfd->sync_mutex); | |
- pdata = mfd->pdev->dev.platform_data; | |
- if (pdata->power_on_panel_at_pan && pdata->on) { | |
- (void)pdata->controller_on_panel_on(mfd->pdev); | |
- pdata->power_on_panel_at_pan = 0; | |
- } | |
} | |
static int msm_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
@@ -3281,12 +3186,8 @@ static int msmfb_overlay_get(struct fb_info *info, void __user *p) | |
static int msmfb_overlay_set(struct fb_info *info, void __user *p) | |
{ | |
struct mdp_overlay req; | |
- struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par; | |
int ret; | |
- if (mfd->nvrw_prohibit_draw) | |
- return -EFAULT; | |
- | |
if (copy_from_user(&req, p, sizeof(req))) | |
return -EFAULT; | |
@@ -3365,8 +3266,6 @@ static int msmfb_overlay_play(struct fb_info *info, unsigned long *argp) | |
if (mfd->overlay_play_enable == 0) /* nothing to do */ | |
return 0; | |
- if (mfd->nvrw_prohibit_draw) | |
- return 0; | |
ret = copy_from_user(&req, argp, sizeof(req)); | |
if (ret) { | |
@@ -4385,12 +4284,6 @@ struct platform_device *msm_fb_add_device(struct platform_device *pdev) | |
/* link to the latest pdev */ | |
mfd->pdev = this_dev; | |
- /* link to the panel pdev */ | |
- mfd->panel_pdev = pdev; | |
-#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_FB_MSM_RECOVER_PANEL) | |
- mutex_init(&mfd->power_lock); | |
-#endif | |
- | |
mfd_list[mfd_list_index++] = mfd; | |
fbi_list[fbi_list_index++] = fbi; | |
diff --git a/drivers/video/msm/msm_fb.h b/drivers/video/msm/msm_fb.h | |
index c0ef2a3..4b6f41f 100644 | |
--- a/drivers/video/msm/msm_fb.h | |
+++ b/drivers/video/msm/msm_fb.h | |
@@ -1,5 +1,4 @@ | |
/* Copyright (c) 2008-2013, The Linux Foundation. All rights reserved. | |
- * Copyright (C) 2012-2013 Sony Mobile Communications AB. | |
* | |
* This program is free software; you can redistribute it and/or modify | |
* it under the terms of the GNU General Public License version 2 and | |
@@ -154,7 +153,6 @@ struct msm_fb_data_type { | |
__u32 bl_level; | |
struct platform_device *pdev; | |
- struct platform_device *panel_pdev; | |
__u32 var_xres; | |
__u32 var_yres; | |
@@ -219,10 +217,6 @@ struct msm_fb_data_type { | |
unsigned char *copy_splash_phys; | |
uint32 sec_mapped; | |
uint32 sec_active; | |
-#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_FB_MSM_RECOVER_PANEL) | |
- struct mutex power_lock; | |
-#endif | |
- bool nvrw_prohibit_draw; | |
}; | |
struct msm_fb_backup_type { | |
struct fb_info info; | |
@@ -257,4 +251,9 @@ void fill_black_screen(bool on, uint8 pipe_num, uint8 mixer_num); | |
int msm_fb_check_frame_rate(struct msm_fb_data_type *mfd, | |
struct fb_info *info); | |
+#ifdef CONFIG_FB_MSM_LOGO | |
+#define INIT_IMAGE_FILE "/initlogo.rle" | |
+int load_565rle_image(char *filename, bool bf_supported); | |
+#endif | |
+ | |
#endif /* MSM_FB_H */ | |
diff --git a/drivers/video/msm/msm_fb_panel.h b/drivers/video/msm/msm_fb_panel.h | |
index 7f812eb..c6e5d63 100644 | |
--- a/drivers/video/msm/msm_fb_panel.h | |
+++ b/drivers/video/msm/msm_fb_panel.h | |
@@ -1,5 +1,4 @@ | |
/* Copyright (c) 2008-2013, The Linux Foundation. All rights reserved. | |
- * Copyright (C) 2012 Sony Mobile Communications AB. | |
* | |
* This program is free software; you can redistribute it and/or modify | |
* it under the terms of the GNU General Public License version 2 and | |
@@ -172,10 +171,6 @@ struct msm_panel_info { | |
__u32 frame_rate; | |
__u32 frame_interval; | |
- /* physical size in mm */ | |
- __u32 width; | |
- __u32 height; | |
- | |
struct mddi_panel_info mddi; | |
struct lcd_panel_info lcd; | |
struct lcdc_panel_info lcdc; | |
@@ -199,9 +194,7 @@ struct msm_fb_panel_data { | |
/* function entry chain */ | |
int (*on) (struct platform_device *pdev); | |
- int (*controller_on_panel_on) (struct platform_device *pdev); | |
int (*off) (struct platform_device *pdev); | |
- int power_on_panel_at_pan; | |
int (*late_init) (struct platform_device *pdev); | |
int (*early_off) (struct platform_device *pdev); | |
int (*power_ctrl) (boolean enable); | |
@@ -209,9 +202,6 @@ struct msm_fb_panel_data { | |
int (*clk_func) (int enable); | |
int (*fps_level_change) (struct platform_device *pdev, | |
u32 fps_level); | |
- struct msm_panel_info *(*panel_detect) (struct msm_fb_data_type *mfd); | |
- int (*update_panel) (struct platform_device *pdev); | |
- int (*get_pcc_data) (struct msm_fb_data_type *mfd); | |
}; | |
/*=========================================================================== | |
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c | |
index 4a9dec4..957bb8f 100644 | |
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c | |
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c | |
@@ -1,5 +1,4 @@ | |
/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. | |
- * Copyright (C) 2012 Sony Mobile Communications AB | |
* | |
* This program is free software; you can redistribute it and/or modify | |
* it under the terms of the GNU General Public License version 2 and | |
@@ -587,6 +586,10 @@ void ddl_vidc_encode_init_codec(struct ddl_client_context *ddl) | |
scaled_frame_rate = DDL_FRAMERATE_SCALE(encoder->\ | |
frame_rate.fps_numerator) / | |
encoder->frame_rate.fps_denominator; | |
+ if ((encoder->codec.codec == VCD_CODEC_H263) && | |
+ (DDL_FRAMERATE_SCALE(DDL_INITIAL_FRAME_RATE) | |
+ != scaled_frame_rate)) | |
+ h263_cpfc_enable = true; | |
vidc_sm_set_extended_encoder_control(&ddl->shared_mem | |
[ddl->command_channel], hdr_ext_control, | |
r_cframe_skip, false, 0, |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment