How Kernel's Makefile Specify Output Directory

Makefile

ifeq ($(KBUILD_SRC),)
ifeq ("$(origin O)", "command line")
	KBUILD_OUTPUT := $(O)
endif

ifneq ($(KBUILD_OUTPUT),)
$(filter-out submake $(CURDIR)/Makefile, $(MAKECMDGOALS)): sub-make
	@:

sub-make:
	make -C $(KBUILD_OUTPUT) -f /home/wangbin/maketest/Makefile \
		KBUILD_SRC=$(PWD) \
		$(MAKECMDGOALS)
	@echo " sub-make KBUILD_OUTPUT: $(KBUILD_OUTPUT)"
skip-makefile := 1
endif #end KBUILD_OUTPUT
endif #end KBUILD_SRC

ifeq ($(skip-makefile),)

target1:
	touch target1
	@echo "target KBUILD_OUTPUT: $(KBUILD_OUTPUT)"

target2:
	touch target2
	@echo "target KBUILD_OUTPUT: $(KBUILD_OUTPUT)"
endif