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wgaylord/Test1

Created April 11, 2020 04:47
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Test1
set APIO_HOME_DIR=C:\Users\chibi\.icestudio\apio& "C:\Users\chibi\.icestudio\venv\Scripts\apio.exe" upload --board upduino21 --verbose-pnr -p "C:\Users\chibi\AppData\Local\Temp\icestudio-12152c8lkqPqY7Fp1"
[Fri Apr 10 23:44:37 2020] Processing upduino21
--------------------------------------------------------------------------------
yosys -p "synth_ice40 -json hardware.json" -q main.v
nextpnr-ice40 --up5k --package sg48 --json hardware.json --asc hardware.asc --pcf main.pcf
Info: Importing module main
Info: Rule checker, verifying imported design
Info: Checksum: 0x5d722337
Info: constrained 'v0ab266' to bel 'X4/Y31/io0'
Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info: 0 LCs used as LUT4 only
Info: 0 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info: 0 LCs used as DFF only
Info: Packing carries..
Info: 0 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info: Packing special functions..
Info: Promoting globals..
Info: Constraining chains...
Info: 0 LCs used to legalise carry chains.
Info: Checksum: 0xed885afc
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x3ad4727f
Info: Device utilisation:
Info: ICESTORM_LC: 1/ 5280 0%
Info: ICESTORM_RAM: 0/ 30 0%
Info: SB_IO: 1/ 96 1%
Info: SB_GB: 0/ 8 0%
Info: ICESTORM_PLL: 0/ 1 0%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 0/ 4 0%
Info: Placed 1 cells based on constraints.
Info: Creating initial analytic placement for 1 cells, random placement wirelen = 22.
Info: at initial placer iter 0, wirelen = 0
Info: at initial placer iter 1, wirelen = 0
Info: at initial placer iter 2, wirelen = 0
Info: at initial placer iter 3, wirelen = 0
Info: Running main analytical placer.
Info: at iteration #1, type ICESTORM_LC: wirelen solved = 0, spread = 0, legal = 1; time = 0.00s
Info: at iteration #2, type ICESTORM_LC: wirelen solved = 1, spread = 1, legal = 1; time = 0.00s
Info: HeAP Placer Time: 0.00s
Info: of which solving equations: 0.00s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 0, wirelen = 1
Info: at iteration #2: temp = 0.000000, timing cost = 0, wirelen = 1
Info: SA placement time 0.00s
Warning: No clocks found in design
Info: Checksum: 0x7aa287ab
Info: Routing..
Info: Setting up routing queue.
Info: Routing 1 arcs.
Info: | (re-)routed arcs | delta | remaining
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs
Info: 1 | 0 1 | 0 1 | 0
Info: Routing complete.
Info: Route time 0.00s
Info: Checksum: 0x6bb19e05
Warning: No clocks found in design
2 warnings, 0 errors
icepack hardware.asc hardware.bin
iceprog -d i:0x0403:0x6014:0 hardware.bin
init..
cdone: high
reset..
cdone: high
flash ID: 0xEF 0x40 0x16 0x00
file size: 104090
erase 64kB sector at 0x000000..
erase 64kB sector at 0x010000..
programming..
reading..
VERIFY OK
cdone: high
Bye.
========================= [SUCCESS] Took 6.90 seconds =========================
Raw
Test2
set APIO_HOME_DIR=C:\Users\chibi\.icestudio\apio& "C:\Users\chibi\.icestudio\venv\Scripts\apio.exe" upload --board upduino21 --verbose-pnr -p "C:\Users\chibi\AppData\Local\Temp\icestudio-12636Vko4oARuH4Iu"
[Fri Apr 10 23:46:00 2020] Processing upduino21
--------------------------------------------------------------------------------
yosys -p "synth_ice40 -json hardware.json" -q main.v
nextpnr-ice40 --up5k --package sg48 --json hardware.json --asc hardware.asc --pcf main.pcf
Info: Importing module main
Info: Rule checker, verifying imported design
Info: Checksum: 0xbc2182f0
Info: constrained 'v0ab266' to bel 'X4/Y31/io0'
Info: constrained 'v1eeb01' to bel 'X15/Y0/io0'
Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info: 0 LCs used as LUT4 only
Info: 0 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info: 0 LCs used as DFF only
Info: Packing carries..
Info: 0 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info: Packing special functions..
Info: Promoting globals..
Info: Constraining chains...
Info: 0 LCs used to legalise carry chains.
Info: Checksum: 0x82144303
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x0fa770d8
Info: Device utilisation:
Info: ICESTORM_LC: 1/ 5280 0%
Info: ICESTORM_RAM: 0/ 30 0%
Info: SB_IO: 2/ 96 2%
Info: SB_GB: 0/ 8 0%
Info: ICESTORM_PLL: 0/ 1 0%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 0/ 4 0%
Info: Placed 2 cells based on constraints.
Info: Creating initial analytic placement for 0 cells, random placement wirelen = 42.
Info: at initial placer iter 0, wirelen = 42
Info: at initial placer iter 1, wirelen = 42
Info: at initial placer iter 2, wirelen = 42
Info: at initial placer iter 3, wirelen = 42
Info: Running main analytical placer.
Info: HeAP Placer Time: 0.03s
Info: of which solving equations: 0.00s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 0, wirelen = 42
Info: at iteration #2: temp = 0.000000, timing cost = 0, wirelen = 42
Info: SA placement time 0.00s
Warning: No clocks found in design
Info: Max delay <async> -> <async>: 7.87 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 75463, 75464) |*
Info: [ 75464, 75465) |
Info: [ 75465, 75466) |
Info: [ 75466, 75467) |
Info: [ 75467, 75468) |
Info: [ 75468, 75469) |
Info: [ 75469, 75470) |
Info: [ 75470, 75471) |
Info: [ 75471, 75472) |
Info: [ 75472, 75473) |
Info: [ 75473, 75474) |
Info: [ 75474, 75475) |
Info: [ 75475, 75476) |
Info: [ 75476, 75477) |
Info: [ 75477, 75478) |
Info: [ 75478, 75479) |
Info: [ 75479, 75480) |
Info: [ 75480, 75481) |
Info: [ 75481, 75482) |
Info: [ 75482, 75483) |
Info: Checksum: 0x4441e144
Info: Routing..
Info: Setting up routing queue.
Info: Routing 1 arcs.
Info: | (re-)routed arcs | delta | remaining
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs
Info: 1 | 0 1 | 0 1 | 0
Info: Routing complete.
Info: Route time 0.02s
Info: Checksum: 0x4ace1f7c
Warning: No clocks found in design
Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: curr total
Info: 0.0 0.0 Source v1eeb01$sb_io.D_IN_0
Info: 8.2 8.2 Net v1eeb01$SB_IO_IN budget 83.333000 ns (15,0) -> (4,31)
Info: Sink v0ab266$sb_io.D_OUT_0
Info: 0.0 ns logic, 8.2 ns routing
Info: Max delay <async> -> <async>: 8.18 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 75153, 75154) |*
Info: [ 75154, 75155) |
Info: [ 75155, 75156) |
Info: [ 75156, 75157) |
Info: [ 75157, 75158) |
Info: [ 75158, 75159) |
Info: [ 75159, 75160) |
Info: [ 75160, 75161) |
Info: [ 75161, 75162) |
Info: [ 75162, 75163) |
Info: [ 75163, 75164) |
Info: [ 75164, 75165) |
Info: [ 75165, 75166) |
Info: [ 75166, 75167) |
Info: [ 75167, 75168) |
Info: [ 75168, 75169) |
Info: [ 75169, 75170) |
Info: [ 75170, 75171) |
Info: [ 75171, 75172) |
Info: [ 75172, 75173) |
2 warnings, 0 errors
icepack hardware.asc hardware.bin
iceprog -d i:0x0403:0x6014:0 hardware.bin
init..
cdone: high
reset..
cdone: high
flash ID: 0xEF 0x40 0x16 0x00
file size: 104090
erase 64kB sector at 0x000000..
erase 64kB sector at 0x010000..
programming..
reading..
VERIFY OK
cdone: high
Bye.
========================= [SUCCESS] Took 7.74 seconds =========================
Raw
Test3
set APIO_HOME_DIR=C:\Users\chibi\.icestudio\apio& "C:\Users\chibi\.icestudio\venv\Scripts\apio.exe" upload --board upduino21 --verbose-pnr -p "C:\Users\chibi\AppData\Local\Temp\icestudio-12636Vko4oARuH4Iu"
[Fri Apr 10 23:46:43 2020] Processing upduino21
--------------------------------------------------------------------------------
yosys -p "synth_ice40 -json hardware.json" -q main.v
nextpnr-ice40 --up5k --package sg48 --json hardware.json --asc hardware.asc --pcf main.pcf
Info: Importing module main
Info: Rule checker, verifying imported design
Info: Checksum: 0x37b394ca
Info: constrained 'v0ab266' to bel 'X4/Y31/io0'
Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info: 8 LCs used as LUT4 only
Info: 25 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info: 1 LCs used as DFF only
Info: Packing carries..
Info: 1 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info: Packing special functions..
Info: constrained ICESTORM_HFOSC 'v0e6814.u_SB_HFOSC_OSC' to X0/Y31/hfosc_1
Info: Promoting globals..
Info: promoting v6a5296.v94c6d7.clk_t_SB_DFF_Q_D [reset] (fanout 24)
Info: Constraining chains...
Info: 1 LCs used to legalise carry chains.
Info: Checksum: 0x158a30cb
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x1ffff2d8
Info: Device utilisation:
Info: ICESTORM_LC: 38/ 5280 0%
Info: ICESTORM_RAM: 0/ 30 0%
Info: SB_IO: 1/ 96 1%
Info: SB_GB: 2/ 8 25%
Info: ICESTORM_PLL: 0/ 1 0%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 1/ 1 100%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 0/ 4 0%
Info: Placed 3 cells based on constraints.
Info: Creating initial analytic placement for 15 cells, random placement wirelen = 595.
Info: at initial placer iter 0, wirelen = 0
Info: at initial placer iter 1, wirelen = 0
Info: at initial placer iter 2, wirelen = 0
Info: at initial placer iter 3, wirelen = 0
Info: Running main analytical placer.
Info: at iteration #1, type ICESTORM_LC: wirelen solved = 0, spread = 34, legal = 78; time = 0.00s
Info: at iteration #1, type SB_GB: wirelen solved = 74, spread = 74, legal = 93; time = 0.00s
Info: at iteration #1, type ALL: wirelen solved = 0, spread = 34, legal = 97; time = 0.00s
Info: at iteration #2, type ICESTORM_LC: wirelen solved = 35, spread = 103, legal = 123; time = 0.00s
Info: at iteration #2, type SB_GB: wirelen solved = 120, spread = 120, legal = 123; time = 0.00s
Info: at iteration #2, type ALL: wirelen solved = 30, spread = 85, legal = 77; time = 0.00s
Info: at iteration #3, type ICESTORM_LC: wirelen solved = 47, spread = 69, legal = 122; time = 0.00s
Info: at iteration #3, type SB_GB: wirelen solved = 111, spread = 111, legal = 122; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 30, spread = 76, legal = 94; time = 0.00s
Info: at iteration #4, type ICESTORM_LC: wirelen solved = 35, spread = 76, legal = 96; time = 0.00s
Info: at iteration #4, type SB_GB: wirelen solved = 81, spread = 81, legal = 96; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 30, spread = 76, legal = 121; time = 0.00s
Info: at iteration #5, type ICESTORM_LC: wirelen solved = 68, spread = 89, legal = 111; time = 0.00s
Info: at iteration #5, type SB_GB: wirelen solved = 80, spread = 80, legal = 101; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 31, spread = 77, legal = 75; time = 0.00s
Info: at iteration #6, type ICESTORM_LC: wirelen solved = 38, spread = 76, legal = 88; time = 0.00s
Info: at iteration #6, type SB_GB: wirelen solved = 73, spread = 73, legal = 88; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 30, spread = 76, legal = 72; time = 0.00s
Info: at iteration #7, type ICESTORM_LC: wirelen solved = 52, spread = 99, legal = 75; time = 0.00s
Info: at iteration #7, type SB_GB: wirelen solved = 60, spread = 60, legal = 75; time = 0.00s
Info: at iteration #7, type ALL: wirelen solved = 30, spread = 76, legal = 71; time = 0.00s
Info: at iteration #8, type ICESTORM_LC: wirelen solved = 49, spread = 99, legal = 98; time = 0.00s
Info: at iteration #8, type SB_GB: wirelen solved = 83, spread = 83, legal = 98; time = 0.00s
Info: at iteration #8, type ALL: wirelen solved = 30, spread = 76, legal = 115; time = 0.00s
Info: at iteration #9, type ICESTORM_LC: wirelen solved = 50, spread = 96, legal = 75; time = 0.00s
Info: at iteration #9, type SB_GB: wirelen solved = 60, spread = 60, legal = 75; time = 0.00s
Info: at iteration #9, type ALL: wirelen solved = 30, spread = 76, legal = 75; time = 0.00s
Info: at iteration #10, type ICESTORM_LC: wirelen solved = 50, spread = 91, legal = 75; time = 0.00s
Info: at iteration #10, type SB_GB: wirelen solved = 60, spread = 60, legal = 75; time = 0.00s
Info: at iteration #10, type ALL: wirelen solved = 31, spread = 77, legal = 73; time = 0.00s
Info: at iteration #11, type ICESTORM_LC: wirelen solved = 51, spread = 91, legal = 72; time = 0.00s
Info: at iteration #11, type SB_GB: wirelen solved = 57, spread = 57, legal = 72; time = 0.00s
Info: at iteration #11, type ALL: wirelen solved = 31, spread = 77, legal = 72; time = 0.00s
Info: at iteration #12, type ICESTORM_LC: wirelen solved = 55, spread = 91, legal = 99; time = 0.00s
Info: at iteration #12, type SB_GB: wirelen solved = 83, spread = 83, legal = 99; time = 0.00s
Info: at iteration #12, type ALL: wirelen solved = 31, spread = 77, legal = 112; time = 0.00s
Info: HeAP Placer Time: 0.03s
Info: of which solving equations: 0.02s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 49, wirelen = 71
Info: at iteration #5: temp = 0.000000, timing cost = 46, wirelen = 59
Info: at iteration #9: temp = 0.000000, timing cost = 46, wirelen = 58
Info: SA placement time 0.01s
Info: Max frequency for clock 'w1': 46.71 MHz (PASS at 12.00 MHz)
Info: Max delay posedge w1 -> <async>: 3.15 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 61923, 62836) |************************
Info: [ 62836, 63749) |
Info: [ 63749, 64662) |
Info: [ 64662, 65575) |
Info: [ 65575, 66488) |
Info: [ 66488, 67401) |
Info: [ 67401, 68314) |
Info: [ 68314, 69227) |
Info: [ 69227, 70140) |
Info: [ 70140, 71053) |*
Info: [ 71053, 71966) |***
Info: [ 71966, 72879) |***
Info: [ 72879, 73792) |**
Info: [ 73792, 74705) |***
Info: [ 74705, 75618) |*****
Info: [ 75618, 76531) |*
Info: [ 76531, 77444) |***
Info: [ 77444, 78357) |**
Info: [ 78357, 79270) |***********************
Info: [ 79270, 80183) |*****
Info: Checksum: 0x15f1e469
Info: Routing..
Info: Setting up routing queue.
Info: Routing 119 arcs.
Info: | (re-)routed arcs | delta | remaining
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs
Info: 124 | 5 119 | 5 119 | 0
Info: Routing complete.
Info: Route time 0.02s
Info: Checksum: 0xe010c342
Info: Critical path report for clock 'w1' (posedge -> posedge):
Info: curr total
Info: 1.4 1.4 Source v6a5296.v94c6d7.divcounter_SB_DFFSR_Q_D_SB_LUT4_O_6_LC.O
Info: 1.8 3.2 Net v6a5296.v94c6d7.divcounter[16] budget 13.839000 ns (3,30) -> (4,29)
Info: Sink v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_O_LC.I0
Info: 1.3 4.4 Source v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_O_LC.O
Info: 1.8 6.2 Net v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0 budget 12.820000 ns (4,29) -> (4,29)
Info: Sink v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_O_LC.I0
Info: 1.3 7.5 Source v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_O_LC.O
Info: 1.8 9.2 Net v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_SB_LUT4_O_I3 budget 12.820000 ns (4,29) -> (4,29)
Info: Sink v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_SB_LUT4_O_LC.I3
Info: 0.9 10.1 Source v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_SB_LUT4_O_LC.O
Info: 3.9 14.0 Net v6a5296.v94c6d7.clk_t_SB_DFF_Q_D budget 15.362000 ns (4,29) -> (19,31)
Info: Sink $gbuf_v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_$glb_sr.USER_SIGNAL_TO_GLOBAL_BUFFER
Info: 1.6 15.6 Source $gbuf_v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_$glb_sr.GLOBAL_BUFFER_OUTPUT
Info: 0.6 16.3 Net v6a5296.v94c6d7.clk_t_SB_DFF_Q_D_$glb_sr budget 15.362000 ns (19,31) -> (3,30)
Info: Sink v6a5296.v94c6d7.divcounter_SB_DFFSR_Q_D_SB_LUT4_O_21_LC.SR
Info: 0.1 16.4 Setup v6a5296.v94c6d7.divcounter_SB_DFFSR_Q_D_SB_LUT4_O_21_LC.SR
Info: 6.5 ns logic, 9.8 ns routing
Info: Critical path report for cross-domain path 'posedge w1' -> '<async>':
Info: curr total
Info: 1.4 1.4 Source v6a5296.v94c6d7.clk_o_SB_LUT4_I3_LC.O
Info: 1.8 3.2 Net v0ab266$SB_IO_OUT budget 81.943001 ns (4,30) -> (4,31)
Info: Sink v0ab266$sb_io.D_OUT_0
Info: 1.4 ns logic, 1.8 ns routing
Info: Max frequency for clock 'w1': 61.13 MHz (PASS at 12.00 MHz)
Info: Max delay posedge w1 -> <async>: 3.15 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 66975, 67636) |************************
Info: [ 67636, 68297) |
Info: [ 68297, 68958) |
Info: [ 68958, 69619) |
Info: [ 69619, 70280) |*
Info: [ 70280, 70941) |*
Info: [ 70941, 71602) |**
Info: [ 71602, 72263) |***
Info: [ 72263, 72924) |**
Info: [ 72924, 73585) |*
Info: [ 73585, 74246) |**
Info: [ 74246, 74907) |**
Info: [ 74907, 75568) |***
Info: [ 75568, 76229) |
Info: [ 76229, 76890) |**
Info: [ 76890, 77551) |***
Info: [ 77551, 78212) |*
Info: [ 78212, 78873) |*
Info: [ 78873, 79534) |**************************
Info: [ 79534, 80195) |*
icepack hardware.asc hardware.bin
iceprog -d i:0x0403:0x6014:0 hardware.bin
init..
cdone: high
reset..
cdone: high
flash ID: 0xEF 0x40 0x16 0x00
file size: 104090
erase 64kB sector at 0x000000..
erase 64kB sector at 0x010000..
programming..
reading..
VERIFY OK
cdone: high
Bye.
========================= [SUCCESS] Took 8.17 seconds =========================
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