VLSI HW2

D_FF.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity D_FF is
port(
	D: in Bit;
	clk: in std_logic;
	Q: out Bit
);
end D_FF;

architecture BEHAVIOR of D_FF is
begin
process
	begin
		wait until clk'event and D='1';
		if D='1' then
              Q <= D;
		end if;
	end process;
end BEHAVIOR;

MY_CKT.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MY_CKT is
port(
	A1,A2, A3, A4: in Bit;
	D: out Bit
);
end MY_CKT;

architecture DATAFLOW of MY_CKT is
begin
process (A1,A2, A3, A4)
	begin
		if (A1='0') and (A2='0') and (A3='0') and (A4='0') then
			D <= '1';
		elsif (A1='0') and (A2='0') and (A3='1') and (A4='1') then
			D <= '1';
		elsif (A1='1') and (A2='0') and (A3='0') and (A4='0') then
			D <= '1';
		elsif (A1='1') and (A2='0') and (A3='0') and (A4='1') then
			D <= '1';
		elsif (A1='1') and (A2='0') and (A3='1') and (A4='0') then
			D <= '1';
		elsif (A1='1') and (A2='1') and (A3='0') and (A4='0') then
			D <= '1';
		elsif (A1='1') and (A2='1') and (A3='0') and (A4='1') then
			D <= '1';
		else
			D <= '0';
		end if;
	end process;
end DATAFLOW;