[NTNU 104_1] VLSI HW1 - MAX

MAX_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MAX_gate is
port(
	A,B,C : in std_logic_vector(3 downto 0);
	A_max,B_max,C_max : out Bit
);
end MAX_gate;

architecture MAX_arch of MAX_gate is
begin
process (A,B,C)
	begin
		if (A>B) and (B>C) then
			A_max <= '1';
			B_max <= '0';
			C_max <= '0';
		elsif (A>C) and (C>B) then
			A_max <= '1';
			B_max <= '0';
			C_max <= '0';
		elsif (A>C) and (B=C) then	
			A_max <= '1';
			B_max <= '0';
			C_max <= '0';
		elsif (B>A) and (A>C) then
			A_max <= '0';
			B_max <= '1';
			C_max <= '0';
		elsif (B>C) and (C>A) then
			A_max <= '0';
			B_max <= '1';
			C_max <= '0';
		elsif (B>C) and (A=C) then
			A_max <= '0';
			B_max <= '1';
			C_max <= '0';
		elsif (C>A) and (A>B) then
			A_max <= '0';
			B_max <= '0';
			C_max <= '1';
		elsif (C>B) and (B>A) then
			A_max <= '0';
			B_max <= '0';
			C_max <= '1';
		elsif (C>A) and (A=B) then
			A_max <= '0';
			B_max <= '0';
			C_max <= '1';
		else
			A_max <= '0';
			B_max <= '0';
			C_max <= '0';
		end if;
	end process;
end MAX_arch;