SRM596_Div1.v

`define N (64)
`define N1 (63)

module SRM596_Div1(
		   input 	 clk,
		   input 	 rstn,
		   input [31:0]  indata,
		   input 	 wenable,
		   output reg [12:0] answer,
		   output reg	 ans_enable
		   );

   reg [9:0] 			 incounter;
   reg [31:0] 			 data[0:`N1];
   
   reg 				 calcdone;
   reg [11:0] 			 cc;
      
   wire [`N1:0] 		 iszero;
   reg [9:0] 			 bit0num;
   reg 				 all0;

   always@(posedge clk or negedge rstn)
     if(!rstn)
	incounter<=0;
     else if(wenable)	
       incounter<=incounter+1;

   genvar 	di;
   generate
      for(di=0;di<`N;di=di+1)begin :tmp_data
	 always@(posedge clk or negedge rstn)
	   if(!rstn)
	     data[di]<=0;
	   else if(wenable&(incounter==di))	
	     data[di]<=indata;
	   else if(!wenable&calcdone)
	     if(bit0num==0)
	       data[di]<=data[di]>>1;
	     else
	       data[di]<={data[di][31:1],1'b0};
      end
   endgenerate

   always@(posedge clk or negedge rstn)
     if(!rstn)
       calcdone<=0;
     else if(cc==`N-8)
       calcdone<=1;
     else
       calcdone<=0;   

   always@(posedge clk or negedge rstn)
     if(!rstn)
       cc<=0;
     else if(wenable)
       cc<=0;
     else if(calcdone)
       cc<=0;
     else
       cc<=cc+8;

   genvar 	zi;
   generate
      for(zi=0;zi<`N;zi=zi+1)begin :tmp_iszero
	 assign iszero[zi]=!(|data[zi]);
      end
   endgenerate

 
   always@(posedge clk or negedge rstn)
     if(!rstn)begin
       bit0num<=0;
       all0<=0;
     end else if(wenable)begin
       bit0num<=0;
       all0<=1;
     end else if(!calcdone)begin
	bit0num<=bit0num+data[cc][0]+data[cc+1][0]+data[cc+2][0]+data[cc+3][0]		
                           +data[cc+4][0]+data[cc+5][0]+data[cc+6][0]+data[cc+7][0];
	all0<=all0 & iszero[cc]&iszero[cc+1]&iszero[cc+2]&iszero[cc+3]
	  &iszero[cc+4]&iszero[cc+5]&iszero[cc+6]&iszero[cc+7];
     end else begin
       bit0num<=0;
       all0<=1;
     end
   
   always@(posedge clk or negedge rstn)
     if(!rstn)
       answer<=0;
     else if(calcdone&!all0)  
       if(bit0num==0)
	 answer<=answer+1;
       else
	 answer<=answer+bit0num;
   
   always@(posedge clk or negedge rstn)
     if(!rstn)
       ans_enable<=0;
     else if(calcdone&all0)  
       ans_enable<=1;
 
endmodule // SRM596_Div1


`ifndef FPGA
module test();
   reg   clk ;
   reg 	 rstn;
   reg [31:0] indata;
   reg 	      wenable; 
   wire [10:0] answer;
   wire        ans_enable;
   
   reg [31:0]  din[0:`N1];

   integer     datanum=50;
   
   initial  $readmemh("data.hex",din);
   
   initial begin
      clk = 0;
      forever begin
	 #5 clk = ~clk;
      end
   end

   SRM596_Div1 dut(
		   .clk	  (clk),
		   .rstn	  (rstn),
		   .indata	  (indata),
		   .wenable  (wenable), 
		   .answer	  (answer),
		   .ans_enable(ans_enable)
		   );

   integer i;
   initial begin
      rstn <= 1;
      wenable<=0;
      indata<=0;
      
      $display("start.");
      @(posedge clk);
      rstn <= 0;
      @(posedge clk);
      @(posedge clk);
      rstn <= 1;
      @(posedge clk);

      wenable<=1;
      for(i=0;i<datanum;i=i+1)begin
	 indata<=din[i];
	 @(posedge clk);
      end
      wenable<=0;

      @(posedge ans_enable);
      $display("The answer is %d",answer);
      @(posedge clk);
      $display("end.");
      $finish();
   end


endmodule // test
`endif