Created
March 17, 2023 00:47
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Risc-V disassembler in pure, `no_std` Rust, ported from spike-dasm
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| #![allow(non_camel_case_types)] | |
| #![allow(non_snake_case)] | |
| #![allow(non_upper_case_globals)] | |
| pub type rv_inst = u64; | |
| #[derive(Clone, Copy, PartialEq)] | |
| pub enum RvIsa { | |
| Rv32 = 0, | |
| Rv64 = 1, | |
| Rv128 = 2, | |
| } | |
| pub type RwFenceType = u8; | |
| pub const rv_fence_w: RwFenceType = 1; | |
| pub const rv_fence_r: RwFenceType = 2; | |
| pub const rv_fence_o: RwFenceType = 4; | |
| pub const rv_fence_i: RwFenceType = 8; | |
| pub const rv_ireg_sp: u8 = 2; | |
| pub const rv_ireg_ra: u8 = 1; | |
| pub const rv_ireg_zero: u8 = 0; | |
| pub type rvc_constraint = u32; | |
| pub const rvc_csr_eq_0xc82: rvc_constraint = 18; | |
| pub const rvc_csr_eq_0xc81: rvc_constraint = 17; | |
| pub const rvc_csr_eq_0xc80: rvc_constraint = 16; | |
| pub const rvc_csr_eq_0xc02: rvc_constraint = 15; | |
| pub const rvc_csr_eq_0xc01: rvc_constraint = 14; | |
| pub const rvc_csr_eq_0xc00: rvc_constraint = 13; | |
| pub const rvc_csr_eq_0x003: rvc_constraint = 12; | |
| pub const rvc_csr_eq_0x002: rvc_constraint = 11; | |
| pub const rvc_csr_eq_0x001: rvc_constraint = 10; | |
| pub const rvc_imm_eq_p1: rvc_constraint = 9; | |
| pub const rvc_imm_eq_n1: rvc_constraint = 8; | |
| pub const rvc_imm_eq_zero: rvc_constraint = 7; | |
| pub const rvc_rs1_eq_ra: rvc_constraint = 6; | |
| pub const rvc_rs2_eq_rs1: rvc_constraint = 5; | |
| pub const rvc_rs2_eq_x0: rvc_constraint = 4; | |
| pub const rvc_rs1_eq_x0: rvc_constraint = 3; | |
| pub const rvc_rd_eq_x0: rvc_constraint = 2; | |
| pub const rvc_rd_eq_ra: rvc_constraint = 1; | |
| pub type rv_codec = u8; | |
| pub const rv_codec_css_sqsp: rv_codec = 47; | |
| pub const rv_codec_css_sdsp: rv_codec = 46; | |
| pub const rv_codec_css_swsp: rv_codec = 45; | |
| pub const rv_codec_cs_sq: rv_codec = 44; | |
| pub const rv_codec_cs_sd: rv_codec = 43; | |
| pub const rv_codec_cs_sw: rv_codec = 42; | |
| pub const rv_codec_cs: rv_codec = 41; | |
| pub const rv_codec_cr_jr: rv_codec = 40; | |
| pub const rv_codec_cr_jalr: rv_codec = 39; | |
| pub const rv_codec_cr_mv: rv_codec = 38; | |
| pub const rv_codec_cr: rv_codec = 37; | |
| pub const rv_codec_cl_lq: rv_codec = 36; | |
| pub const rv_codec_cl_ld: rv_codec = 35; | |
| pub const rv_codec_cl_lw: rv_codec = 34; | |
| pub const RV_CODEC_CJ_JAL: rv_codec = 33; | |
| pub const rv_codec_cj: rv_codec = 32; | |
| pub const rv_codec_ciw_4spn: rv_codec = 31; | |
| pub const rv_codec_ci_none: rv_codec = 30; | |
| pub const rv_codec_ci_lui: rv_codec = 29; | |
| pub const rv_codec_ci_li: rv_codec = 28; | |
| pub const rv_codec_ci_lqsp: rv_codec = 27; | |
| pub const rv_codec_ci_ldsp: rv_codec = 26; | |
| pub const rv_codec_ci_lwsp: rv_codec = 25; | |
| pub const rv_codec_ci_16sp: rv_codec = 24; | |
| pub const rv_codec_ci_sh6: rv_codec = 23; | |
| pub const rv_codec_ci: rv_codec = 21; | |
| pub const rv_codec_cb_sh6: rv_codec = 20; | |
| pub const rv_codec_cb_imm: rv_codec = 18; | |
| pub const rv_codec_cb: rv_codec = 17; | |
| pub const rv_codec_r_f: rv_codec = 16; | |
| pub const rv_codec_r_l: rv_codec = 15; | |
| pub const rv_codec_r_a: rv_codec = 14; | |
| pub const rv_codec_r4_m: rv_codec = 13; | |
| pub const rv_codec_r_m: rv_codec = 12; | |
| pub const rv_codec_r: rv_codec = 11; | |
| pub const rv_codec_sb: rv_codec = 10; | |
| pub const rv_codec_s: rv_codec = 9; | |
| pub const rv_codec_i_csr: rv_codec = 8; | |
| pub const rv_codec_i_sh7: rv_codec = 7; | |
| pub const rv_codec_i_sh6: rv_codec = 6; | |
| pub const rv_codec_i_sh5: rv_codec = 5; | |
| pub const rv_codec_i: rv_codec = 4; | |
| pub const rv_codec_uj: rv_codec = 3; | |
| pub const RV_CODEC_U: rv_codec = 2; | |
| pub const RV_CODEC_NONE: rv_codec = 1; | |
| pub const rv_codec_illegal: rv_codec = 0; | |
| #[derive(Clone, Copy)] | |
| #[repr(usize)] | |
| enum RvOp { | |
| illegal, | |
| lui, | |
| auipc, | |
| jal, | |
| jalr, | |
| beq, | |
| bne, | |
| blt, | |
| bge, | |
| bltu, | |
| bgeu, | |
| lb, | |
| lh, | |
| lw, | |
| lbu, | |
| lhu, | |
| sb, | |
| sh, | |
| sw, | |
| addi, | |
| slti, | |
| sltiu, | |
| xori, | |
| ori, | |
| andi, | |
| slli, | |
| srli, | |
| srai, | |
| add, | |
| sub, | |
| sll, | |
| slt, | |
| sltu, | |
| xor, | |
| srl, | |
| sra, | |
| or, | |
| and, | |
| fence, | |
| fence_i, | |
| lwu, | |
| ld, | |
| sd, | |
| addiw, | |
| slliw, | |
| srliw, | |
| sraiw, | |
| addw, | |
| subw, | |
| sllw, | |
| srlw, | |
| sraw, | |
| ldu, | |
| lq, | |
| sq, | |
| addid, | |
| sllid, | |
| srlid, | |
| sraid, | |
| addd, | |
| subd, | |
| slld, | |
| srld, | |
| srad, | |
| mul, | |
| mulh, | |
| mulhsu, | |
| mulhu, | |
| div, | |
| divu, | |
| rem, | |
| remu, | |
| mulw, | |
| divw, | |
| divuw, | |
| remw, | |
| remuw, | |
| muld, | |
| divd, | |
| divud, | |
| remd, | |
| remud, | |
| lr_w, | |
| sc_w, | |
| amoswap_w, | |
| amoadd_w, | |
| amoxor_w, | |
| amoor_w, | |
| amoand_w, | |
| amomin_w, | |
| amomax_w, | |
| amominu_w, | |
| amomaxu_w, | |
| lr_d, | |
| sc_d, | |
| amoswap_d, | |
| amoadd_d, | |
| amoxor_d, | |
| amoor_d, | |
| amoand_d, | |
| amomin_d, | |
| amomax_d, | |
| amominu_d, | |
| amomaxu_d, | |
| lr_q, | |
| sc_q, | |
| amoswap_q, | |
| amoadd_q, | |
| amoxor_q, | |
| amoor_q, | |
| amoand_q, | |
| amomin_q, | |
| amomax_q, | |
| amominu_q, | |
| amomaxu_q, | |
| ecall, | |
| ebreak, | |
| uret, | |
| sret, | |
| hret, | |
| mret, | |
| dret, | |
| sfence_vm, | |
| sfence_vma, | |
| wfi, | |
| csrrw, | |
| csrrs, | |
| csrrc, | |
| csrrwi, | |
| csrrsi, | |
| csrrci, | |
| flw, | |
| fsw, | |
| fmadd_s, | |
| fmsub_s, | |
| fnmsub_s, | |
| fnmadd_s, | |
| fadd_s, | |
| fsub_s, | |
| fmul_s, | |
| fdiv_s, | |
| fsgnj_s, | |
| fsgnjn_s, | |
| fsgnjx_s, | |
| fmin_s, | |
| fmax_s, | |
| fsqrt_s, | |
| fle_s, | |
| flt_s, | |
| feq_s, | |
| fcvt_w_s, | |
| fcvt_wu_s, | |
| fcvt_s_w, | |
| fcvt_s_wu, | |
| fmv_x_s, | |
| fclass_s, | |
| fmv_s_x, | |
| fcvt_l_s, | |
| fcvt_lu_s, | |
| fcvt_s_l, | |
| fcvt_s_lu, | |
| fld, | |
| fsd, | |
| fmadd_d, | |
| fmsub_d, | |
| fnmsub_d, | |
| fnmadd_d, | |
| fadd_d, | |
| fsub_d, | |
| fmul_d, | |
| fdiv_d, | |
| fsgnj_d, | |
| fsgnjn_d, | |
| fsgnjx_d, | |
| fmin_d, | |
| fmax_d, | |
| fcvt_s_d, | |
| fcvt_d_s, | |
| fsqrt_d, | |
| fle_d, | |
| flt_d, | |
| feq_d, | |
| fcvt_w_d, | |
| fcvt_wu_d, | |
| fcvt_d_w, | |
| fcvt_d_wu, | |
| fclass_d, | |
| fcvt_l_d, | |
| fcvt_lu_d, | |
| fmv_x_d, | |
| fcvt_d_l, | |
| fcvt_d_lu, | |
| fmv_d_x, | |
| flq, | |
| fsq, | |
| fmadd_q, | |
| fmsub_q, | |
| fnmsub_q, | |
| fnmadd_q, | |
| fadd_q, | |
| fsub_q, | |
| fmul_q, | |
| fdiv_q, | |
| fsgnj_q, | |
| fsgnjn_q, | |
| fsgnjx_q, | |
| fmin_q, | |
| fmax_q, | |
| fcvt_s_q, | |
| fcvt_q_s, | |
| fcvt_d_q, | |
| fcvt_q_d, | |
| fsqrt_q, | |
| fle_q, | |
| flt_q, | |
| feq_q, | |
| fcvt_w_q, | |
| fcvt_wu_q, | |
| fcvt_q_w, | |
| fcvt_q_wu, | |
| fclass_q, | |
| fcvt_l_q, | |
| fcvt_lu_q, | |
| fcvt_q_l, | |
| fcvt_q_lu, | |
| fmv_x_q, | |
| fmv_q_x, | |
| c_addi4spn, | |
| c_fld, | |
| c_lw, | |
| c_flw, | |
| c_fsd, | |
| c_sw, | |
| c_fsw, | |
| c_nop, | |
| c_addi, | |
| c_jal, | |
| c_li, | |
| c_addi16sp, | |
| c_lui, | |
| c_srli, | |
| c_srai, | |
| c_andi, | |
| c_sub, | |
| c_xor, | |
| c_or, | |
| c_and, | |
| c_subw, | |
| c_addw, | |
| c_j, | |
| c_beqz, | |
| c_bnez, | |
| c_slli, | |
| c_fldsp, | |
| c_lwsp, | |
| c_flwsp, | |
| c_jr, | |
| c_mv, | |
| c_ebreak, | |
| c_jalr, | |
| c_add, | |
| c_fsdsp, | |
| c_swsp, | |
| c_fswsp, | |
| c_ld, | |
| c_sd, | |
| c_addiw, | |
| c_ldsp, | |
| c_sdsp, | |
| c_lq, | |
| c_sq, | |
| c_lqsp, | |
| c_sqsp, | |
| nop, | |
| mv, | |
| not, | |
| neg, | |
| negw, | |
| sext_w, | |
| seqz, | |
| snez, | |
| sltz, | |
| sgtz, | |
| fmv_s, | |
| fabs_s, | |
| fneg_s, | |
| fmv_d, | |
| fabs_d, | |
| fneg_d, | |
| fmv_q, | |
| fabs_q, | |
| fneg_q, | |
| beqz, | |
| bnez, | |
| blez, | |
| bgez, | |
| bltz, | |
| bgtz, | |
| ble, | |
| bleu, | |
| bgt, | |
| bgtu, | |
| j, | |
| ret, | |
| jr, | |
| rdcycle, | |
| rdtime, | |
| rdinstret, | |
| rdcycleh, | |
| rdtimeh, | |
| rdinstreth, | |
| frcsr, | |
| frrm, | |
| frflags, | |
| fscsr, | |
| fsrm, | |
| fsflags, | |
| fsrmi, | |
| fsflagsi, | |
| } | |
| #[derive(Copy, Clone)] | |
| #[repr(C)] | |
| pub struct rv_decode { | |
| pc: u64, | |
| inst: u64, | |
| imm: i32, | |
| op: RvOp, | |
| codec: u8, | |
| rd: u8, | |
| rs1: u8, | |
| rs2: u8, | |
| rs3: u8, | |
| rm: u8, | |
| pred: u8, | |
| succ: u8, | |
| aq: u8, | |
| rl: u8, | |
| } | |
| #[derive(Copy, Clone)] | |
| pub struct rv_opcode_data { | |
| name: &'static str, | |
| codec: rv_codec, | |
| format: &'static [u8], | |
| pseudo: &'static [rv_comp_data], | |
| decomp_rv32: Option<RvOp>, | |
| decomp_rv64: Option<RvOp>, | |
| decomp_rv128: Option<RvOp>, | |
| decomp_data: RvCdImmediate, | |
| } | |
| #[derive(Copy, Clone)] | |
| pub struct rv_comp_data { | |
| op: RvOp, | |
| constraints: &'static [rvc_constraint], | |
| } | |
| #[derive(PartialEq, Copy, Clone)] | |
| enum RvCdImmediate { | |
| None, | |
| Nz, | |
| NzHint, | |
| } | |
| const RV_IREG_NAME_SYM: &[&str] = &[ | |
| "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", | |
| "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", | |
| "t5", "t6", | |
| ]; | |
| const RV_FREG_NAME_SYM: &[&str] = &[ | |
| "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", "fa0", "fa1", "fa2", | |
| "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", | |
| "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", | |
| ]; | |
| const RV_FMT_NONE: &[u8] = b"O\t"; | |
| const RV_FMT_RS1: &[u8] = b"O\t1"; | |
| const RV_FMT_OFFSET: &[u8] = b"O\to"; | |
| const RV_FMT_PRED_SUCC: &[u8] = b"O\tp,s"; | |
| const RV_FMT_RS1_RS2: &[u8] = b"O\t1,2"; | |
| const RV_FMT_RD_IMM: &[u8] = b"O\t0,i"; | |
| const RD_FMT_RD_OFFSET: &[u8] = b"O\t0,o"; | |
| const RV_FMT_RD_RS1_RS2: &[u8] = b"O\t0,1,2"; | |
| const RV_FMT_FRD_RS1: &[u8] = b"O\t3,1"; | |
| const RV_FMT_RD_FRS1: &[u8] = b"O\t0,4"; | |
| const RV_FMT_RD_FRS1_FRS2: &[u8] = b"O\t0,4,5"; | |
| const RV_FMT_FRD_FRS1_FRS2: &[u8] = b"O\t3,4,5"; | |
| const RV_FMT_RM_FRD_FRS1: &[u8] = b"O\tr,3,4"; | |
| const RV_FMT_RM_FRD_RS1: &[u8] = b"O\tr,3,1"; | |
| const RV_FMT_RM_RD_FRS1: &[u8] = b"O\tr,0,4"; | |
| const RV_FMT_RM_FRD_FRS1_FRS2: &[u8] = b"O\tr,3,4,5"; | |
| const RV_FMT_RM_FRD_FRS1_FRS2_FRS3: &[u8] = b"O\tr,3,4,5,6"; | |
| const RV_FMT_RD_RS1_IMM: &[u8] = b"O\t0,1,i"; | |
| const RV_FMT_RD_RS1_OFFSET: &[u8] = b"O\t0,1,i"; | |
| const RV_FMT_RD_OFFSET_RS1: &[u8] = b"O\t0,i(1)"; | |
| const RV_FMT_FRD_OFFSET_RS1: &[u8] = b"O\t3,i(1)"; | |
| const RV_FMT_RD_CSR_RS1: &[u8] = b"O\t0,c,1"; | |
| const RV_FMT_RD_CSR_ZIMM: &[u8] = b"O\t0,c,7"; | |
| const RV_FMT_RS2_OFFSET_RS1: &[u8] = b"O\t2,i(1)"; | |
| const RV_FMT_FRS2_OFFSET_RS1: &[u8] = b"O\t5,i(1)"; | |
| const RV_FMT_RS1_RS2_OFFSET: &[u8] = b"O\t1,2,o"; | |
| const RV_FMT_RS2_RS1_OFFSET: &[u8] = b"O\t2,1,o"; | |
| const RV_FMT_AQRL_RD_RS2_RS1: &[u8] = b"OAR\t0,2,(1)"; | |
| const RV_FMT_AQRL_RD_RS1: &[u8] = b"OAR\t0,(1)"; | |
| const RV_FMT_RD: &[u8] = b"O\t0"; | |
| const RV_FMT_RD_ZIMM: &[u8] = b"O\t0,7"; | |
| const RV_FMT_RD_RS1: &[u8] = b"O\t0,1"; | |
| const RV_FMT_RD_RS2: &[u8] = b"O\t0,2"; | |
| const RV_FMT_RS1_OFFSET: &[u8] = b"O\t1,o"; | |
| const RV_FMT_RS2_OFFSET: &[u8] = b"O\t2,o"; | |
| const rvcc_imm_eq_zero: [rvc_constraint; 1] = [rvc_imm_eq_zero]; | |
| const rvcc_imm_eq_n1: [rvc_constraint; 1] = [rvc_imm_eq_n1]; | |
| const rvcc_imm_eq_p1: [rvc_constraint; 1] = [rvc_imm_eq_p1]; | |
| const rvcc_rs1_eq_x0: [rvc_constraint; 1] = [rvc_rs1_eq_x0]; | |
| const rvcc_rs2_eq_x0: [rvc_constraint; 1] = [rvc_rs2_eq_x0]; | |
| const rvcc_rs2_eq_rs1: [rvc_constraint; 1] = [rvc_rs2_eq_rs1]; | |
| const rvcc_jal_j: [rvc_constraint; 1] = [rvc_rd_eq_x0]; | |
| const rvcc_jal_jal: [rvc_constraint; 1] = [rvc_rd_eq_ra]; | |
| const rvcc_jalr_jr: [rvc_constraint; 2] = [rvc_rd_eq_x0, rvc_imm_eq_zero]; | |
| const rvcc_jalr_jalr: [rvc_constraint; 2] = [rvc_rd_eq_ra, rvc_imm_eq_zero]; | |
| const rvcc_jalr_ret: [rvc_constraint; 2] = [rvc_rd_eq_x0, rvc_rs1_eq_ra]; | |
| const rvcc_addi_nop: [rvc_constraint; 3] = [rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero]; | |
| const rvcc_rdcycle: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0xc00]; | |
| const rvcc_rdtime: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0xc01]; | |
| const rvcc_rdinstret: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0xc02]; | |
| const rvcc_rdcycleh: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0xc80]; | |
| const rvcc_rdtimeh: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0xc81]; | |
| const rvcc_rdinstreth: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0xc82]; | |
| const rvcc_frcsr: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0x003]; | |
| const rvcc_frrm: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0x002]; | |
| const rvcc_frflags: [rvc_constraint; 2] = [rvc_rs1_eq_x0, rvc_csr_eq_0x001]; | |
| const rvcc_fscsr: [rvc_constraint; 1] = [rvc_csr_eq_0x003]; | |
| const rvcc_fsrm: [rvc_constraint; 1] = [rvc_csr_eq_0x002]; | |
| const rvcc_fsflags: [rvc_constraint; 1] = [rvc_csr_eq_0x001]; | |
| const rvcc_fsrmi: [rvc_constraint; 1] = [rvc_csr_eq_0x002]; | |
| const rvcc_fsflagsi: [rvc_constraint; 1] = [rvc_csr_eq_0x001]; | |
| const rvcp_jal: [rv_comp_data; 2] = [ | |
| rv_comp_data { | |
| op: RvOp::j, | |
| constraints: &rvcc_jal_j, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::jal, | |
| constraints: &rvcc_jal_jal, | |
| }, | |
| ]; | |
| const rvcp_jalr: [rv_comp_data; 3] = [ | |
| rv_comp_data { | |
| op: RvOp::ret, | |
| constraints: &rvcc_jalr_ret, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::jr, | |
| constraints: &rvcc_jalr_jr, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::jalr, | |
| constraints: &rvcc_jalr_jalr, | |
| }, | |
| ]; | |
| const rvcp_beq: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::beqz, | |
| constraints: &rvcc_rs2_eq_x0, | |
| }]; | |
| const rvcp_bne: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::bnez, | |
| constraints: &rvcc_rs2_eq_x0, | |
| }]; | |
| const rvcp_blt: [rv_comp_data; 3] = [ | |
| rv_comp_data { | |
| op: RvOp::bltz, | |
| constraints: &rvcc_rs2_eq_x0, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::bgtz, | |
| constraints: &rvcc_rs1_eq_x0, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::bgt, | |
| constraints: &[], | |
| }, | |
| ]; | |
| const rvcp_bge: [rv_comp_data; 3] = [ | |
| rv_comp_data { | |
| op: RvOp::blez, | |
| constraints: &rvcc_rs1_eq_x0, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::bgez, | |
| constraints: &rvcc_rs2_eq_x0, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::ble, | |
| constraints: &[], | |
| }, | |
| ]; | |
| const rvcp_bltu: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::bgtu, | |
| constraints: &[], | |
| }]; | |
| const rvcp_bgeu: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::bleu, | |
| constraints: &[], | |
| }]; | |
| const rvcp_addi: [rv_comp_data; 2] = [ | |
| rv_comp_data { | |
| op: RvOp::nop, | |
| constraints: &rvcc_addi_nop, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::mv, | |
| constraints: &rvcc_imm_eq_zero, | |
| }, | |
| ]; | |
| const rvcp_sltiu: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::seqz, | |
| constraints: &rvcc_imm_eq_p1, | |
| }]; | |
| const rvcp_xori: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::not, | |
| constraints: &rvcc_imm_eq_n1, | |
| }]; | |
| const rvcp_sub: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::neg, | |
| constraints: &rvcc_rs1_eq_x0, | |
| }]; | |
| const rvcp_slt: [rv_comp_data; 2] = [ | |
| rv_comp_data { | |
| op: RvOp::sltz, | |
| constraints: &rvcc_rs2_eq_x0, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::sgtz, | |
| constraints: &rvcc_rs1_eq_x0, | |
| }, | |
| ]; | |
| const rvcp_sltu: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::snez, | |
| constraints: &rvcc_rs1_eq_x0, | |
| }]; | |
| const rvcp_addiw: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::sext_w, | |
| constraints: &rvcc_imm_eq_zero, | |
| }]; | |
| const rvcp_subw: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::negw, | |
| constraints: &rvcc_rs1_eq_x0, | |
| }]; | |
| const rvcp_csrrw: [rv_comp_data; 3] = [ | |
| rv_comp_data { | |
| op: RvOp::fscsr, | |
| constraints: &rvcc_fscsr, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::fsrm, | |
| constraints: &rvcc_fsrm, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::fsflags, | |
| constraints: &rvcc_fsflags, | |
| }, | |
| ]; | |
| const rvcp_csrrs: [rv_comp_data; 9] = [ | |
| rv_comp_data { | |
| op: RvOp::rdcycle, | |
| constraints: &rvcc_rdcycle, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::rdtime, | |
| constraints: &rvcc_rdtime, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::rdinstret, | |
| constraints: &rvcc_rdinstret, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::rdcycleh, | |
| constraints: &rvcc_rdcycleh, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::rdtimeh, | |
| constraints: &rvcc_rdtimeh, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::rdinstreth, | |
| constraints: &rvcc_rdinstreth, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::frcsr, | |
| constraints: &rvcc_frcsr, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::frrm, | |
| constraints: &rvcc_frrm, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::frflags, | |
| constraints: &rvcc_frflags, | |
| }, | |
| ]; | |
| const rvcp_csrrwi: [rv_comp_data; 2] = [ | |
| rv_comp_data { | |
| op: RvOp::fsrmi, | |
| constraints: &rvcc_fsrmi, | |
| }, | |
| rv_comp_data { | |
| op: RvOp::fsflagsi, | |
| constraints: &rvcc_fsflagsi, | |
| }, | |
| ]; | |
| const rvcp_fsgnj_s: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fmv_s, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| const rvcp_fsgnjn_s: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fneg_s, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| const rvcp_fsgnjx_s: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fabs_s, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| const rvcp_fsgnj_d: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fmv_d, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| const rvcp_fsgnjn_d: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fneg_d, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| const rvcp_fsgnjx_d: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fabs_d, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| const rvcp_fsgnj_q: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fmv_q, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| const rvcp_fsgnjn_q: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fneg_q, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| const rvcp_fsgnjx_q: [rv_comp_data; 1] = [rv_comp_data { | |
| op: RvOp::fabs_q, | |
| constraints: &rvcc_rs2_eq_rs1, | |
| }]; | |
| pub const opcode_data: [rv_opcode_data; 319] = [ | |
| rv_opcode_data { | |
| name: "illegal", | |
| codec: rv_codec_illegal, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lui", | |
| codec: RV_CODEC_U, | |
| format: RV_FMT_RD_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "auipc", | |
| codec: RV_CODEC_U, | |
| format: RD_FMT_RD_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "jal", | |
| codec: rv_codec_uj, | |
| format: RD_FMT_RD_OFFSET, | |
| pseudo: &rvcp_jal, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "jalr", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_OFFSET, | |
| pseudo: &rvcp_jalr, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "beq", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_RS2_OFFSET, | |
| pseudo: &rvcp_beq, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bne", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_RS2_OFFSET, | |
| pseudo: &rvcp_bne, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "blt", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_RS2_OFFSET, | |
| pseudo: &rvcp_blt, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bge", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_RS2_OFFSET, | |
| pseudo: &rvcp_bge, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bltu", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_RS2_OFFSET, | |
| pseudo: &rvcp_bltu, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bgeu", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_RS2_OFFSET, | |
| pseudo: &rvcp_bgeu, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lb", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lh", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lw", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lbu", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lhu", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sb", | |
| codec: rv_codec_s, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sh", | |
| codec: rv_codec_s, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sw", | |
| codec: rv_codec_s, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "addi", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &rvcp_addi, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "slti", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sltiu", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &rvcp_sltiu, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "xori", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &rvcp_xori, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "ori", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "andi", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "slli", | |
| codec: rv_codec_i_sh7, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "srli", | |
| codec: rv_codec_i_sh7, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "srai", | |
| codec: rv_codec_i_sh7, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "add", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sub", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &rvcp_sub, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sll", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "slt", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &rvcp_slt, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sltu", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &rvcp_sltu, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "xor", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "srl", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sra", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "or", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "and", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fence", | |
| codec: rv_codec_r_f, | |
| format: RV_FMT_PRED_SUCC, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fence.i", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lwu", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "ld", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sd", | |
| codec: rv_codec_s, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "addiw", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &rvcp_addiw, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "slliw", | |
| codec: rv_codec_i_sh5, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "srliw", | |
| codec: rv_codec_i_sh5, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sraiw", | |
| codec: rv_codec_i_sh5, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "addw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "subw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &rvcp_subw, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sllw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "srlw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sraw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "ldu", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lq", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sq", | |
| codec: rv_codec_s, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "addid", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sllid", | |
| codec: rv_codec_i_sh6, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "srlid", | |
| codec: rv_codec_i_sh6, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sraid", | |
| codec: rv_codec_i_sh6, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "addd", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "subd", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "slld", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "srld", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "srad", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "mul", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "mulh", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "mulhsu", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "mulhu", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "div", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "divu", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "rem", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "remu", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "mulw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "divw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "divuw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "remw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "remuw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "muld", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "divd", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "divud", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "remd", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "remud", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lr.w", | |
| codec: rv_codec_r_l, | |
| format: RV_FMT_AQRL_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sc.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoswap.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoadd.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoxor.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoor.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoand.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomin.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomax.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amominu.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomaxu.w", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lr.d", | |
| codec: rv_codec_r_l, | |
| format: RV_FMT_AQRL_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sc.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoswap.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoadd.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoxor.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoor.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoand.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomin.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomax.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amominu.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomaxu.d", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "lr.q", | |
| codec: rv_codec_r_l, | |
| format: RV_FMT_AQRL_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sc.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoswap.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoadd.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoxor.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoor.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amoand.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomin.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomax.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amominu.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "amomaxu.q", | |
| codec: rv_codec_r_a, | |
| format: RV_FMT_AQRL_RD_RS2_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "ecall", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "ebreak", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "uret", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sret", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "hret", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "mret", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "dret", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sfence.vm", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sfence.vma", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "wfi", | |
| codec: RV_CODEC_NONE, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "csrrw", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_CSR_RS1, | |
| pseudo: &rvcp_csrrw, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "csrrs", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_CSR_RS1, | |
| pseudo: &rvcp_csrrs, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "csrrc", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_CSR_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "csrrwi", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_CSR_ZIMM, | |
| pseudo: &rvcp_csrrwi, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "csrrsi", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_CSR_ZIMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "csrrci", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_CSR_ZIMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "flw", | |
| codec: rv_codec_i, | |
| format: RV_FMT_FRD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsw", | |
| codec: rv_codec_s, | |
| format: RV_FMT_FRS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmadd.s", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmsub.s", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fnmsub.s", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fnmadd.s", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fadd.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsub.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmul.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fdiv.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnj.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnj_s, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnjn.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnjn_s, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnjx.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnjx_s, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmin.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmax.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsqrt.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fle.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "flt.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "feq.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.w.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.wu.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.s.w", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.s.wu", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.x.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fclass.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.s.x", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.l.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.lu.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.s.l", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.s.lu", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fld", | |
| codec: rv_codec_i, | |
| format: RV_FMT_FRD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsd", | |
| codec: rv_codec_s, | |
| format: RV_FMT_FRS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmadd.d", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmsub.d", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fnmsub.d", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fnmadd.d", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fadd.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsub.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmul.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fdiv.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnj.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnj_d, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnjn.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnjn_d, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnjx.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnjx_d, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmin.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmax.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.s.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.d.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsqrt.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fle.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "flt.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "feq.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.w.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.wu.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.d.w", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.d.wu", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fclass.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.l.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.lu.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.x.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.d.l", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.d.lu", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.d.x", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "flq", | |
| codec: rv_codec_i, | |
| format: RV_FMT_FRD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsq", | |
| codec: rv_codec_s, | |
| format: RV_FMT_FRS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmadd.q", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmsub.q", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fnmsub.q", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fnmadd.q", | |
| codec: rv_codec_r4_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2_FRS3, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fadd.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsub.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmul.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fdiv.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnj.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnj_q, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnjn.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnjn_q, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsgnjx.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &rvcp_fsgnjx_q, | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmin.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmax.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.s.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.q.s", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.d.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.q.d", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsqrt.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fle.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "flt.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "feq.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1_FRS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.w.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.wu.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.q.w", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.q.wu", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fclass.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.l.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.lu.q", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.q.l", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fcvt.q.lu", | |
| codec: rv_codec_r_m, | |
| format: RV_FMT_RM_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.x.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_FRS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.q.x", | |
| codec: rv_codec_r, | |
| format: RV_FMT_FRD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.addi4spn", | |
| codec: rv_codec_ciw_4spn, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::addi), | |
| decomp_rv64: Some(RvOp::addi), | |
| decomp_rv128: Some(RvOp::addi), | |
| decomp_data: RvCdImmediate::Nz, | |
| }, | |
| rv_opcode_data { | |
| name: "c.fld", | |
| codec: rv_codec_cl_ld, | |
| format: RV_FMT_FRD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::fld), | |
| decomp_rv64: Some(RvOp::fld), | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.lw", | |
| codec: rv_codec_cl_lw, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::lw), | |
| decomp_rv64: Some(RvOp::lw), | |
| decomp_rv128: Some(RvOp::lw), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.flw", | |
| codec: rv_codec_cl_lw, | |
| format: RV_FMT_FRD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::flw), | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.fsd", | |
| codec: rv_codec_cs_sd, | |
| format: RV_FMT_FRS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::fsd), | |
| decomp_rv64: Some(RvOp::fsd), | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.sw", | |
| codec: rv_codec_cs_sw, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::sw), | |
| decomp_rv64: Some(RvOp::sw), | |
| decomp_rv128: Some(RvOp::sw), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.fsw", | |
| codec: rv_codec_cs_sw, | |
| format: RV_FMT_FRS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::fsw), | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.nop", | |
| codec: rv_codec_ci_none, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::addi), | |
| decomp_rv64: Some(RvOp::addi), | |
| decomp_rv128: Some(RvOp::addi), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.addi", | |
| codec: rv_codec_ci, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::addi), | |
| decomp_rv64: Some(RvOp::addi), | |
| decomp_rv128: Some(RvOp::addi), | |
| decomp_data: RvCdImmediate::NzHint, | |
| }, | |
| rv_opcode_data { | |
| name: "c.jal", | |
| codec: RV_CODEC_CJ_JAL, | |
| format: RD_FMT_RD_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::jal), | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.li", | |
| codec: rv_codec_ci_li, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::addi), | |
| decomp_rv64: Some(RvOp::addi), | |
| decomp_rv128: Some(RvOp::addi), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.addi16sp", | |
| codec: rv_codec_ci_16sp, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::addi), | |
| decomp_rv64: Some(RvOp::addi), | |
| decomp_rv128: Some(RvOp::addi), | |
| decomp_data: RvCdImmediate::Nz, | |
| }, | |
| rv_opcode_data { | |
| name: "c.lui", | |
| codec: rv_codec_ci_lui, | |
| format: RV_FMT_RD_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::lui), | |
| decomp_rv64: Some(RvOp::lui), | |
| decomp_rv128: Some(RvOp::lui), | |
| decomp_data: RvCdImmediate::Nz, | |
| }, | |
| rv_opcode_data { | |
| name: "c.srli", | |
| codec: rv_codec_cb_sh6, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::srli), | |
| decomp_rv64: Some(RvOp::srli), | |
| decomp_rv128: Some(RvOp::srli), | |
| decomp_data: RvCdImmediate::Nz, | |
| }, | |
| rv_opcode_data { | |
| name: "c.srai", | |
| codec: rv_codec_cb_sh6, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::srai), | |
| decomp_rv64: Some(RvOp::srai), | |
| decomp_rv128: Some(RvOp::srai), | |
| decomp_data: RvCdImmediate::Nz, | |
| }, | |
| rv_opcode_data { | |
| name: "c.andi", | |
| codec: rv_codec_cb_imm, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::andi), | |
| decomp_rv64: Some(RvOp::andi), | |
| decomp_rv128: Some(RvOp::andi), | |
| decomp_data: RvCdImmediate::Nz, | |
| }, | |
| rv_opcode_data { | |
| name: "c.sub", | |
| codec: rv_codec_cs, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::sub), | |
| decomp_rv64: Some(RvOp::sub), | |
| decomp_rv128: Some(RvOp::sub), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.xor", | |
| codec: rv_codec_cs, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::xor), | |
| decomp_rv64: Some(RvOp::xor), | |
| decomp_rv128: Some(RvOp::xor), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.or", | |
| codec: rv_codec_cs, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::or), | |
| decomp_rv64: Some(RvOp::or), | |
| decomp_rv128: Some(RvOp::or), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.and", | |
| codec: rv_codec_cs, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::and), | |
| decomp_rv64: Some(RvOp::and), | |
| decomp_rv128: Some(RvOp::and), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.subw", | |
| codec: rv_codec_cs, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::subw), | |
| decomp_rv64: Some(RvOp::subw), | |
| decomp_rv128: Some(RvOp::subw), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.addw", | |
| codec: rv_codec_cs, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::addw), | |
| decomp_rv64: Some(RvOp::addw), | |
| decomp_rv128: Some(RvOp::addw), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.j", | |
| codec: rv_codec_cj, | |
| format: RD_FMT_RD_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::jal), | |
| decomp_rv64: Some(RvOp::jal), | |
| decomp_rv128: Some(RvOp::jal), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.beqz", | |
| codec: rv_codec_cb, | |
| format: RV_FMT_RS1_RS2_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::beq), | |
| decomp_rv64: Some(RvOp::beq), | |
| decomp_rv128: Some(RvOp::beq), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.bnez", | |
| codec: rv_codec_cb, | |
| format: RV_FMT_RS1_RS2_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::bne), | |
| decomp_rv64: Some(RvOp::bne), | |
| decomp_rv128: Some(RvOp::bne), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.slli", | |
| codec: rv_codec_ci_sh6, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::slli), | |
| decomp_rv64: Some(RvOp::slli), | |
| decomp_rv128: Some(RvOp::slli), | |
| decomp_data: RvCdImmediate::Nz, | |
| }, | |
| rv_opcode_data { | |
| name: "c.fldsp", | |
| codec: rv_codec_ci_ldsp, | |
| format: RV_FMT_FRD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::fld), | |
| decomp_rv64: Some(RvOp::fld), | |
| decomp_rv128: Some(RvOp::fld), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.lwsp", | |
| codec: rv_codec_ci_lwsp, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::lw), | |
| decomp_rv64: Some(RvOp::lw), | |
| decomp_rv128: Some(RvOp::lw), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.flwsp", | |
| codec: rv_codec_ci_lwsp, | |
| format: RV_FMT_FRD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::flw), | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.jr", | |
| codec: rv_codec_cr_jr, | |
| format: RV_FMT_RD_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::jalr), | |
| decomp_rv64: Some(RvOp::jalr), | |
| decomp_rv128: Some(RvOp::jalr), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.mv", | |
| codec: rv_codec_cr_mv, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::addi), | |
| decomp_rv64: Some(RvOp::addi), | |
| decomp_rv128: Some(RvOp::addi), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.ebreak", | |
| codec: rv_codec_ci_none, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::ebreak), | |
| decomp_rv64: Some(RvOp::ebreak), | |
| decomp_rv128: Some(RvOp::ebreak), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.jalr", | |
| codec: rv_codec_cr_jalr, | |
| format: RV_FMT_RD_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::jalr), | |
| decomp_rv64: Some(RvOp::jalr), | |
| decomp_rv128: Some(RvOp::jalr), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.add", | |
| codec: rv_codec_cr, | |
| format: RV_FMT_RD_RS1_RS2, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::add), | |
| decomp_rv64: Some(RvOp::add), | |
| decomp_rv128: Some(RvOp::add), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.fsdsp", | |
| codec: rv_codec_css_sdsp, | |
| format: RV_FMT_FRS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::fsd), | |
| decomp_rv64: Some(RvOp::fsd), | |
| decomp_rv128: Some(RvOp::fsd), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.swsp", | |
| codec: rv_codec_css_swsp, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::sw), | |
| decomp_rv64: Some(RvOp::sw), | |
| decomp_rv128: Some(RvOp::sw), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.fswsp", | |
| codec: rv_codec_css_swsp, | |
| format: RV_FMT_FRS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: Some(RvOp::fsw), | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.ld", | |
| codec: rv_codec_cl_ld, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: Some(RvOp::ld), | |
| decomp_rv128: Some(RvOp::ld), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.sd", | |
| codec: rv_codec_cs_sd, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: Some(RvOp::sd), | |
| decomp_rv128: Some(RvOp::sd), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.addiw", | |
| codec: rv_codec_ci, | |
| format: RV_FMT_RD_RS1_IMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: Some(RvOp::addiw), | |
| decomp_rv128: Some(RvOp::addiw), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.ldsp", | |
| codec: rv_codec_ci_ldsp, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: Some(RvOp::ld), | |
| decomp_rv128: Some(RvOp::ld), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.sdsp", | |
| codec: rv_codec_css_sdsp, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: Some(RvOp::sd), | |
| decomp_rv128: Some(RvOp::sd), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.lq", | |
| codec: rv_codec_cl_lq, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: Some(RvOp::lq), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.sq", | |
| codec: rv_codec_cs_sq, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: Some(RvOp::sq), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.lqsp", | |
| codec: rv_codec_ci_lqsp, | |
| format: RV_FMT_RD_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: Some(RvOp::lq), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "c.sqsp", | |
| codec: rv_codec_css_sqsp, | |
| format: RV_FMT_RS2_OFFSET_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: Some(RvOp::sq), | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "nop", | |
| codec: rv_codec_i, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "mv", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "not", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "neg", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "negw", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sext.w", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "seqz", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "snez", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sltz", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "sgtz", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS2, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fabs.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fneg.s", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fabs.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fneg.d", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fmv.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fabs.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fneg.q", | |
| codec: rv_codec_r, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "beqz", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bnez", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "blez", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS2_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bgez", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bltz", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bgtz", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS2_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "ble", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS2_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bleu", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS2_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bgt", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS2_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "bgtu", | |
| codec: rv_codec_sb, | |
| format: RV_FMT_RS2_RS1_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "j", | |
| codec: rv_codec_uj, | |
| format: RV_FMT_OFFSET, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "ret", | |
| codec: rv_codec_i, | |
| format: RV_FMT_NONE, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "jr", | |
| codec: rv_codec_i, | |
| format: RV_FMT_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "rdcycle", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "rdtime", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "rdinstret", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "rdcycleh", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "rdtimeh", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "rdinstreth", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "frcsr", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "frrm", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "frflags", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fscsr", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsrm", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsflags", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_RS1, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsrmi", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_ZIMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| rv_opcode_data { | |
| name: "fsflagsi", | |
| codec: rv_codec_i_csr, | |
| format: RV_FMT_RD_ZIMM, | |
| pseudo: &[], | |
| decomp_rv32: None, | |
| decomp_rv64: None, | |
| decomp_rv128: None, | |
| decomp_data: RvCdImmediate::None, | |
| }, | |
| ]; | |
| fn csr_name(csrno: i32) -> Option<&'static str> { | |
| match csrno { | |
| 0 => Some("ustatus"), | |
| 1 => Some("fflags"), | |
| 2 => Some("frm"), | |
| 3 => Some("fcsr"), | |
| 4 => Some("uie"), | |
| 5 => Some("utvec"), | |
| 7 => Some("utvt"), | |
| 8 => Some("vstart"), | |
| 9 => Some("vxsat"), | |
| 10 => Some("vxrm"), | |
| 15 => Some("vcsr"), | |
| 64 => Some("uscratch"), | |
| 65 => Some("uepc"), | |
| 66 => Some("ucause"), | |
| 67 => Some("utval"), | |
| 68 => Some("uip"), | |
| 69 => Some("unxti"), | |
| 70 => Some("uintstatus"), | |
| 72 => Some("uscratchcsw"), | |
| 73 => Some("uscratchcswl"), | |
| 256 => Some("sstatus"), | |
| 258 => Some("sedeleg"), | |
| 259 => Some("sideleg"), | |
| 260 => Some("sie"), | |
| 261 => Some("stvec"), | |
| 262 => Some("scounteren"), | |
| 263 => Some("stvt"), | |
| 320 => Some("sscratch"), | |
| 321 => Some("sepc"), | |
| 322 => Some("scause"), | |
| 323 => Some("stval"), | |
| 324 => Some("sip"), | |
| 325 => Some("snxti"), | |
| 326 => Some("sintstatus"), | |
| 328 => Some("sscratchcsw"), | |
| 329 => Some("sscratchcswl"), | |
| 384 => Some("satp"), | |
| 512 => Some("vsstatus"), | |
| 516 => Some("vsie"), | |
| 517 => Some("vstvec"), | |
| 576 => Some("vsscratch"), | |
| 577 => Some("vsepc"), | |
| 578 => Some("vscause"), | |
| 579 => Some("vstval"), | |
| 580 => Some("vsip"), | |
| 640 => Some("vsatp"), | |
| 768 => Some("mstatus"), | |
| 769 => Some("misa"), | |
| 770 => Some("medeleg"), | |
| 771 => Some("mideleg"), | |
| 772 => Some("mie"), | |
| 773 => Some("mtvec"), | |
| 774 => Some("mcounteren"), | |
| 775 => Some("mtvt"), | |
| 784 => Some("mstatush"), | |
| 800 => Some("mcountinhibit"), | |
| 803 => Some("mhpmevent3"), | |
| 804 => Some("mhpmevent4"), | |
| 805 => Some("mhpmevent5"), | |
| 806 => Some("mhpmevent6"), | |
| 807 => Some("mhpmevent7"), | |
| 808 => Some("mhpmevent8"), | |
| 809 => Some("mhpmevent9"), | |
| 810 => Some("mhpmevent10"), | |
| 811 => Some("mhpmevent11"), | |
| 812 => Some("mhpmevent12"), | |
| 813 => Some("mhpmevent13"), | |
| 814 => Some("mhpmevent14"), | |
| 815 => Some("mhpmevent15"), | |
| 816 => Some("mhpmevent16"), | |
| 817 => Some("mhpmevent17"), | |
| 818 => Some("mhpmevent18"), | |
| 819 => Some("mhpmevent19"), | |
| 820 => Some("mhpmevent20"), | |
| 821 => Some("mhpmevent21"), | |
| 822 => Some("mhpmevent22"), | |
| 823 => Some("mhpmevent23"), | |
| 824 => Some("mhpmevent24"), | |
| 825 => Some("mhpmevent25"), | |
| 826 => Some("mhpmevent26"), | |
| 827 => Some("mhpmevent27"), | |
| 828 => Some("mhpmevent28"), | |
| 829 => Some("mhpmevent29"), | |
| 830 => Some("mhpmevent30"), | |
| 831 => Some("mhpmevent31"), | |
| 832 => Some("mscratch"), | |
| 833 => Some("mepc"), | |
| 834 => Some("mcause"), | |
| 835 => Some("mtval"), | |
| 836 => Some("mip"), | |
| 837 => Some("mnxti"), | |
| 838 => Some("mintstatus"), | |
| 840 => Some("mscratchcsw"), | |
| 841 => Some("mscratchcswl"), | |
| 842 => Some("mtinst"), | |
| 843 => Some("mtval2"), | |
| 928 => Some("pmpcfg0"), | |
| 929 => Some("pmpcfg1"), | |
| 930 => Some("pmpcfg2"), | |
| 931 => Some("pmpcfg3"), | |
| 944 => Some("pmpaddr0"), | |
| 945 => Some("pmpaddr1"), | |
| 946 => Some("pmpaddr2"), | |
| 947 => Some("pmpaddr3"), | |
| 948 => Some("pmpaddr4"), | |
| 949 => Some("pmpaddr5"), | |
| 950 => Some("pmpaddr6"), | |
| 951 => Some("pmpaddr7"), | |
| 952 => Some("pmpaddr8"), | |
| 953 => Some("pmpaddr9"), | |
| 954 => Some("pmpaddr10"), | |
| 955 => Some("pmpaddr11"), | |
| 956 => Some("pmpaddr12"), | |
| 957 => Some("pmpaddr13"), | |
| 958 => Some("pmpaddr14"), | |
| 959 => Some("pmpaddr15"), | |
| 1536 => Some("hstatus"), | |
| 1538 => Some("hedeleg"), | |
| 1539 => Some("hideleg"), | |
| 1540 => Some("hie"), | |
| 1541 => Some("htimedelta"), | |
| 1542 => Some("hcounteren"), | |
| 1543 => Some("hgeie"), | |
| 1557 => Some("htimedeltah"), | |
| 1603 => Some("htval"), | |
| 1604 => Some("hip"), | |
| 1605 => Some("hvip"), | |
| 1610 => Some("htinst"), | |
| 1664 => Some("hgatp"), | |
| 1952 => Some("tselect"), | |
| 1953 => Some("tdata1"), | |
| 1954 => Some("tdata2"), | |
| 1955 => Some("tdata3"), | |
| 1956 => Some("tinfo"), | |
| 1957 => Some("tcontrol"), | |
| 1960 => Some("mcontext"), | |
| 1961 => Some("mnoise"), | |
| 1962 => Some("scontext"), | |
| 1968 => Some("dcsr"), | |
| 1969 => Some("dpc"), | |
| 1970 => Some("dscratch0"), | |
| 1971 => Some("dscratch1"), | |
| 2816 => Some("mcycle"), | |
| 2818 => Some("minstret"), | |
| 2819 => Some("mhpmcounter3"), | |
| 2820 => Some("mhpmcounter4"), | |
| 2821 => Some("mhpmcounter5"), | |
| 2822 => Some("mhpmcounter6"), | |
| 2823 => Some("mhpmcounter7"), | |
| 2824 => Some("mhpmcounter8"), | |
| 2825 => Some("mhpmcounter9"), | |
| 2826 => Some("mhpmcounter10"), | |
| 2827 => Some("mhpmcounter11"), | |
| 2828 => Some("mhpmcounter12"), | |
| 2829 => Some("mhpmcounter13"), | |
| 2830 => Some("mhpmcounter14"), | |
| 2831 => Some("mhpmcounter15"), | |
| 2832 => Some("mhpmcounter16"), | |
| 2833 => Some("mhpmcounter17"), | |
| 2834 => Some("mhpmcounter18"), | |
| 2835 => Some("mhpmcounter19"), | |
| 2836 => Some("mhpmcounter20"), | |
| 2837 => Some("mhpmcounter21"), | |
| 2838 => Some("mhpmcounter22"), | |
| 2839 => Some("mhpmcounter23"), | |
| 2840 => Some("mhpmcounter24"), | |
| 2841 => Some("mhpmcounter25"), | |
| 2842 => Some("mhpmcounter26"), | |
| 2843 => Some("mhpmcounter27"), | |
| 2844 => Some("mhpmcounter28"), | |
| 2845 => Some("mhpmcounter29"), | |
| 2846 => Some("mhpmcounter30"), | |
| 2847 => Some("mhpmcounter31"), | |
| 2944 => Some("mcycleh"), | |
| 2946 => Some("minstreth"), | |
| 2947 => Some("mhpmcounter3h"), | |
| 2948 => Some("mhpmcounter4h"), | |
| 2949 => Some("mhpmcounter5h"), | |
| 2950 => Some("mhpmcounter6h"), | |
| 2951 => Some("mhpmcounter7h"), | |
| 2952 => Some("mhpmcounter8h"), | |
| 2953 => Some("mhpmcounter9h"), | |
| 2954 => Some("mhpmcounter10h"), | |
| 2955 => Some("mhpmcounter11h"), | |
| 2956 => Some("mhpmcounter12h"), | |
| 2957 => Some("mhpmcounter13h"), | |
| 2958 => Some("mhpmcounter14h"), | |
| 2959 => Some("mhpmcounter15h"), | |
| 2960 => Some("mhpmcounter16h"), | |
| 2961 => Some("mhpmcounter17h"), | |
| 2962 => Some("mhpmcounter18h"), | |
| 2963 => Some("mhpmcounter19h"), | |
| 2964 => Some("mhpmcounter20h"), | |
| 2965 => Some("mhpmcounter21h"), | |
| 2966 => Some("mhpmcounter22h"), | |
| 2967 => Some("mhpmcounter23h"), | |
| 2968 => Some("mhpmcounter24h"), | |
| 2969 => Some("mhpmcounter25h"), | |
| 2970 => Some("mhpmcounter26h"), | |
| 2971 => Some("mhpmcounter27h"), | |
| 2972 => Some("mhpmcounter28h"), | |
| 2973 => Some("mhpmcounter29h"), | |
| 2974 => Some("mhpmcounter30h"), | |
| 2975 => Some("mhpmcounter31h"), | |
| 3072 => Some("cycle"), | |
| 3073 => Some("time"), | |
| 3074 => Some("instret"), | |
| 3075 => Some("hpmcounter3"), | |
| 3076 => Some("hpmcounter4"), | |
| 3077 => Some("hpmcounter5"), | |
| 3078 => Some("hpmcounter6"), | |
| 3079 => Some("hpmcounter7"), | |
| 3080 => Some("hpmcounter8"), | |
| 3081 => Some("hpmcounter9"), | |
| 3082 => Some("hpmcounter10"), | |
| 3083 => Some("hpmcounter11"), | |
| 3084 => Some("hpmcounter12"), | |
| 3085 => Some("hpmcounter13"), | |
| 3086 => Some("hpmcounter14"), | |
| 3087 => Some("hpmcounter15"), | |
| 3088 => Some("hpmcounter16"), | |
| 3089 => Some("hpmcounter17"), | |
| 3090 => Some("hpmcounter18"), | |
| 3091 => Some("hpmcounter19"), | |
| 3092 => Some("hpmcounter20"), | |
| 3093 => Some("hpmcounter21"), | |
| 3094 => Some("hpmcounter22"), | |
| 3095 => Some("hpmcounter23"), | |
| 3096 => Some("hpmcounter24"), | |
| 3097 => Some("hpmcounter25"), | |
| 3098 => Some("hpmcounter26"), | |
| 3099 => Some("hpmcounter27"), | |
| 3100 => Some("hpmcounter28"), | |
| 3101 => Some("hpmcounter29"), | |
| 3102 => Some("hpmcounter30"), | |
| 3103 => Some("hpmcounter31"), | |
| 3104 => Some("vl"), | |
| 3105 => Some("vtype"), | |
| 3106 => Some("vlenb"), | |
| 3200 => Some("cycleh"), | |
| 3201 => Some("timeh"), | |
| 3202 => Some("instreth"), | |
| 3203 => Some("hpmcounter3h"), | |
| 3204 => Some("hpmcounter4h"), | |
| 3205 => Some("hpmcounter5h"), | |
| 3206 => Some("hpmcounter6h"), | |
| 3207 => Some("hpmcounter7h"), | |
| 3208 => Some("hpmcounter8h"), | |
| 3209 => Some("hpmcounter9h"), | |
| 3210 => Some("hpmcounter10h"), | |
| 3211 => Some("hpmcounter11h"), | |
| 3212 => Some("hpmcounter12h"), | |
| 3213 => Some("hpmcounter13h"), | |
| 3214 => Some("hpmcounter14h"), | |
| 3215 => Some("hpmcounter15h"), | |
| 3216 => Some("hpmcounter16h"), | |
| 3217 => Some("hpmcounter17h"), | |
| 3218 => Some("hpmcounter18h"), | |
| 3219 => Some("hpmcounter19h"), | |
| 3220 => Some("hpmcounter20h"), | |
| 3221 => Some("hpmcounter21h"), | |
| 3222 => Some("hpmcounter22h"), | |
| 3223 => Some("hpmcounter23h"), | |
| 3224 => Some("hpmcounter24h"), | |
| 3225 => Some("hpmcounter25h"), | |
| 3226 => Some("hpmcounter26h"), | |
| 3227 => Some("hpmcounter27h"), | |
| 3228 => Some("hpmcounter28h"), | |
| 3229 => Some("hpmcounter29h"), | |
| 3230 => Some("hpmcounter30h"), | |
| 3231 => Some("hpmcounter31h"), | |
| 3602 => Some("hgeip"), | |
| 3857 => Some("mvendorid"), | |
| 3858 => Some("marchid"), | |
| 3859 => Some("mimpid"), | |
| 3860 => Some("mhartid"), | |
| 3861 => Some("mentropy"), | |
| _ => None, | |
| } | |
| } | |
| fn decode_inst_opcode(dec: &mut rv_decode, isa: RvIsa) { | |
| let inst = dec.inst; | |
| let mut op = RvOp::illegal; | |
| match inst >> 0 & 0o3 { | |
| 0 => match inst >> 13 & 0o7 { | |
| 0 => { | |
| op = RvOp::c_addi4spn; | |
| } | |
| 1 => { | |
| op = if isa == RvIsa::Rv128 { | |
| RvOp::c_lq | |
| } else { | |
| RvOp::c_fld | |
| }; | |
| } | |
| 2 => { | |
| op = RvOp::c_lw; | |
| } | |
| 3 => { | |
| op = if isa == RvIsa::Rv32 { | |
| RvOp::c_flw | |
| } else { | |
| RvOp::c_ld | |
| }; | |
| } | |
| 5 => { | |
| op = if isa == RvIsa::Rv128 { | |
| RvOp::c_sq | |
| } else { | |
| RvOp::c_fsd | |
| }; | |
| } | |
| 6 => { | |
| op = RvOp::c_sw; | |
| } | |
| 7 => { | |
| op = if isa == RvIsa::Rv32 { | |
| RvOp::c_fsw | |
| } else { | |
| RvOp::c_sd | |
| }; | |
| } | |
| _ => {} | |
| }, | |
| 1 => match inst >> 13 & 0o7 { | |
| 0 => match inst >> 2 & 0o3777 { | |
| 0 => { | |
| op = RvOp::c_nop; | |
| } | |
| _ => { | |
| op = RvOp::c_addi; | |
| } | |
| }, | |
| 1 => { | |
| op = if isa == RvIsa::Rv32 { | |
| RvOp::c_jal | |
| } else { | |
| RvOp::c_addiw | |
| }; | |
| } | |
| 2 => { | |
| op = RvOp::c_li; | |
| } | |
| 3 => match inst >> 7 & 0o37 { | |
| 2 => { | |
| op = RvOp::c_addi16sp; | |
| } | |
| _ => { | |
| op = RvOp::c_lui; | |
| } | |
| }, | |
| 4 => match inst >> 10 & 0o3 { | |
| 0 => { | |
| op = RvOp::c_srli; | |
| } | |
| 1 => { | |
| op = RvOp::c_srai; | |
| } | |
| 2 => { | |
| op = RvOp::c_andi; | |
| } | |
| 3 => match inst >> 10 & 0o4 as u64 | inst >> 5 & 0o3 as u64 { | |
| 0 => { | |
| op = RvOp::c_sub; | |
| } | |
| 1 => { | |
| op = RvOp::c_xor; | |
| } | |
| 2 => { | |
| op = RvOp::c_or; | |
| } | |
| 3 => { | |
| op = RvOp::c_and; | |
| } | |
| 4 => { | |
| op = RvOp::c_subw; | |
| } | |
| 5 => { | |
| op = RvOp::c_addw; | |
| } | |
| _ => {} | |
| }, | |
| _ => {} | |
| }, | |
| 5 => { | |
| op = RvOp::c_j; | |
| } | |
| 6 => { | |
| op = RvOp::c_beqz; | |
| } | |
| 7 => { | |
| op = RvOp::c_bnez; | |
| } | |
| _ => {} | |
| }, | |
| 2 => match inst >> 13 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::c_slli; | |
| } | |
| 1 => { | |
| op = if isa == RvIsa::Rv128 { | |
| RvOp::c_lqsp | |
| } else { | |
| RvOp::c_fldsp | |
| }; | |
| } | |
| 2 => { | |
| op = RvOp::c_lwsp; | |
| } | |
| 3 => { | |
| op = if isa == RvIsa::Rv32 { | |
| RvOp::c_flwsp | |
| } else { | |
| RvOp::c_ldsp | |
| }; | |
| } | |
| 4 => match inst >> 12 & 0o1 as u64 { | |
| 0 => match inst >> 2 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::c_jr; | |
| } | |
| _ => { | |
| op = RvOp::c_mv; | |
| } | |
| }, | |
| 1 => match inst >> 2 & 0o37 as u64 { | |
| 0 => match inst >> 7 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::c_ebreak; | |
| } | |
| _ => { | |
| op = RvOp::c_jalr; | |
| } | |
| }, | |
| _ => { | |
| op = RvOp::c_add; | |
| } | |
| }, | |
| _ => {} | |
| }, | |
| 5 => { | |
| op = if isa == RvIsa::Rv128 { | |
| RvOp::c_sqsp | |
| } else { | |
| RvOp::c_fsdsp | |
| }; | |
| } | |
| 6 => { | |
| op = RvOp::c_swsp; | |
| } | |
| 7 => { | |
| op = if isa == RvIsa::Rv32 { | |
| RvOp::c_fswsp | |
| } else { | |
| RvOp::c_sdsp | |
| }; | |
| } | |
| _ => {} | |
| }, | |
| 3 => match inst >> 2 & 0o37 as u64 { | |
| 0 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::lb; | |
| } | |
| 1 => { | |
| op = RvOp::lh; | |
| } | |
| 2 => { | |
| op = RvOp::lw; | |
| } | |
| 3 => { | |
| op = RvOp::ld; | |
| } | |
| 4 => { | |
| op = RvOp::lbu; | |
| } | |
| 5 => { | |
| op = RvOp::lhu; | |
| } | |
| 6 => { | |
| op = RvOp::lwu; | |
| } | |
| 7 => { | |
| op = RvOp::ldu; | |
| } | |
| _ => {} | |
| }, | |
| 1 => match inst >> 12 & 0o7 as u64 { | |
| 2 => { | |
| op = RvOp::flw; | |
| } | |
| 3 => { | |
| op = RvOp::fld; | |
| } | |
| 4 => { | |
| op = RvOp::flq; | |
| } | |
| _ => {} | |
| }, | |
| 3 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fence; | |
| } | |
| 1 => { | |
| op = RvOp::fence_i; | |
| } | |
| 2 => { | |
| op = RvOp::lq; | |
| } | |
| _ => {} | |
| }, | |
| 4 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::addi; | |
| } | |
| 1 => match inst >> 27 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::slli; | |
| } | |
| _ => {} | |
| }, | |
| 2 => { | |
| op = RvOp::slti; | |
| } | |
| 3 => { | |
| op = RvOp::sltiu; | |
| } | |
| 4 => { | |
| op = RvOp::xori; | |
| } | |
| 5 => match inst >> 27 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::srli; | |
| } | |
| 8 => { | |
| op = RvOp::srai; | |
| } | |
| _ => {} | |
| }, | |
| 6 => { | |
| op = RvOp::ori; | |
| } | |
| 7 => { | |
| op = RvOp::andi; | |
| } | |
| _ => {} | |
| }, | |
| 5 => { | |
| op = RvOp::auipc; | |
| } | |
| 6 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::addiw; | |
| } | |
| 1 => match inst >> 25 & 0o177 as u64 { | |
| 0 => { | |
| op = RvOp::slliw; | |
| } | |
| _ => {} | |
| }, | |
| 5 => match inst >> 25 & 0o177 as u64 { | |
| 0 => { | |
| op = RvOp::srliw; | |
| } | |
| 32 => { | |
| op = RvOp::sraiw; | |
| } | |
| _ => {} | |
| }, | |
| _ => {} | |
| }, | |
| 8 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::sb; | |
| } | |
| 1 => { | |
| op = RvOp::sh; | |
| } | |
| 2 => { | |
| op = RvOp::sw; | |
| } | |
| 3 => { | |
| op = RvOp::sd; | |
| } | |
| 4 => { | |
| op = RvOp::sq; | |
| } | |
| _ => {} | |
| }, | |
| 9 => match inst >> 12 & 0o7 as u64 { | |
| 2 => { | |
| op = RvOp::fsw; | |
| } | |
| 3 => { | |
| op = RvOp::fsd; | |
| } | |
| 4 => { | |
| op = RvOp::fsq; | |
| } | |
| _ => {} | |
| }, | |
| 11 => match inst >> 24 & 0o370 as u64 | inst >> 12 & 0o7 as u64 { | |
| 2 => { | |
| op = RvOp::amoadd_w; | |
| } | |
| 3 => { | |
| op = RvOp::amoadd_d; | |
| } | |
| 4 => { | |
| op = RvOp::amoadd_q; | |
| } | |
| 10 => { | |
| op = RvOp::amoswap_w; | |
| } | |
| 11 => { | |
| op = RvOp::amoswap_d; | |
| } | |
| 12 => { | |
| op = RvOp::amoswap_q; | |
| } | |
| 18 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::lr_w; | |
| } | |
| _ => {} | |
| }, | |
| 19 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::lr_d; | |
| } | |
| _ => {} | |
| }, | |
| 20 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::lr_q; | |
| } | |
| _ => {} | |
| }, | |
| 26 => { | |
| op = RvOp::sc_w; | |
| } | |
| 27 => { | |
| op = RvOp::sc_d; | |
| } | |
| 28 => { | |
| op = RvOp::sc_q; | |
| } | |
| 34 => { | |
| op = RvOp::amoxor_w; | |
| } | |
| 35 => { | |
| op = RvOp::amoxor_d; | |
| } | |
| 36 => { | |
| op = RvOp::amoxor_q; | |
| } | |
| 66 => { | |
| op = RvOp::amoor_w; | |
| } | |
| 67 => { | |
| op = RvOp::amoor_d; | |
| } | |
| 68 => { | |
| op = RvOp::amoor_q; | |
| } | |
| 98 => { | |
| op = RvOp::amoand_w; | |
| } | |
| 99 => { | |
| op = RvOp::amoand_d; | |
| } | |
| 100 => { | |
| op = RvOp::amoand_q; | |
| } | |
| 130 => { | |
| op = RvOp::amomin_w; | |
| } | |
| 131 => { | |
| op = RvOp::amomin_d; | |
| } | |
| 132 => { | |
| op = RvOp::amomin_q; | |
| } | |
| 162 => { | |
| op = RvOp::amomax_w; | |
| } | |
| 163 => { | |
| op = RvOp::amomax_d; | |
| } | |
| 164 => { | |
| op = RvOp::amomax_q; | |
| } | |
| 194 => { | |
| op = RvOp::amominu_w; | |
| } | |
| 195 => { | |
| op = RvOp::amominu_d; | |
| } | |
| 196 => { | |
| op = RvOp::amominu_q; | |
| } | |
| 226 => { | |
| op = RvOp::amomaxu_w; | |
| } | |
| 227 => { | |
| op = RvOp::amomaxu_d; | |
| } | |
| 228 => { | |
| op = RvOp::amomaxu_q; | |
| } | |
| _ => {} | |
| }, | |
| 12 => match inst >> 22 & 0o1770 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::add; | |
| } | |
| 1 => { | |
| op = RvOp::sll; | |
| } | |
| 2 => { | |
| op = RvOp::slt; | |
| } | |
| 3 => { | |
| op = RvOp::sltu; | |
| } | |
| 4 => { | |
| op = RvOp::xor; | |
| } | |
| 5 => { | |
| op = RvOp::srl; | |
| } | |
| 6 => { | |
| op = RvOp::or; | |
| } | |
| 7 => { | |
| op = RvOp::and; | |
| } | |
| 8 => { | |
| op = RvOp::mul; | |
| } | |
| 9 => { | |
| op = RvOp::mulh; | |
| } | |
| 10 => { | |
| op = RvOp::mulhsu; | |
| } | |
| 11 => { | |
| op = RvOp::mulhu; | |
| } | |
| 12 => { | |
| op = RvOp::div; | |
| } | |
| 13 => { | |
| op = RvOp::divu; | |
| } | |
| 14 => { | |
| op = RvOp::rem; | |
| } | |
| 15 => { | |
| op = RvOp::remu; | |
| } | |
| 256 => { | |
| op = RvOp::sub; | |
| } | |
| 261 => { | |
| op = RvOp::sra; | |
| } | |
| _ => {} | |
| }, | |
| 13 => { | |
| op = RvOp::lui; | |
| } | |
| 14 => match inst >> 22 & 0o1770 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::addw; | |
| } | |
| 1 => { | |
| op = RvOp::sllw; | |
| } | |
| 5 => { | |
| op = RvOp::srlw; | |
| } | |
| 8 => { | |
| op = RvOp::mulw; | |
| } | |
| 12 => { | |
| op = RvOp::divw; | |
| } | |
| 13 => { | |
| op = RvOp::divuw; | |
| } | |
| 14 => { | |
| op = RvOp::remw; | |
| } | |
| 15 => { | |
| op = RvOp::remuw; | |
| } | |
| 256 => { | |
| op = RvOp::subw; | |
| } | |
| 261 => { | |
| op = RvOp::sraw; | |
| } | |
| _ => {} | |
| }, | |
| 16 => match inst >> 25 & 0o3 as u64 { | |
| 0 => { | |
| op = RvOp::fmadd_s; | |
| } | |
| 1 => { | |
| op = RvOp::fmadd_d; | |
| } | |
| 3 => { | |
| op = RvOp::fmadd_q; | |
| } | |
| _ => {} | |
| }, | |
| 17 => match inst >> 25 & 0o3 as u64 { | |
| 0 => { | |
| op = RvOp::fmsub_s; | |
| } | |
| 1 => { | |
| op = RvOp::fmsub_d; | |
| } | |
| 3 => { | |
| op = RvOp::fmsub_q; | |
| } | |
| _ => {} | |
| }, | |
| 18 => match inst >> 25 & 0o3 as u64 { | |
| 0 => { | |
| op = RvOp::fnmsub_s; | |
| } | |
| 1 => { | |
| op = RvOp::fnmsub_d; | |
| } | |
| 3 => { | |
| op = RvOp::fnmsub_q; | |
| } | |
| _ => {} | |
| }, | |
| 19 => match inst >> 25 & 0o3 as u64 { | |
| 0 => { | |
| op = RvOp::fnmadd_s; | |
| } | |
| 1 => { | |
| op = RvOp::fnmadd_d; | |
| } | |
| 3 => { | |
| op = RvOp::fnmadd_q; | |
| } | |
| _ => {} | |
| }, | |
| 20 => match inst >> 25 & 0o177 as u64 { | |
| 0 => { | |
| op = RvOp::fadd_s; | |
| } | |
| 1 => { | |
| op = RvOp::fadd_d; | |
| } | |
| 3 => { | |
| op = RvOp::fadd_q; | |
| } | |
| 4 => { | |
| op = RvOp::fsub_s; | |
| } | |
| 5 => { | |
| op = RvOp::fsub_d; | |
| } | |
| 7 => { | |
| op = RvOp::fsub_q; | |
| } | |
| 8 => { | |
| op = RvOp::fmul_s; | |
| } | |
| 9 => { | |
| op = RvOp::fmul_d; | |
| } | |
| 11 => { | |
| op = RvOp::fmul_q; | |
| } | |
| 12 => { | |
| op = RvOp::fdiv_s; | |
| } | |
| 13 => { | |
| op = RvOp::fdiv_d; | |
| } | |
| 15 => { | |
| op = RvOp::fdiv_q; | |
| } | |
| 16 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fsgnj_s; | |
| } | |
| 1 => { | |
| op = RvOp::fsgnjn_s; | |
| } | |
| 2 => { | |
| op = RvOp::fsgnjx_s; | |
| } | |
| _ => {} | |
| }, | |
| 17 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fsgnj_d; | |
| } | |
| 1 => { | |
| op = RvOp::fsgnjn_d; | |
| } | |
| 2 => { | |
| op = RvOp::fsgnjx_d; | |
| } | |
| _ => {} | |
| }, | |
| 19 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fsgnj_q; | |
| } | |
| 1 => { | |
| op = RvOp::fsgnjn_q; | |
| } | |
| 2 => { | |
| op = RvOp::fsgnjx_q; | |
| } | |
| _ => {} | |
| }, | |
| 20 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmin_s; | |
| } | |
| 1 => { | |
| op = RvOp::fmax_s; | |
| } | |
| _ => {} | |
| }, | |
| 21 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmin_d; | |
| } | |
| 1 => { | |
| op = RvOp::fmax_d; | |
| } | |
| _ => {} | |
| }, | |
| 23 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmin_q; | |
| } | |
| 1 => { | |
| op = RvOp::fmax_q; | |
| } | |
| _ => {} | |
| }, | |
| 32 => match inst >> 20 & 0o37 as u64 { | |
| 1 => { | |
| op = RvOp::fcvt_s_d; | |
| } | |
| 3 => { | |
| op = RvOp::fcvt_s_q; | |
| } | |
| _ => {} | |
| }, | |
| 33 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fcvt_d_s; | |
| } | |
| 3 => { | |
| op = RvOp::fcvt_d_q; | |
| } | |
| _ => {} | |
| }, | |
| 35 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fcvt_q_s; | |
| } | |
| 1 => { | |
| op = RvOp::fcvt_q_d; | |
| } | |
| _ => {} | |
| }, | |
| 44 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fsqrt_s; | |
| } | |
| _ => {} | |
| }, | |
| 45 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fsqrt_d; | |
| } | |
| _ => {} | |
| }, | |
| 47 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fsqrt_q; | |
| } | |
| _ => {} | |
| }, | |
| 80 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fle_s; | |
| } | |
| 1 => { | |
| op = RvOp::flt_s; | |
| } | |
| 2 => { | |
| op = RvOp::feq_s; | |
| } | |
| _ => {} | |
| }, | |
| 81 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fle_d; | |
| } | |
| 1 => { | |
| op = RvOp::flt_d; | |
| } | |
| 2 => { | |
| op = RvOp::feq_d; | |
| } | |
| _ => {} | |
| }, | |
| 83 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fle_q; | |
| } | |
| 1 => { | |
| op = RvOp::flt_q; | |
| } | |
| 2 => { | |
| op = RvOp::feq_q; | |
| } | |
| _ => {} | |
| }, | |
| 96 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fcvt_w_s; | |
| } | |
| 1 => { | |
| op = RvOp::fcvt_wu_s; | |
| } | |
| 2 => { | |
| op = RvOp::fcvt_l_s; | |
| } | |
| 3 => { | |
| op = RvOp::fcvt_lu_s; | |
| } | |
| _ => {} | |
| }, | |
| 97 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fcvt_w_d; | |
| } | |
| 1 => { | |
| op = RvOp::fcvt_wu_d; | |
| } | |
| 2 => { | |
| op = RvOp::fcvt_l_d; | |
| } | |
| 3 => { | |
| op = RvOp::fcvt_lu_d; | |
| } | |
| _ => {} | |
| }, | |
| 99 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fcvt_w_q; | |
| } | |
| 1 => { | |
| op = RvOp::fcvt_wu_q; | |
| } | |
| 2 => { | |
| op = RvOp::fcvt_l_q; | |
| } | |
| 3 => { | |
| op = RvOp::fcvt_lu_q; | |
| } | |
| _ => {} | |
| }, | |
| 104 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fcvt_s_w; | |
| } | |
| 1 => { | |
| op = RvOp::fcvt_s_wu; | |
| } | |
| 2 => { | |
| op = RvOp::fcvt_s_l; | |
| } | |
| 3 => { | |
| op = RvOp::fcvt_s_lu; | |
| } | |
| _ => {} | |
| }, | |
| 105 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fcvt_d_w; | |
| } | |
| 1 => { | |
| op = RvOp::fcvt_d_wu; | |
| } | |
| 2 => { | |
| op = RvOp::fcvt_d_l; | |
| } | |
| 3 => { | |
| op = RvOp::fcvt_d_lu; | |
| } | |
| _ => {} | |
| }, | |
| 107 => match inst >> 20 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::fcvt_q_w; | |
| } | |
| 1 => { | |
| op = RvOp::fcvt_q_wu; | |
| } | |
| 2 => { | |
| op = RvOp::fcvt_q_l; | |
| } | |
| 3 => { | |
| op = RvOp::fcvt_q_lu; | |
| } | |
| _ => {} | |
| }, | |
| 112 => match inst >> 17 & 0o370 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmv_x_s; | |
| } | |
| 1 => { | |
| op = RvOp::fclass_s; | |
| } | |
| _ => {} | |
| }, | |
| 113 => match inst >> 17 & 0o370 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmv_x_d; | |
| } | |
| 1 => { | |
| op = RvOp::fclass_d; | |
| } | |
| _ => {} | |
| }, | |
| 115 => match inst >> 17 & 0o370 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmv_x_q; | |
| } | |
| 1 => { | |
| op = RvOp::fclass_q; | |
| } | |
| _ => {} | |
| }, | |
| 120 => match inst >> 17 & 0o370 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmv_s_x; | |
| } | |
| _ => {} | |
| }, | |
| 121 => match inst >> 17 & 0o370 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmv_d_x; | |
| } | |
| _ => {} | |
| }, | |
| 123 => match inst >> 17 & 0o370 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::fmv_q_x; | |
| } | |
| _ => {} | |
| }, | |
| _ => {} | |
| }, | |
| 22 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::addid; | |
| } | |
| 1 => match inst >> 26 & 0o77 as u64 { | |
| 0 => { | |
| op = RvOp::sllid; | |
| } | |
| _ => {} | |
| }, | |
| 5 => match inst >> 26 & 0o77 as u64 { | |
| 0 => { | |
| op = RvOp::srlid; | |
| } | |
| 16 => { | |
| op = RvOp::sraid; | |
| } | |
| _ => {} | |
| }, | |
| _ => {} | |
| }, | |
| 24 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::beq; | |
| } | |
| 1 => { | |
| op = RvOp::bne; | |
| } | |
| 4 => { | |
| op = RvOp::blt; | |
| } | |
| 5 => { | |
| op = RvOp::bge; | |
| } | |
| 6 => { | |
| op = RvOp::bltu; | |
| } | |
| 7 => { | |
| op = RvOp::bgeu; | |
| } | |
| _ => {} | |
| }, | |
| 25 => match inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::jalr; | |
| } | |
| _ => {} | |
| }, | |
| 27 => { | |
| op = RvOp::jal; | |
| } | |
| 28 => match inst >> 12 & 0o7 as u64 { | |
| 0 => match inst >> 20 & 0o7740 as u64 | inst >> 7 & 0o37 as u64 { | |
| 0 => match inst >> 15 & 0o1777 as u64 { | |
| 0 => { | |
| op = RvOp::ecall; | |
| } | |
| 32 => { | |
| op = RvOp::ebreak; | |
| } | |
| 64 => { | |
| op = RvOp::uret; | |
| } | |
| _ => {} | |
| }, | |
| 256 => match inst >> 20 & 0o37 as u64 { | |
| 2 => match inst >> 15 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::sret; | |
| } | |
| _ => {} | |
| }, | |
| 4 => { | |
| op = RvOp::sfence_vm; | |
| } | |
| 5 => match inst >> 15 & 0o37 as u64 { | |
| 0 => { | |
| op = RvOp::wfi; | |
| } | |
| _ => {} | |
| }, | |
| _ => {} | |
| }, | |
| 288 => { | |
| op = RvOp::sfence_vma; | |
| } | |
| 512 => match inst >> 15 & 0o1777 as u64 { | |
| 64 => { | |
| op = RvOp::hret; | |
| } | |
| _ => {} | |
| }, | |
| 768 => match inst >> 15 & 0o1777 as u64 { | |
| 64 => { | |
| op = RvOp::mret; | |
| } | |
| _ => {} | |
| }, | |
| 1952 => match inst >> 15 & 0o1777 as u64 { | |
| 576 => { | |
| op = RvOp::dret; | |
| } | |
| _ => {} | |
| }, | |
| _ => {} | |
| }, | |
| 1 => { | |
| op = RvOp::csrrw; | |
| } | |
| 2 => { | |
| op = RvOp::csrrs; | |
| } | |
| 3 => { | |
| op = RvOp::csrrc; | |
| } | |
| 5 => { | |
| op = RvOp::csrrwi; | |
| } | |
| 6 => { | |
| op = RvOp::csrrsi; | |
| } | |
| 7 => { | |
| op = RvOp::csrrci; | |
| } | |
| _ => {} | |
| }, | |
| 30 => match inst >> 22 & 0o1770 as u64 | inst >> 12 & 0o7 as u64 { | |
| 0 => { | |
| op = RvOp::addd; | |
| } | |
| 1 => { | |
| op = RvOp::slld; | |
| } | |
| 5 => { | |
| op = RvOp::srld; | |
| } | |
| 8 => { | |
| op = RvOp::muld; | |
| } | |
| 12 => { | |
| op = RvOp::divd; | |
| } | |
| 13 => { | |
| op = RvOp::divud; | |
| } | |
| 14 => { | |
| op = RvOp::remd; | |
| } | |
| 15 => { | |
| op = RvOp::remud; | |
| } | |
| 256 => { | |
| op = RvOp::subd; | |
| } | |
| 261 => { | |
| op = RvOp::srad; | |
| } | |
| _ => {} | |
| }, | |
| _ => {} | |
| }, | |
| _ => {} | |
| } | |
| dec.op = op; | |
| } | |
| fn operand_rd(inst: rv_inst) -> u8 { | |
| (inst << 52 >> 59) as u8 | |
| } | |
| fn operand_rs1(inst: rv_inst) -> u8 { | |
| (inst << 44 >> 59) as u8 | |
| } | |
| fn operand_rs2(inst: rv_inst) -> u8 { | |
| (inst << 39 >> 59) as u8 | |
| } | |
| fn operand_rs3(inst: rv_inst) -> u8 { | |
| (inst << 32 >> 59) as u8 | |
| } | |
| fn operand_aq(inst: rv_inst) -> u8 { | |
| (inst << 37 >> 63) as u8 | |
| } | |
| fn operand_rl(inst: rv_inst) -> u8 { | |
| (inst << 38 >> 63) as u8 | |
| } | |
| fn operand_pred(inst: rv_inst) -> u8 { | |
| (inst << 36 >> 60) as u8 | |
| } | |
| fn operand_succ(inst: rv_inst) -> u8 { | |
| (inst << 40 >> 60) as u8 | |
| } | |
| fn operand_rm(inst: rv_inst) -> u8 { | |
| (inst << 49 >> 61) as u8 | |
| } | |
| fn operand_shamt5(inst: rv_inst) -> i32 { | |
| (inst << 39 >> 59) as i32 | |
| } | |
| fn operand_shamt6(inst: rv_inst) -> i32 { | |
| (inst << 38 >> 58) as i32 | |
| } | |
| fn operand_shamt7(inst: rv_inst) -> i32 { | |
| (inst << 37 >> 57) as i32 | |
| } | |
| fn operand_crdq(inst: rv_inst) -> u8 { | |
| (inst << 59 >> 61) as u8 | |
| } | |
| fn operand_crs1q(inst: rv_inst) -> u8 { | |
| (inst << 54 >> 61) as u8 | |
| } | |
| fn operand_crs1rdq(inst: rv_inst) -> u8 { | |
| (inst << 54 >> 61) as u8 | |
| } | |
| fn operand_crs2q(inst: rv_inst) -> u8 { | |
| (inst << 59 >> 61) as u8 | |
| } | |
| fn operand_crd(inst: rv_inst) -> u8 { | |
| (inst << 52 >> 59) as u8 | |
| } | |
| fn operand_crs1(inst: rv_inst) -> u8 { | |
| (inst << 52 >> 59) as u8 | |
| } | |
| fn operand_crs1rd(inst: rv_inst) -> u8 { | |
| (inst << 52 >> 59) as u8 | |
| } | |
| fn operand_crs2(inst: rv_inst) -> u8 { | |
| (inst << 57 >> 59) as u8 | |
| } | |
| fn operand_cimmsh5(inst: rv_inst) -> i32 { | |
| (inst << 57 >> 59) as i32 | |
| } | |
| fn operand_csr12(inst: rv_inst) -> i32 { | |
| (inst << 32 >> 52) as i32 | |
| } | |
| fn operand_imm12(inst: rv_inst) -> i32 { | |
| ((inst as i64) << 32 >> 52) as i32 | |
| } | |
| fn operand_imm20(inst: rv_inst) -> i32 { | |
| (((inst as i64) << 32 >> 44) << 12) as i32 | |
| } | |
| fn operand_jimm20(inst: rv_inst) -> i32 { | |
| ((((inst as i64) << 32 >> 63) << 20) as u64 | |
| | (inst << 33 >> 54) << 1 | |
| | (inst << 43 >> 63) << 11 | |
| | (inst << 44 >> 56) << 12) as i32 | |
| } | |
| fn operand_simm12(inst: rv_inst) -> i32 { | |
| ((((inst as i64) << 32 >> 57) << 5) as u64 | inst << 52 >> 59) as i32 | |
| } | |
| fn operand_sbimm12(inst: rv_inst) -> i32 { | |
| ((((inst as i64) << 32 >> 63) << 12) as u64 | |
| | (inst << 33 >> 58) << 5 | |
| | (inst << 52 >> 60) << 1 | |
| | (inst << 56 >> 63) << 11) as i32 | |
| } | |
| fn operand_cimmsh6(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 63) << 5 | inst << 57 >> 59) as i32 | |
| } | |
| fn operand_cimmi(inst: rv_inst) -> i32 { | |
| ((((inst as i64) << 51 >> 63) << 5) as u64 | inst << 57 >> 59) as i32 | |
| } | |
| fn operand_cimmui(inst: rv_inst) -> i32 { | |
| ((((inst as i64) << 51 >> 63) << 17) as u64 | (inst << 57 >> 59) << 12) as i32 | |
| } | |
| fn operand_cimmlwsp(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 63) << 5 | (inst << 57 >> 61) << 2 | (inst << 60 >> 62) << 6) as i32 | |
| } | |
| fn operand_cimmldsp(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 63) << 5 | (inst << 57 >> 62) << 3 | (inst << 59 >> 61) << 6) as i32 | |
| } | |
| fn operand_cimmlqsp(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 63) << 5 | (inst << 57 >> 63) << 4 | (inst << 58 >> 60) << 6) as i32 | |
| } | |
| fn operand_cimm16sp(inst: rv_inst) -> i32 { | |
| ((((inst as i64) << 51 >> 63) << 9) as u64 | |
| | (inst << 57 >> 63) << 4 | |
| | (inst << 58 >> 63) << 6 | |
| | (inst << 59 >> 62) << 7 | |
| | (inst << 61 >> 63) << 5) as i32 | |
| } | |
| fn operand_cimmj(inst: rv_inst) -> i32 { | |
| ((((inst as i64) << 51 >> 63) << 11) as u64 | |
| | (inst << 52 >> 63) << 4 | |
| | (inst << 53 >> 62) << 8 | |
| | (inst << 55 >> 63) << 10 | |
| | (inst << 56 >> 63) << 6 | |
| | (inst << 57 >> 63) << 7 | |
| | (inst << 58 >> 61) << 1 | |
| | (inst << 61 >> 63) << 5) as i32 | |
| } | |
| fn operand_cimmb(inst: rv_inst) -> i32 { | |
| ((((inst as i64) << 51 >> 63) << 8) as u64 | |
| | (inst << 52 >> 62) << 3 | |
| | (inst << 57 >> 62) << 6 | |
| | (inst << 59 >> 62) << 1 | |
| | (inst << 61 >> 63) << 5) as i32 | |
| } | |
| fn operand_cimmswsp(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 60) << 2 | (inst << 55 >> 62) << 6) as i32 | |
| } | |
| fn operand_cimmsdsp(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 61) << 3 | (inst << 54 >> 61) << 6) as i32 | |
| } | |
| fn operand_cimmsqsp(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 62) << 4 | (inst << 53 >> 60) << 6) as i32 | |
| } | |
| fn operand_cimm4spn(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 62) << 4 | |
| | (inst << 53 >> 60) << 6 | |
| | (inst << 57 >> 63) << 2 | |
| | (inst << 58 >> 63) << 3) as i32 | |
| } | |
| fn operand_cimmw(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 61) << 3 | (inst << 57 >> 63) << 2 | (inst << 58 >> 63) << 6) as i32 | |
| } | |
| fn operand_cimmd(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 61) << 3 | (inst << 57 >> 62) << 6) as i32 | |
| } | |
| fn operand_cimmq(inst: rv_inst) -> i32 { | |
| ((inst << 51 >> 62) << 4 | (inst << 53 >> 63) << 8 | (inst << 57 >> 62) << 6) as i32 | |
| } | |
| fn decode_inst_operands(dec: &mut rv_decode) { | |
| let inst = dec.inst; | |
| dec.codec = opcode_data[dec.op as usize].codec; | |
| match dec.codec { | |
| RV_CODEC_NONE => { | |
| dec.rs2 = rv_ireg_zero; | |
| dec.rs1 = dec.rs2; | |
| dec.rd = dec.rs1; | |
| dec.imm = 0; | |
| } | |
| RV_CODEC_U => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.rs1 = dec.rs2; | |
| dec.imm = operand_imm20(inst); | |
| } | |
| 3 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.rs1 = dec.rs2; | |
| dec.imm = operand_jimm20(inst); | |
| } | |
| 4 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_imm12(inst); | |
| } | |
| 5 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_shamt5(inst); | |
| } | |
| 6 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_shamt6(inst); | |
| } | |
| 7 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_shamt7(inst); | |
| } | |
| 8 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_csr12(inst); | |
| } | |
| 9 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = operand_rs2(inst); | |
| dec.imm = operand_simm12(inst); | |
| } | |
| 10 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = operand_rs2(inst); | |
| dec.imm = operand_sbimm12(inst); | |
| } | |
| 11 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = operand_rs2(inst); | |
| dec.imm = 0; | |
| } | |
| 12 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = operand_rs2(inst); | |
| dec.rm = operand_rm(inst); | |
| dec.imm = 0; | |
| } | |
| 13 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = operand_rs2(inst); | |
| dec.rs3 = operand_rs3(inst); | |
| dec.imm = 0; | |
| dec.rm = operand_rm(inst); | |
| } | |
| 14 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = operand_rs2(inst); | |
| dec.imm = 0; | |
| dec.aq = operand_aq(inst); | |
| dec.rl = operand_rl(inst); | |
| } | |
| 15 => { | |
| dec.rd = operand_rd(inst); | |
| dec.rs1 = operand_rs1(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = 0; | |
| dec.aq = operand_aq(inst); | |
| dec.rl = operand_rl(inst); | |
| } | |
| 16 => { | |
| dec.rs2 = rv_ireg_zero; | |
| dec.rs1 = dec.rs2; | |
| dec.rd = dec.rs1; | |
| dec.pred = operand_pred(inst); | |
| dec.succ = operand_succ(inst); | |
| dec.imm = 0; | |
| } | |
| 17 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = operand_crs1q(inst).wrapping_add(8); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmb(inst); | |
| } | |
| 18 => { | |
| dec.rs1 = operand_crs1rdq(inst).wrapping_add(8); | |
| dec.rd = dec.rs1; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmi(inst); | |
| } | |
| 19 => { | |
| dec.rs1 = operand_crs1rdq(inst).wrapping_add(8); | |
| dec.rd = dec.rs1; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmsh5(inst); | |
| } | |
| 20 => { | |
| dec.rs1 = operand_crs1rdq(inst).wrapping_add(8); | |
| dec.rd = dec.rs1; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmsh6(inst); | |
| } | |
| 21 => { | |
| dec.rs1 = operand_crs1rd(inst); | |
| dec.rd = dec.rs1; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmi(inst); | |
| } | |
| 22 => { | |
| dec.rs1 = operand_crs1rd(inst); | |
| dec.rd = dec.rs1; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmsh5(inst); | |
| } | |
| 23 => { | |
| dec.rs1 = operand_crs1rd(inst); | |
| dec.rd = dec.rs1; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmsh6(inst); | |
| } | |
| 24 => { | |
| dec.rd = rv_ireg_sp; | |
| dec.rs1 = rv_ireg_sp; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimm16sp(inst); | |
| } | |
| 25 => { | |
| dec.rd = operand_crd(inst); | |
| dec.rs1 = rv_ireg_sp; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmlwsp(inst); | |
| } | |
| 26 => { | |
| dec.rd = operand_crd(inst); | |
| dec.rs1 = rv_ireg_sp; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmldsp(inst); | |
| } | |
| 27 => { | |
| dec.rd = operand_crd(inst); | |
| dec.rs1 = rv_ireg_sp; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmlqsp(inst); | |
| } | |
| 28 => { | |
| dec.rd = operand_crd(inst); | |
| dec.rs1 = rv_ireg_zero; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmi(inst); | |
| } | |
| 29 => { | |
| dec.rd = operand_crd(inst); | |
| dec.rs1 = rv_ireg_zero; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmui(inst); | |
| } | |
| 30 => { | |
| dec.rs2 = rv_ireg_zero; | |
| dec.rs1 = dec.rs2; | |
| dec.rd = dec.rs1; | |
| dec.imm = 0; | |
| } | |
| 31 => { | |
| dec.rd = operand_crdq(inst).wrapping_add(8); | |
| dec.rs1 = rv_ireg_sp; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimm4spn(inst); | |
| } | |
| 32 => { | |
| dec.rs2 = rv_ireg_zero; | |
| dec.rs1 = dec.rs2; | |
| dec.rd = dec.rs1; | |
| dec.imm = operand_cimmj(inst); | |
| } | |
| 33 => { | |
| dec.rd = rv_ireg_ra; | |
| dec.rs2 = rv_ireg_zero; | |
| dec.rs1 = dec.rs2; | |
| dec.imm = operand_cimmj(inst); | |
| } | |
| 34 => { | |
| dec.rd = operand_crdq(inst).wrapping_add(8); | |
| dec.rs1 = operand_crs1q(inst).wrapping_add(8); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmw(inst); | |
| } | |
| 35 => { | |
| dec.rd = operand_crdq(inst).wrapping_add(8); | |
| dec.rs1 = operand_crs1q(inst).wrapping_add(8); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmd(inst); | |
| } | |
| 36 => { | |
| dec.rd = operand_crdq(inst).wrapping_add(8); | |
| dec.rs1 = operand_crs1q(inst).wrapping_add(8); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = operand_cimmq(inst); | |
| } | |
| 37 => { | |
| dec.rs1 = operand_crs1rd(inst); | |
| dec.rd = dec.rs1; | |
| dec.rs2 = operand_crs2(inst); | |
| dec.imm = 0; | |
| } | |
| 38 => { | |
| dec.rd = operand_crd(inst); | |
| dec.rs1 = operand_crs2(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = 0; | |
| } | |
| 39 => { | |
| dec.rd = rv_ireg_ra; | |
| dec.rs1 = operand_crs1(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = 0; | |
| } | |
| 40 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = operand_crs1(inst); | |
| dec.rs2 = rv_ireg_zero; | |
| dec.imm = 0; | |
| } | |
| 41 => { | |
| dec.rs1 = operand_crs1rdq(inst).wrapping_add(8); | |
| dec.rd = dec.rs1; | |
| dec.rs2 = operand_crs2q(inst).wrapping_add(8); | |
| dec.imm = 0; | |
| } | |
| 42 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = (operand_crs1q(inst)).wrapping_add(8); | |
| dec.rs2 = (operand_crs2q(inst)).wrapping_add(8); | |
| dec.imm = operand_cimmw(inst); | |
| } | |
| 43 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = (operand_crs1q(inst)).wrapping_add(8); | |
| dec.rs2 = (operand_crs2q(inst)).wrapping_add(8); | |
| dec.imm = operand_cimmd(inst); | |
| } | |
| 44 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = (operand_crs1q(inst)).wrapping_add(8); | |
| dec.rs2 = (operand_crs2q(inst)).wrapping_add(8); | |
| dec.imm = operand_cimmq(inst); | |
| } | |
| 45 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = rv_ireg_sp; | |
| dec.rs2 = operand_crs2(inst); | |
| dec.imm = operand_cimmswsp(inst); | |
| } | |
| 46 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = rv_ireg_sp; | |
| dec.rs2 = operand_crs2(inst); | |
| dec.imm = operand_cimmsdsp(inst); | |
| } | |
| 47 => { | |
| dec.rd = rv_ireg_zero; | |
| dec.rs1 = rv_ireg_sp; | |
| dec.rs2 = operand_crs2(inst); | |
| dec.imm = operand_cimmsqsp(inst); | |
| } | |
| _ => {} | |
| }; | |
| } | |
| fn decode_inst_decompress(dec: &mut rv_decode, isa: RvIsa) { | |
| let decomp_op = 0; | |
| if let Some(decomp_op) = match isa { | |
| RvIsa::Rv32 => opcode_data[dec.op as usize].decomp_rv32, | |
| RvIsa::Rv64 => opcode_data[dec.op as usize].decomp_rv64, | |
| RvIsa::Rv128 => opcode_data[dec.op as usize].decomp_rv128, | |
| } { | |
| if opcode_data[dec.op as usize].decomp_data == RvCdImmediate::Nz && dec.imm == 0 { | |
| dec.op = RvOp::illegal; | |
| } else { | |
| dec.op = decomp_op; | |
| dec.codec = opcode_data[decomp_op as usize].codec as u8; | |
| } | |
| } | |
| } | |
| fn check_constraints(dec: &rv_decode, constraints: &[rvc_constraint]) -> bool { | |
| let imm = dec.imm; | |
| let rd = dec.rd; | |
| let rs1 = dec.rs1; | |
| let rs2 = dec.rs2; | |
| for c in constraints { | |
| match *c { | |
| rvc_rd_eq_ra => { | |
| if !(rd == 1) { | |
| return false; | |
| } | |
| } | |
| rvc_rd_eq_x0 => { | |
| if rd != 0 { | |
| return false; | |
| } | |
| } | |
| rvc_rs1_eq_x0 => { | |
| if rs1 != 0 { | |
| return false; | |
| } | |
| } | |
| rvc_rs2_eq_x0 => { | |
| if rs2 != 0 { | |
| return false; | |
| } | |
| } | |
| rvc_rs2_eq_rs1 => { | |
| if rs2 != rs1 { | |
| return false; | |
| } | |
| } | |
| rvc_rs1_eq_ra => { | |
| if rs1 != 1 { | |
| return false; | |
| } | |
| } | |
| rvc_imm_eq_zero => { | |
| if imm != 0 { | |
| return false; | |
| } | |
| } | |
| rvc_imm_eq_n1 => { | |
| if imm != -1 { | |
| return false; | |
| } | |
| } | |
| rvc_imm_eq_p1 => { | |
| if imm != 1 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0x001 => { | |
| if imm != 0x1 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0x002 => { | |
| if imm != 0x2 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0x003 => { | |
| if imm != 0x3 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0xc00 => { | |
| if imm != 0xc00 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0xc01 => { | |
| if imm != 0xc01 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0xc02 => { | |
| if imm != 0xc02 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0xc80 => { | |
| if imm != 0xc80 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0xc81 => { | |
| if imm != 0xc81 { | |
| return false; | |
| } | |
| } | |
| rvc_csr_eq_0xc82 => { | |
| if imm != 0xc82 { | |
| return false; | |
| } | |
| } | |
| _ => {} | |
| } | |
| } | |
| return true; | |
| } | |
| fn decode_inst_lift_pseudo(dec: &mut rv_decode) { | |
| for comp_data in opcode_data[dec.op as usize].pseudo { | |
| if check_constraints(dec, comp_data.constraints) { | |
| dec.op = comp_data.op; | |
| dec.codec = opcode_data[dec.op as usize].codec; | |
| return; | |
| } | |
| } | |
| } | |
| fn decode_inst_format(tab: usize, dec: &rv_decode) { | |
| match inst_length(dec.inst) { | |
| 2 => { | |
| print!("{:04x} ", dec.inst & 0xffff); | |
| } | |
| 4 => { | |
| print!("{:08x} ", dec.inst & 0xffff_ffff); | |
| } | |
| 6 => { | |
| print!("{:012x}", dec.inst & 0xffff_ffff_ffff); | |
| } | |
| _ => { | |
| print!("{:016x}", dec.inst); | |
| } | |
| } | |
| for fmt in opcode_data[dec.op as usize].format { | |
| match fmt { | |
| b'O' => { | |
| print!("{}", opcode_data[dec.op as usize].name); | |
| } | |
| b'(' => { | |
| print!("("); | |
| } | |
| b',' => { | |
| print!(","); | |
| } | |
| b')' => { | |
| print!(")"); | |
| } | |
| b'0' => { | |
| print!("{}", RV_IREG_NAME_SYM[dec.rd as usize]); | |
| } | |
| b'1' => { | |
| print!("{}", RV_IREG_NAME_SYM[dec.rs1 as usize]); | |
| } | |
| b'2' => { | |
| print!("{}", (RV_IREG_NAME_SYM[dec.rs2 as usize])); | |
| } | |
| b'3' => { | |
| print!("{}", (RV_FREG_NAME_SYM[dec.rd as usize])); | |
| } | |
| b'4' => { | |
| print!("{}", (RV_FREG_NAME_SYM[dec.rs1 as usize])); | |
| } | |
| b'5' => { | |
| print!("{}", (RV_FREG_NAME_SYM[dec.rs2 as usize])); | |
| } | |
| b'6' => { | |
| print!("{}", (RV_FREG_NAME_SYM[dec.rs3 as usize])); | |
| } | |
| b'7' => { | |
| print!("{}", dec.rs1); | |
| } | |
| b'i' => { | |
| print!("{}", dec.imm); | |
| } | |
| b'o' => { | |
| print!("{}", dec.imm); | |
| print!(" "); | |
| print!("# 0x{:x}", dec.pc.wrapping_add(dec.imm as u64)); | |
| } | |
| b'c' => match csr_name(dec.imm & 0xfff) { | |
| Some(name) => print!("{}", name), | |
| None => print!("{:03x}", dec.imm & 0xfff), | |
| }, | |
| b'r' => match dec.rm { | |
| 0 => { | |
| print!("rne"); | |
| } | |
| 1 => { | |
| print!("rtz"); | |
| } | |
| 2 => { | |
| print!("rdn"); | |
| } | |
| 3 => { | |
| print!("rup"); | |
| } | |
| 4 => { | |
| print!("rmm"); | |
| } | |
| 7 => { | |
| print!("dyn"); | |
| } | |
| _ => { | |
| print!("inv"); | |
| } | |
| }, | |
| b'p' => { | |
| if dec.pred & rv_fence_i != 0 { | |
| print!("i"); | |
| } | |
| if dec.pred & rv_fence_o != 0 { | |
| print!("o"); | |
| } | |
| if dec.pred & rv_fence_r != 0 { | |
| print!("r"); | |
| } | |
| if dec.pred & rv_fence_w != 0 { | |
| print!("w"); | |
| } | |
| } | |
| b's' => { | |
| if dec.succ & rv_fence_i != 0 { | |
| print!("i"); | |
| } | |
| if dec.succ & rv_fence_o != 0 { | |
| print!("o"); | |
| } | |
| if dec.succ & rv_fence_r != 0 { | |
| print!("r"); | |
| } | |
| if dec.succ & rv_fence_w != 0 { | |
| print!("w"); | |
| } | |
| } | |
| b'\t' => { | |
| print!("\t"); | |
| } | |
| b'A' => { | |
| if dec.aq != 0 { | |
| print!(".aq"); | |
| } | |
| } | |
| b'R' => { | |
| if dec.rl != 0 { | |
| print!(".rl"); | |
| } | |
| } | |
| _ => {} | |
| } | |
| } | |
| } | |
| fn inst_length(inst: rv_inst) -> usize { | |
| return (if inst & 0o3 != 0o3 { | |
| 2 | |
| } else if inst & 0o34 != 0o34 { | |
| 4 | |
| } else if inst & 0o77 == 0o37 { | |
| 6 | |
| } else if inst & 0o177 == 0o77 { | |
| 8 | |
| } else { | |
| 0 | |
| }) as usize; | |
| } | |
| pub fn inst_fetch(data: &[u8]) -> (rv_inst, usize) { | |
| let mut inst: rv_inst = (data[1] as rv_inst) << 8 | data[0] as rv_inst; | |
| let length = inst_length(inst); | |
| if length >= 8 { | |
| inst |= (data[7] as rv_inst) << 56 | (data[6] as rv_inst) << 48; | |
| } | |
| if length >= 6 { | |
| inst |= (data[5] as rv_inst) << 40 | (data[4] as rv_inst) << 32; | |
| } | |
| if length >= 4 { | |
| inst |= (data[3] as rv_inst) << 24 | (data[2] as rv_inst) << 16; | |
| } | |
| (inst, length) | |
| } | |
| pub fn disasm_inst(isa: RvIsa, pc: u64, inst: rv_inst) { | |
| let mut dec = rv_decode { | |
| pc, | |
| inst, | |
| imm: 0, | |
| op: RvOp::illegal, | |
| codec: 0, | |
| rd: 0, | |
| rs1: 0, | |
| rs2: 0, | |
| rs3: 0, | |
| rm: 0, | |
| pred: 0, | |
| succ: 0, | |
| aq: 0, | |
| rl: 0, | |
| }; | |
| decode_inst_opcode(&mut dec, isa); | |
| decode_inst_operands(&mut dec); | |
| decode_inst_decompress(&mut dec, isa); | |
| decode_inst_lift_pseudo(&mut dec); | |
| decode_inst_format(32, &dec); | |
| } |
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