xobs

diff --git a/wishbone-tool/src/bridge/uart.rs b/wishbone-tool/src/bridge/uart.rs
index 0ca9c9a..daf9025 100644
--- a/wishbone-tool/src/bridge/uart.rs
+++ b/wishbone-tool/src/bridge/uart.rs
@@ -239,7 +239,9 @@ impl UartBridge {
         // LiteX ignores the bottom two Wishbone bits, so shift it by
         // two when writing the address.
         serial.write_u32::<BigEndian>(addr >> 2)?;
-        Ok(serial.write_u32::<BigEndian>(value)?)
+        serial.write_u32::<BigEndian>(value)?;

xobs

#include <stdio.h>
#include <stdint.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>

int main(int argc, char **argv) {
        int f = open("args.bin", O_RDONLY);
        uint8_t fourcc[4];
        uint32_t val;

xobs

import time
 
import microcontroller
import digitalio
from adafruit_hid.keyboard import Keyboard
from adafruit_hid.keyboard_layout_us import KeyboardLayoutUS
from adafruit_hid.keycode import Keycode
 
# A simple neat keyboard demo in CircuitPython
 

xobs

Щīńδǿωŝ Ĥ℮ℓℓò ƒòґ ßùśĩήėŝś ρгŏνіŝīőπĩńġ щīŀļ йŏτ вë łǻüŋ¢нεð. 
Ðэνįčĕ ïŝ ∆ĀĐ јόïπέð ( ΛÄĐĴ õř ĐЈ++ ): Not Tested 
Ũѕеř ħąѕ ļöģģĕδ ôņ ωιτн ÁДÐ čŗ℮ðěπŧíдŀş: No 
Ẃĩńđŏшѕ Ħęľľσ ƒõґ Ъцşīʼnеšś φőĺíçŷ іś ℮лавℓéđ: Not Tested 
Шīʼnδŏẁŝ Ήεℓłо ƒοѓ Ьϋѕíήèşŝ ρбѕť-ŀŏğóʼn ρřõνìšīŏŋìπĝ ĩş ëηãьļĕδ: Not Tested 
Ŀοсªļ сǿmρџť℮ŕ mĕĕŧѕ Ẅīņđбŵŝ ħęľłõ ƒóг вцѕīиєśş ђâŕðωãŗз ŗ℮qųïřémεňтš: Not Tested 
Ũşея їŝ йбŧ čθήñ℮сτēδ ţб тħě мäċђіŋє νίá Гёmöтë Đêŝкťöρ: Yes 
Ůşêя сёгтΐƒΐçªťė ƒòґ οп φŕêмīşё âцτн φöℓїĉў ĭš ėŋãъŀêð: Not Tested 
Мαćђïйе ΐś ġöνèřñěð вў none рθĺīςў. 
Şёë https://go.microsoft.com/fwlink/?linkid=832647 ƒòŕ mοřе δзţäīŀŝ.

xobs

      # Overall system interface
      self.address = RegStorage(7, resettable=True, description="""Write to update the USB Address.

          When you receive a `SET_ADDRESS` packet from the host, update the address by writing it into
          this field.  Otherwise, the USB controller will ignore all future packets.

          This value will be reset to 0 when the host issues a USB reset.
          """)
####
      # SETUP endpoint Register Interface

xobs

.comment from next-pnr
.device 5k
.io_tile 1 0
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000

xobs

   0x000016dc <+0>:     li      a0,1
   0x000016e0 <+4>:     li      a0,2
   0x000016e4 <+8>:     li      a0,3
   0x000016e8 <+12>:    li      a0,4
   0x000016ec <+16>:    li      a0,5
   0x000016f0 <+20>:    li      a0,6
   0x000016f4 <+24>:    li      a0,7

xobs

fomu@fomu-dev:~/patch-rom $ cat make-multi.sh
#!/bin/sh

icepack -u /home/fomu/top.bin > top.txt
./convert-to-hex.py
icebram random.hex foboot.hex < top.txt > top-patched.txt
icepack -s < top-patched.txt > top-patched.bin
cp multiboot.bin top-multi.bin
cat top-patched.bin >> top-multi.bin
fomu@fomu-dev:~/patch-rom $ cat convert-to-hex.py

xobs

#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on.  lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "icestorm", "yosys"]

# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv

xobs

#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on.  lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "icestorm", "yosys"]

# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv