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| /* | |
| * there were a lot of warnings when decompiling (missing range/reg, unexpected values). | |
| * the header of the dtb says it's version 11. | |
| */ | |
| /dts-v1/; | |
| / { | |
| compatible = "starfive,jh7110"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| model = "StarFive VisionFive V2"; | |
| osc { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x16e3600>; | |
| u-boot,dm-spl; | |
| phandle = <0x08>; | |
| }; | |
| gmac1_rmii_refin { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2faf080>; | |
| u-boot,dm-spl; | |
| phandle = <0x09>; | |
| }; | |
| gmac1_rgmii_rxin { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x7735940>; | |
| phandle = <0x21>; | |
| }; | |
| i2stx_bclk_ext { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0xbb8000>; | |
| phandle = <0x22>; | |
| }; | |
| i2stx_lrck_ext { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2ee00>; | |
| phandle = <0x23>; | |
| }; | |
| i2srx_bclk_ext { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0xbb8000>; | |
| phandle = <0x24>; | |
| }; | |
| i2srx_lrck_ext { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2ee00>; | |
| phandle = <0x25>; | |
| }; | |
| tdm_ext { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2ee0000>; | |
| phandle = <0x26>; | |
| }; | |
| mclk_ext { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2ee0000>; | |
| phandle = <0x27>; | |
| }; | |
| jtag_tck_inner { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2faf080>; | |
| phandle = <0x28>; | |
| }; | |
| bist_apb { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2faf080>; | |
| phandle = <0x29>; | |
| }; | |
| stg_apb { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x30d4000>; | |
| u-boot,dm-spl; | |
| phandle = <0x0a>; | |
| }; | |
| gmac0_rmii_refin { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2faf080>; | |
| u-boot,dm-spl; | |
| phandle = <0x0b>; | |
| }; | |
| gmac0_rgmii_rxin { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x7735940>; | |
| phandle = <0x2a>; | |
| }; | |
| clk_rtc { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x8000>; | |
| phandle = <0x2b>; | |
| }; | |
| hdmitx0_pixelclk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x11b3dc40>; | |
| phandle = <0x0c>; | |
| }; | |
| mipitx_dphy_rxesc { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x989680>; | |
| phandle = <0x0d>; | |
| }; | |
| mipitx_dphy_txbytehs { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x11b3dc40>; | |
| phandle = <0x0e>; | |
| }; | |
| cpus { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| u-boot,dm-spl; | |
| timebase-frequency = "\0=\t"; | |
| phandle = <0x2c>; | |
| cpu@0 { | |
| compatible = "sifive,u74-mc\0riscv"; | |
| reg = <0x00>; | |
| d-cache-block-size = <0x40>; | |
| d-cache-sets = <0x40>; | |
| d-cache-size = <0x2000>; | |
| d-tlb-sets = <0x01>; | |
| d-tlb-size = <0x28>; | |
| device_type = "cpu"; | |
| i-cache-block-size = <0x40>; | |
| i-cache-sets = <0x40>; | |
| i-cache-size = <0x4000>; | |
| i-tlb-sets = <0x01>; | |
| i-tlb-size = <0x28>; | |
| mmu-type = "riscv,sv39"; | |
| next-level-cache = <0x01>; | |
| riscv,isa = "rv64imacu"; | |
| tlb-split; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x2d>; | |
| interrupt-controller { | |
| #interrupt-cells = <0x01>; | |
| compatible = "riscv,cpu-intc"; | |
| interrupt-controller; | |
| u-boot,dm-spl; | |
| phandle = <0x03>; | |
| }; | |
| }; | |
| cpu@1 { | |
| compatible = "sifive,u74-mc\0riscv"; | |
| reg = <0x01>; | |
| d-cache-block-size = <0x40>; | |
| d-cache-sets = <0x40>; | |
| d-cache-size = <0x8000>; | |
| d-tlb-sets = <0x01>; | |
| d-tlb-size = <0x28>; | |
| device_type = "cpu"; | |
| i-cache-block-size = <0x40>; | |
| i-cache-sets = <0x40>; | |
| i-cache-size = <0x8000>; | |
| i-tlb-sets = <0x01>; | |
| i-tlb-size = <0x28>; | |
| mmu-type = "riscv,sv39"; | |
| next-level-cache = <0x01>; | |
| riscv,isa = "rv64imafdcbsux"; | |
| tlb-split; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x2e>; | |
| interrupt-controller { | |
| #interrupt-cells = <0x01>; | |
| compatible = "riscv,cpu-intc"; | |
| interrupt-controller; | |
| u-boot,dm-spl; | |
| phandle = <0x04>; | |
| }; | |
| }; | |
| cpu@2 { | |
| compatible = "sifive,u74-mc\0riscv"; | |
| reg = <0x02>; | |
| d-cache-block-size = <0x40>; | |
| d-cache-sets = <0x40>; | |
| d-cache-size = <0x8000>; | |
| d-tlb-sets = <0x01>; | |
| d-tlb-size = <0x28>; | |
| device_type = "cpu"; | |
| i-cache-block-size = <0x40>; | |
| i-cache-sets = <0x40>; | |
| i-cache-size = <0x8000>; | |
| i-tlb-sets = <0x01>; | |
| i-tlb-size = <0x28>; | |
| mmu-type = "riscv,sv39"; | |
| next-level-cache = <0x01>; | |
| riscv,isa = "rv64imafdcbsux"; | |
| tlb-split; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x2f>; | |
| interrupt-controller { | |
| #interrupt-cells = <0x01>; | |
| compatible = "riscv,cpu-intc"; | |
| interrupt-controller; | |
| u-boot,dm-spl; | |
| phandle = <0x05>; | |
| }; | |
| }; | |
| cpu@3 { | |
| compatible = "sifive,u74-mc\0riscv"; | |
| reg = <0x03>; | |
| d-cache-block-size = <0x40>; | |
| d-cache-sets = <0x40>; | |
| d-cache-size = <0x8000>; | |
| d-tlb-sets = <0x01>; | |
| d-tlb-size = <0x28>; | |
| device_type = "cpu"; | |
| i-cache-block-size = <0x40>; | |
| i-cache-sets = <0x40>; | |
| i-cache-size = <0x8000>; | |
| i-tlb-sets = <0x01>; | |
| i-tlb-size = <0x28>; | |
| mmu-type = "riscv,sv39"; | |
| next-level-cache = <0x01>; | |
| riscv,isa = "rv64imafdcbsux"; | |
| tlb-split; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x30>; | |
| interrupt-controller { | |
| #interrupt-cells = <0x01>; | |
| compatible = "riscv,cpu-intc"; | |
| interrupt-controller; | |
| u-boot,dm-spl; | |
| phandle = <0x06>; | |
| }; | |
| }; | |
| cpu@4 { | |
| compatible = "sifive,u74-mc\0riscv"; | |
| reg = <0x04>; | |
| d-cache-block-size = <0x40>; | |
| d-cache-sets = <0x40>; | |
| d-cache-size = <0x8000>; | |
| d-tlb-sets = <0x01>; | |
| d-tlb-size = <0x28>; | |
| device_type = "cpu"; | |
| i-cache-block-size = <0x40>; | |
| i-cache-sets = <0x40>; | |
| i-cache-size = <0x8000>; | |
| i-tlb-sets = <0x01>; | |
| i-tlb-size = <0x28>; | |
| mmu-type = "riscv,sv39"; | |
| next-level-cache = <0x01>; | |
| riscv,isa = "rv64imafdcbsux"; | |
| tlb-split; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x31>; | |
| interrupt-controller { | |
| #interrupt-cells = <0x01>; | |
| compatible = "riscv,cpu-intc"; | |
| interrupt-controller; | |
| u-boot,dm-spl; | |
| phandle = <0x07>; | |
| }; | |
| }; | |
| }; | |
| soc { | |
| compatible = "simple-bus"; | |
| interrupt-parent = <0x02>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| #clock-cells = <0x01>; | |
| ranges; | |
| u-boot,dm-spl; | |
| phandle = <0x32>; | |
| pmu { | |
| compatible = "riscv,pmu"; | |
| riscv,event-to-mhpmcounters = <0x05 0x06 0x18 0x08 0x09 0x18>; | |
| riscv,event-to-mhpmevent = <0x05 0x00 0x4000 0x06 0x00 0x4001 0x08 0x00 0x4008 0x09 0x00 0x4009>; | |
| riscv,raw-event-to-mhpmcounters = <0x00 0x100 0xffffffff 0xffffffff 0x18 0x00 0x200 0xffffffff 0xffffffff 0x18 0x00 0x400 0xffffffff 0xffffffff 0x18 0x00 0x800 0xffffffff 0xffffffff 0x18 0x00 0x1000 0xffffffff 0xffffffff 0x18 0x00 0x2000 0xffffffff 0xffffffff 0x18 0x00 0x4000 0xffffffff 0xffffffff 0x18 0x00 0x8000 0xffffffff 0xffffffff 0x18 0x00 0x10000 0xffffffff 0xffffffff 0x18 0x00 0x20000 0xffffffff 0xffffffff 0x18 0x00 0x40000 0xffffffff 0xffffffff 0x18 0x00 0x80000 0xffffffff 0xffffffff 0x18 0x00 0x100000 0xffffffff 0xffffffff 0x18 0x00 0x200000 0xffffffff 0xffffffff 0x18 0x00 0x400000 0xffffffff 0xffffffff 0x18 0x00 0x800000 0xffffffff 0xffffffff 0x18 0x00 0x1000000 0xffffffff 0xffffffff 0x18 0x00 0x2000000 0xffffffff 0xffffffff 0x18 0x00 0x101 0xffffffff 0xffffffff 0x18 0x00 0x201 0xffffffff 0xffffffff 0x18 0x00 0x401 0xffffffff 0xffffffff 0x18 0x00 0x801 0xffffffff 0xffffffff 0x18 0x00 0x1001 0xffffffff 0xffffffff 0x18 0x00 0x2001 0xffffffff 0xffffffff 0x18 0x00 0x4001 0xffffffff 0xffffffff 0x18 0x00 0x8001 0xffffffff 0xffffffff 0x18 0x00 0x10001 0xffffffff 0xffffffff 0x18 0x00 0x20001 0xffffffff 0xffffffff 0x18 0x00 0x40001 0xffffffff 0xffffffff 0x18 0x00 0x102 0xffffffff 0xffffffff 0x18 0x00 0x202 0xffffffff 0xffffffff 0x18 0x00 0x402 0xffffffff 0xffffffff 0x18 0x00 0x802 0xffffffff 0xffffffff 0x18 0x00 0x1002 0xffffffff 0xffffffff 0x18 0x00 0x2002 0xffffffff 0xffffffff 0x18>; | |
| }; | |
| cache-controller@2010000 { | |
| compatible = "sifive,fu740-c000-ccache\0cache"; | |
| reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x2000000>; | |
| reg-names = "control\0sideband"; | |
| interrupts = <0x01 0x03 0x04 0x02>; | |
| cache-block-size = <0x40>; | |
| cache-level = <0x02>; | |
| cache-sets = <0x800>; | |
| cache-size = <0x200000>; | |
| cache-unified; | |
| phandle = <0x01>; | |
| }; | |
| aon_syscon@17010000 { | |
| compatible = "syscon"; | |
| reg = <0x00 0x17010000 0x00 0x1000>; | |
| phandle = <0x33>; | |
| }; | |
| stg_syscon@10240000 { | |
| compatible = "syscon"; | |
| reg = <0x00 0x10240000 0x00 0x1000>; | |
| phandle = <0x11>; | |
| }; | |
| sys_syscon@13030000 { | |
| compatible = "syscon"; | |
| reg = <0x00 0x13030000 0x00 0x1000>; | |
| phandle = <0x12>; | |
| }; | |
| clint@2000000 { | |
| compatible = "riscv,clint0"; | |
| reg = <0x00 0x2000000 0x00 0x10000>; | |
| reg-names = "control"; | |
| interrupts-extended = <0x03 0x03 0x03 0x07 0x04 0x03 0x04 0x07 0x05 0x03 0x05 0x07 0x06 0x03 0x06 0x07 0x07 0x03 0x07 0x07>; | |
| #interrupt-cells = <0x01>; | |
| u-boot,dm-spl; | |
| phandle = <0x34>; | |
| }; | |
| plic@c000000 { | |
| compatible = "riscv,plic0"; | |
| reg = <0x00 0xc000000 0x00 0x4000000>; | |
| reg-names = "control"; | |
| interrupts-extended = <0x03 0x0b 0x04 0x0b 0x04 0x09 0x05 0x0b 0x05 0x09 0x06 0x0b 0x06 0x09 0x07 0x0b 0x07 0x09>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x01>; | |
| riscv,max-priority = <0x07>; | |
| riscv,ndev = <0x88>; | |
| phandle = <0x02>; | |
| }; | |
| clock-controller { | |
| compatible = "starfive,jh7110-clkgen"; | |
| reg = <0x00 0x13020000 0x00 0x10000 0x00 0x10230000 0x00 0x10000 0x00 0x17000000 0x00 0x10000>; | |
| reg-names = "sys\0stg\0aon"; | |
| clocks = <0x08 0x09 0x0a 0x0b>; | |
| clock-names = "osc\0gmac1_rmii_refin\0stg_apb\0gmac0_rmii_refin"; | |
| #clock-cells = <0x01>; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x0f>; | |
| }; | |
| clock-controller@295C0000 { | |
| compatible = "starfive,jh7110-clk-vout"; | |
| reg = <0x00 0x295c0000 0x00 0x10000>; | |
| reg-names = "vout"; | |
| clocks = <0x0c 0x0d 0x0e>; | |
| clock-names = "hdmitx0_pixelclk\0mipitx_dphy_rxesc\0mipitx_dphy_txbytehs"; | |
| #clock-cells = <0x01>; | |
| status = "disabled"; | |
| phandle = <0x1c>; | |
| }; | |
| clock-controller@19810000 { | |
| compatible = "starfive,jh7110-clk-isp"; | |
| reg = <0x00 0x19810000 0x00 0x10000>; | |
| reg-names = "isp"; | |
| #clock-cells = <0x01>; | |
| clocks = <0x0f 0x10a 0x0f 0x33 0x0f 0x34>; | |
| clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp\0u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x\0u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi"; | |
| resets = <0x10 0x29 0x10 0x2a>; | |
| reset-names = "rst_isp_top_n\0rst_isp_top_axi"; | |
| status = "disabled"; | |
| phandle = <0x17>; | |
| }; | |
| spi@13010000 { | |
| compatible = "cdns,qspi-nor"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0x13010000 0x00 0x10000 0x00 0x21000000 0x00 0x400000>; | |
| clocks = <0x0f 0x5a>; | |
| clock-names = "clk_ref"; | |
| resets = <0x10 0x3e 0x10 0x3d 0x10 0x3f>; | |
| resets-names = "rst_apb\0rst_ahb\0rst_ref"; | |
| cdns,fifo-depth = <0x100>; | |
| cdns,fifo-width = <0x04>; | |
| spi-max-frequency = <0xee6b280>; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x35>; | |
| nor-flash@0 { | |
| compatible = "jedec,spi-nor"; | |
| reg = <0x00>; | |
| spi-max-frequency = <0x5f5e100>; | |
| cdns,tshsl-ns = <0x01>; | |
| cdns,tsd2d-ns = <0x01>; | |
| cdns,tchsh-ns = <0x01>; | |
| cdns,tslch-ns = <0x01>; | |
| u-boot,dm-spl; | |
| phandle = <0x36>; | |
| }; | |
| }; | |
| otp@17050000 { | |
| compatible = "starfive,jh7110-otp"; | |
| reg = <0x00 0x17050000 0x00 0x10000>; | |
| clock-frequency = "\0=\t"; | |
| clocks = <0x0f 0xe4>; | |
| clock-names = "apb"; | |
| phandle = <0x37>; | |
| }; | |
| usbdrd { | |
| compatible = "starfive,jh7110-cdns3"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| clocks = <0x0f 0xc4 0x0f 0xc2 0x0f 0xc3 0x0f 0xbf 0x0f 0xc1 0x0f 0xc0>; | |
| clock-names = "app\0lpm\0stb\0apb\0axi\0utmi"; | |
| resets = <0x10 0x8a 0x10 0x88 0x10 0x87 0x10 0x89>; | |
| reset-names = "pwrup\0apb\0axi\0utmi"; | |
| starfive,stg-syscon = <0x11 0x04>; | |
| starfive,sys-syscon = <0x12 0x18>; | |
| status = "okay"; | |
| phandle = <0x38>; | |
| usb@10100000 { | |
| compatible = "cdns,usb3"; | |
| reg = <0x00 0x10100000 0x00 0x10000 0x00 0x10110000 0x00 0x10000 0x00 0x10120000 0x00 0x10000>; | |
| reg-names = "otg\0xhci\0dev"; | |
| interrupts = <0x6c 0x6d 0x6e>; | |
| interrupt-names = "host\0peripheral\0otg"; | |
| phy-names = "cdns3,usb3-phy\0cnds3,usb2-phy"; | |
| maximum-speed = "super-speed"; | |
| dr_mode = "host"; | |
| phandle = <0x39>; | |
| }; | |
| }; | |
| timer@13050000 { | |
| compatible = "starfive,si5-timers"; | |
| reg = <0x00 0x13050000 0x00 0x10000>; | |
| interrupts = <0x45 0x46 0x47 0x48>; | |
| interrupt-names = "timer0\0timer1\0timer2\0timer3"; | |
| clocks = <0x0f 0x7d 0x0f 0x7e 0x0f 0x7f 0x0f 0x80 0x0f 0x7c>; | |
| clock-names = "timer0\0timer1\0timer2\0timer3\0apb_clk"; | |
| clock-frequency = <0x1e8480>; | |
| status = "disabled"; | |
| phandle = <0x3a>; | |
| }; | |
| wdog@13070000 { | |
| compatible = "starfive,dskit-wdt"; | |
| reg = <0x00 0x13070000 0x00 0x10000>; | |
| interrupts = <0x44>; | |
| interrupt-names = "wdog"; | |
| clock-frequency = <0x1e8480>; | |
| clocks = <0x0f 0x7b 0x0f 0x7a>; | |
| clock-names = "core_clk\0apb_clk"; | |
| resets = <0x10 0x6d 0x10 0x6e>; | |
| reset-names = "rst_apb\0rst_core"; | |
| timeout-sec = <0x0f>; | |
| status = "disabled"; | |
| phandle = <0x3b>; | |
| }; | |
| rtc@17040000 { | |
| compatible = "starfive,rtc_hms"; | |
| reg = <0x00 0x17040000 0x00 0x10000>; | |
| interrupts = <0x0a 0x0b 0x0c>; | |
| interrupt-names = "rtc_ms_pulse\0rtc_sec_pulse\0rtc"; | |
| clocks = <0x0f 0xe5 0x0f 0xe8>; | |
| clock-names = "pclk\0cal_clk"; | |
| resets = <0x10 0xa5 0x10 0xa6 0x10 0xa7>; | |
| reset-names = "rst_apb\0rst_cal\0rst_osc"; | |
| rtc,cal-clock-freq = <0xf4240>; | |
| status = "okay"; | |
| phandle = <0x3c>; | |
| }; | |
| pmu@17030000 { | |
| compatible = "starfive,jh7110-pmu"; | |
| reg = <0x00 0x17030000 0x00 0x10000>; | |
| interrupts = <0x6f>; | |
| status = "okay"; | |
| phandle = <0x3d>; | |
| }; | |
| serial@10000000 { | |
| compatible = "snps,dw-apb-uart"; | |
| reg = <0x00 0x10000000 0x00 0x10000>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| clocks = <0x0f 0x92 0x0f 0x91>; | |
| clock-names = "baudclk\0apb_pclk"; | |
| resets = <0x10 0x53 0x10 0x54>; | |
| interrupts = <0x20>; | |
| status = "okay"; | |
| reg-offset = <0x00>; | |
| current-speed = <0x1c200>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x13>; | |
| clock-frequency = <0x16e3600>; | |
| u-boot,dm-spl; | |
| phandle = <0x3e>; | |
| }; | |
| serial@10010000 { | |
| compatible = "snps,dw-apb-uart"; | |
| reg = <0x00 0x10010000 0x00 0x10000>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| clocks = <0x0f 0x94 0x0f 0x93>; | |
| clock-names = "baudclk\0apb_pclk"; | |
| resets = <0x10 0x55 0x10 0x56>; | |
| interrupts = <0x21>; | |
| status = "disabled"; | |
| phandle = <0x3f>; | |
| }; | |
| serial@10020000 { | |
| compatible = "snps,dw-apb-uart"; | |
| reg = <0x00 0x10020000 0x00 0x10000>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| clocks = <0x0f 0x96 0x0f 0x95>; | |
| clock-names = "baudclk\0apb_pclk"; | |
| resets = <0x10 0x57 0x10 0x58>; | |
| interrupts = <0x22>; | |
| status = "disabled"; | |
| phandle = <0x40>; | |
| }; | |
| serial@12000000 { | |
| compatible = "snps,dw-apb-uart"; | |
| reg = <0x00 0x12000000 0x00 0x10000>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| clocks = <0x0f 0x98 0x0f 0x97>; | |
| clock-names = "baudclk\0apb_pclk"; | |
| resets = <0x10 0x59 0x10 0x5a>; | |
| interrupts = <0x2d>; | |
| status = "disabled"; | |
| phandle = <0x41>; | |
| }; | |
| serial@12010000 { | |
| compatible = "snps,dw-apb-uart"; | |
| reg = <0x00 0x12010000 0x00 0x10000>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| clocks = <0x0f 0x9a 0x0f 0x99>; | |
| clock-names = "baudclk\0apb_pclk"; | |
| resets = <0x10 0x5b 0x10 0x5c>; | |
| interrupts = <0x2e>; | |
| status = "disabled"; | |
| phandle = <0x42>; | |
| }; | |
| serial@12020000 { | |
| compatible = "snps,dw-apb-uart"; | |
| reg = <0x00 0x12020000 0x00 0x10000>; | |
| reg-io-width = <0x04>; | |
| reg-shift = <0x02>; | |
| clocks = <0x0f 0x9c 0x0f 0x9b>; | |
| clock-names = "baudclk\0apb_pclk"; | |
| resets = <0x10 0x5d 0x10 0x5e>; | |
| interrupts = <0x2f>; | |
| status = "disabled"; | |
| phandle = <0x43>; | |
| }; | |
| dma-controller@16050000 { | |
| compatible = "starfive,axi-dma"; | |
| reg = <0x00 0x16050000 0x00 0x10000>; | |
| clocks = <0x0f 0xd9 0x0f 0xda>; | |
| clock-names = "core-clk\0cfgr-clk"; | |
| resets = <0x10 0x85 0x10 0x86>; | |
| reset-names = "rst_axi\0rst_ahb"; | |
| interrupts = <0x49>; | |
| #dma-cells = <0x02>; | |
| dma-channels = <0x04>; | |
| snps,dma-masters = <0x01>; | |
| snps,data-width = <0x03>; | |
| snps,num-hs-if = <0x38>; | |
| snps,block-size = <0x10000 0x10000 0x10000 0x10000>; | |
| snps,priority = <0x00 0x01 0x02 0x03>; | |
| snps,axi-max-burst-len = <0x10>; | |
| status = "disabled"; | |
| phandle = <0x19>; | |
| }; | |
| gpio@13040000 { | |
| compatible = "starfive,jh7110-sys-pinctrl"; | |
| reg = <0x00 0x13040000 0x00 0x10000>; | |
| reg-names = "control"; | |
| interrupts = <0x5b>; | |
| interrupt-controller; | |
| #gpio-cells = <0x02>; | |
| ngpios = <0x40>; | |
| status = "okay"; | |
| phandle = <0x44>; | |
| uart0-0 { | |
| phandle = <0x13>; | |
| tx-pins { | |
| pinmux = <0xff140005>; | |
| bias-disable; | |
| drive-strength = <0x0c>; | |
| input-disable; | |
| input-schmitt-disable; | |
| slew-rate = <0x00>; | |
| }; | |
| rx-pins { | |
| pinmux = <0xe000406>; | |
| bias-pull-up; | |
| drive-strength = <0x02>; | |
| input-enable; | |
| input-schmitt-enable; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| mmc0-pins { | |
| phandle = <0x15>; | |
| mmc0-pins-rest { | |
| pinmux = <0xff13003e>; | |
| bias-pull-up; | |
| drive-strength = <0x0c>; | |
| input-disable; | |
| input-schmitt-disable; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| sdcard1-pins { | |
| phandle = <0x16>; | |
| sdcard1-pins0 { | |
| pinmux = <0xff37000a>; | |
| bias-pull-up; | |
| drive-strength = <0x0c>; | |
| input-disable; | |
| input-schmitt-disable; | |
| slew-rate = <0x00>; | |
| }; | |
| sdcard1-pins1 { | |
| pinmux = <0x2c394c09>; | |
| bias-pull-up; | |
| drive-strength = <0x0c>; | |
| input-enable; | |
| input-schmitt-enable; | |
| slew-rate = <0x00>; | |
| }; | |
| sdcard1-pins2 { | |
| pinmux = <0x2d3a500b>; | |
| bias-pull-up; | |
| drive-strength = <0x0c>; | |
| input-enable; | |
| input-schmitt-enable; | |
| slew-rate = <0x00>; | |
| }; | |
| sdcard1-pins3 { | |
| pinmux = <0x2e3b540c>; | |
| bias-pull-up; | |
| drive-strength = <0x0c>; | |
| input-enable; | |
| input-schmitt-enable; | |
| slew-rate = <0x00>; | |
| }; | |
| sdcard1-pins4 { | |
| pinmux = <0x2f3c5807>; | |
| bias-pull-up; | |
| drive-strength = <0x0c>; | |
| input-enable; | |
| input-schmitt-enable; | |
| slew-rate = <0x00>; | |
| }; | |
| sdcard1-pins5 { | |
| pinmux = <0x303d5c08>; | |
| bias-pull-up; | |
| drive-strength = <0x0c>; | |
| input-enable; | |
| input-schmitt-enable; | |
| slew-rate = <0x00>; | |
| }; | |
| }; | |
| }; | |
| gpio@17020000 { | |
| compatible = "starfive,jh7110-aon-pinctrl"; | |
| reg = <0x00 0x17020000 0x00 0x10000>; | |
| reg-names = "control"; | |
| interrupts = <0x5a>; | |
| interrupt-controller; | |
| #gpio-cells = <0x02>; | |
| ngpios = <0x04>; | |
| status = "disabled"; | |
| phandle = <0x45>; | |
| }; | |
| trng@1600C000 { | |
| compatible = "starfive,trng"; | |
| reg = <0x00 0x1600c000 0x00 0x4000>; | |
| clocks = <0x0f 0xcd 0x0f 0xce>; | |
| clock-names = "hclk\0miscahb_clk"; | |
| resets = <0x10 0x83>; | |
| interrupts = <0x1e>; | |
| status = "disabled"; | |
| phandle = <0x46>; | |
| }; | |
| sec_dma@16008000 { | |
| compatible = "starfive,pl080"; | |
| reg = <0x00 0x16008000 0x00 0x4000>; | |
| reg-names = "sec_dma"; | |
| interrupts = <0x1d>; | |
| clocks = <0x0f 0xcd 0x0f 0xce>; | |
| clock-names = "sec_hclk\0sec_ahb"; | |
| resets = <0x10 0x83>; | |
| reset-names = "sec_hre"; | |
| lli-bus-interface-ahb1; | |
| mem-bus-interface-ahb1; | |
| memcpy-burst-size = <0x100>; | |
| memcpy-bus-width = <0x20>; | |
| #dma-cells = <0x02>; | |
| status = "disabled"; | |
| phandle = <0x14>; | |
| }; | |
| crypto@16000000 { | |
| compatible = "starfive,jh7110-sec"; | |
| reg = <0x00 0x16000000 0x00 0x4000 0x00 0x16008000 0x00 0x4000>; | |
| reg-names = "secreg\0secdma"; | |
| interrupts = <0x1c 0x1d>; | |
| interrupt-names = "secirq\0dmairq"; | |
| clocks = <0x0f 0xcd 0x0f 0xce>; | |
| clock-names = "sec_hclk\0sec_ahb"; | |
| resets = <0x10 0x83>; | |
| reset-names = "sec_hre"; | |
| enable-dma = "true"; | |
| dmas = <0x14 0x01 0x02 0x14 0x00 0x02>; | |
| dma-names = "sec_m\0sec_p"; | |
| status = "disabled"; | |
| phandle = <0x47>; | |
| }; | |
| i2c@12060000 { | |
| compatible = "snps,designware-i2c"; | |
| reg = <0x00 0x12060000 0x00 0x10000>; | |
| clocks = <0x0f 0x12b 0x0f 0x90>; | |
| clock-names = "ref\0pclk"; | |
| resets = <0x10 0x52>; | |
| interrupts = <0x33>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x48>; | |
| }; | |
| i2c@10030000 { | |
| compatible = "snps,designware-i2c"; | |
| reg = <0x00 0x10030000 0x00 0x10000>; | |
| clocks = <0x0f 0x125 0x0f 0x8a>; | |
| clock-names = "ref\0pclk"; | |
| resets = <0x10 0x4c>; | |
| interrupts = <0x23>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x49>; | |
| }; | |
| i2c@10040000 { | |
| compatible = "snps,designware-i2c"; | |
| reg = <0x00 0x10040000 0x00 0x10000>; | |
| clocks = <0x0f 0x126 0x0f 0x8b>; | |
| clock-names = "ref\0pclk"; | |
| resets = <0x10 0x4d>; | |
| interrupts = <0x24>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x4a>; | |
| }; | |
| i2c5@12050000 { | |
| compatible = "snps,designware-i2c"; | |
| reg = <0x00 0x12050000 0x00 0x10000>; | |
| clocks = <0x0f 0x12a 0x0f 0x8f>; | |
| clock-names = "ref\0pclk"; | |
| resets = <0x10 0x51>; | |
| interrupts = <0x32>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "okay"; | |
| clock-frequency = <0x186a0>; | |
| i2c-sda-hold-time-ns = <0x12c>; | |
| i2c-sda-falling-time-ns = <0xbb8>; | |
| i2c-scl-falling-time-ns = <0xbb8>; | |
| auto_calc_scl_lhcnt; | |
| u-boot,dm-spl; | |
| phandle = <0x4b>; | |
| eeprom@50 { | |
| compatible = "atmel,24c04"; | |
| reg = <0x50>; | |
| pagesize = <0x10>; | |
| u-boot,dm-spl; | |
| }; | |
| axp15060_reg@36 { | |
| compatible = "stf,axp15060-regulator"; | |
| reg = <0x36>; | |
| phandle = <0x4c>; | |
| }; | |
| }; | |
| sdio0@16010000 { | |
| compatible = "snps,dw-mshc"; | |
| reg = <0x00 0x16010000 0x00 0x10000>; | |
| clocks = <0x0f 0x5b 0x0f 0x5d>; | |
| clock-names = "biu\0ciu"; | |
| resets = <0x10 0x40>; | |
| reset-names = "reset"; | |
| fifo-depth = <0x20>; | |
| bus-width = <0x08>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x15>; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x4d>; | |
| }; | |
| sdio1@16020000 { | |
| compatible = "snps,dw-mshc"; | |
| reg = <0x00 0x16020000 0x00 0x10000>; | |
| clocks = <0x0f 0x5c 0x0f 0x5e>; | |
| clock-names = "biu\0ciu"; | |
| resets = <0x10 0x41>; | |
| reset-names = "reset"; | |
| fifo-depth = <0x20>; | |
| bus-width = <0x04>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x16>; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x4e>; | |
| }; | |
| vin_sysctl@19800000 { | |
| compatible = "starfive,stf-vin"; | |
| reg = <0x00 0x19800000 0x00 0x10000 0x00 0x19810000 0x00 0x10000 0x00 0x19820000 0x00 0x10000 0x00 0x19830000 0x00 0x10000 0x00 0x19840000 0x00 0x10000 0x00 0x19870000 0x00 0x30000 0x00 0x198a0000 0x00 0x30000 0x00 0x11840000 0x00 0x10000 0x00 0x17030000 0x00 0x10000 0x00 0x13020000 0x00 0x10000>; | |
| reg-names = "mipi0\0vclk\0vrst\0mipi1\0sctrl\0isp0\0isp1\0trst\0pmu\0syscrg"; | |
| clocks = <0x17 0x00 0x17 0x06 0x17 0x07 0x17 0x0d 0x17 0x02 0x17 0x0c 0x17 0x01 0x17 0x08 0x17 0x09 0x17 0x0a 0x17 0x0b>; | |
| clock-names = "clk_apb_func\0clk_pclk\0clk_sys_clk\0clk_wrapper_clk_c\0clk_dvp_inv\0clk_axiwr\0clk_mipi_rx0_pxl\0clk_pixel_clk_if0\0clk_pixel_clk_if1\0clk_pixel_clk_if2\0clk_pixel_clk_if3"; | |
| resets = <0x10 0xc0 0x10 0xc1 0x10 0xc4 0x10 0xc9 0x10 0xca 0x10 0xcb 0x10 0xc5 0x10 0xc6 0x10 0xc7 0x10 0xc8 0x10 0xc2 0x10 0xc3>; | |
| reset-names = "rst_wrapper_p\0rst_wrapper_c\0rst_pclk\0rst_sys_clk\0rst_axird\0rst_axiwr\0rst_pixel_clk_if0\0rst_pixel_clk_if1\0rst_pixel_clk_if2\0rst_pixel_clk_if3\0rst_m31dphy_hw\0rst_m31dphy_b09_always_on"; | |
| interrupts = <0x5c 0x57 0x56>; | |
| status = "disabled"; | |
| phandle = <0x4f>; | |
| }; | |
| jpu@11900000 { | |
| compatible = "starfive,jpu"; | |
| reg = <0x00 0x13090000 0x00 0x300>; | |
| interrupts = <0x0e>; | |
| clocks = <0x0f 0x42 0x0f 0x43 0x0f 0x44>; | |
| clock-names = "axi_clk\0core_clk\0apb_clk"; | |
| resets = <0x10 0x2c 0x10 0x2d 0x10 0x2e>; | |
| reset-names = "rst_axi\0rst_core\0rst_apb"; | |
| status = "disabled"; | |
| phandle = <0x50>; | |
| }; | |
| vpu_dec@130A0000 { | |
| compatible = "starfive,vdec"; | |
| reg = <0x00 0x130a0000 0x00 0x10000>; | |
| interrupts = <0x0d>; | |
| clocks = <0x0f 0x46 0x0f 0x47 0x0f 0x48 0x0f 0x49 0x0f 0x4c>; | |
| clock-names = "axi_clk\0bpu_clk\0vce_clk\0apb_clk\0noc_bus"; | |
| resets = <0x10 0x2f 0x10 0x30 0x10 0x31 0x10 0x32 0x10 0x35>; | |
| reset-names = "rst_axi\0rst_bpu\0rst_vce\0rst_apb\0rst_sram"; | |
| starfive,vdec_noc_ctrl; | |
| status = "disabled"; | |
| phandle = <0x51>; | |
| }; | |
| vpu_enc@130B0000 { | |
| compatible = "starfive,venc"; | |
| reg = <0x00 0x130b0000 0x00 0x10000>; | |
| interrupts = <0x0f>; | |
| clocks = <0x0f 0x4e 0x0f 0x4f 0x0f 0x50 0x0f 0x51 0x0f 0x52>; | |
| clock-names = "axi_clk\0bpu_clk\0vce_clk\0apb_clk\0noc_bus"; | |
| resets = <0x10 0x36 0x10 0x37 0x10 0x38 0x10 0x39 0x10 0x3a>; | |
| reset-names = "rst_axi\0rst_bpu\0rst_vce\0rst_apb\0rst_sram"; | |
| starfive,venc_noc_ctrl; | |
| status = "disabled"; | |
| phandle = <0x52>; | |
| }; | |
| reset-controller { | |
| compatible = "starfive,jh7110-reset"; | |
| reg = <0x00 0x13020000 0x00 0x10000 0x00 0x10230000 0x00 0x10000 0x00 0x17000000 0x00 0x10000 0x00 0x19810000 0x00 0x10000 0x00 0x295c0000 0x00 0x10000>; | |
| reg-names = "syscrg\0stgcrg\0aoncrg\0ispcrg\0voutcrg"; | |
| #reset-cells = <0x01>; | |
| status = "okay"; | |
| u-boot,dm-spl; | |
| phandle = <0x10>; | |
| }; | |
| stmmac-axi-config { | |
| snps,wr_osr_lmt = <0x0f>; | |
| snps,rd_osr_lmt = <0x0f>; | |
| snps,blen = <0x100 0x80 0x40 0x20 0x00 0x00 0x00>; | |
| phandle = <0x18>; | |
| }; | |
| ethernet@16030000 { | |
| compatible = "starfive,jh7110-eqos-5.20"; | |
| reg = <0x00 0x16030000 0x00 0x10000>; | |
| clock-names = "gtx\0tx\0ptp_ref\0stmmaceth\0pclk\0gtxc\0rmii_rtx"; | |
| clocks = <0x0f 0x6c 0x0f 0xe0 0x0f 0x6d 0x0f 0xdd 0x0f 0xde 0x0f 0x6f 0x0f 0xdf>; | |
| resets = <0x10 0xa1 0x10 0xa0>; | |
| reset-names = "ahb\0stmmaceth"; | |
| interrupts = <0x07 0x06 0x05>; | |
| interrupt-names = "macirq\0eth_wake_irq\0eth_lpi"; | |
| max-frame-size = <0x2328>; | |
| phy-mode = "rgmii-id"; | |
| snps,multicast-filter-bins = <0x100>; | |
| snps,perfect-filter-entries = <0x80>; | |
| rx-fifo-depth = <0x40000>; | |
| tx-fifo-depth = <0x20000>; | |
| snps,fixed-burst; | |
| snps,no-pbl-x8; | |
| snps,force_thresh_dma_mode; | |
| snps,axi-config = <0x18>; | |
| snps,tso; | |
| snps,en-tx-lpi-clockgating; | |
| snps,en-lpi; | |
| snps,write-requests = <0x02>; | |
| snps,read-requests = <0x10>; | |
| snps,burst-map = <0x07>; | |
| snps,txpbl = <0x10>; | |
| snps,rxpbl = <0x10>; | |
| status = "okay"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x53>; | |
| ethernet-phy@0 { | |
| rxc_dly_en = <0x01>; | |
| tx_delay_sel_fe = <0x05>; | |
| tx_delay_sel = <0x0a>; | |
| tx_inverted_10 = <0x01>; | |
| tx_inverted_100 = <0x01>; | |
| tx_inverted_1000 = <0x01>; | |
| phandle = <0x54>; | |
| }; | |
| }; | |
| ethernet@16040000 { | |
| compatible = "starfive,jh7110-eqos-5.20"; | |
| reg = <0x00 0x16040000 0x00 0x10000>; | |
| clock-names = "gtx\0tx\0ptp_ref\0stmmaceth\0pclk\0gtxc\0rmii_rtx"; | |
| clocks = <0x0f 0x64 0x0f 0x69 0x0f 0x66 0x0f 0x61 0x0f 0x62 0x0f 0x6b 0x0f 0x65>; | |
| resets = <0x10 0x43 0x10 0x42>; | |
| reset-names = "ahb\0stmmaceth"; | |
| interrupts = <0x4e 0x4d 0x4c>; | |
| interrupt-names = "macirq\0eth_wake_irq\0eth_lpi"; | |
| max-frame-size = <0x2328>; | |
| phy-mode = "rgmii-id"; | |
| snps,multicast-filter-bins = <0x100>; | |
| snps,perfect-filter-entries = <0x80>; | |
| rx-fifo-depth = <0x40000>; | |
| tx-fifo-depth = <0x20000>; | |
| snps,fixed-burst; | |
| snps,no-pbl-x8; | |
| snps,force_thresh_dma_mode; | |
| snps,axi-config = <0x18>; | |
| snps,tso; | |
| snps,en-tx-lpi-clockgating; | |
| snps,en-lpi; | |
| snps,write-requests = <0x02>; | |
| snps,read-requests = <0x10>; | |
| snps,burst-map = <0x07>; | |
| snps,txpbl = <0x10>; | |
| snps,rxpbl = <0x10>; | |
| status = "okay"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x55>; | |
| ethernet-phy@1 { | |
| tx_delay_sel_fe = <0x05>; | |
| tx_delay_sel = <0x00>; | |
| rxc_dly_en = <0x00>; | |
| tx_inverted_10 = <0x01>; | |
| tx_inverted_100 = <0x01>; | |
| tx_inverted_1000 = <0x00>; | |
| phandle = <0x56>; | |
| }; | |
| }; | |
| gpu@18000000 { | |
| compatible = "img-gpu"; | |
| reg = <0x00 0x18000000 0x00 0x100000 0x00 0x130c000 0x00 0x10000>; | |
| clocks = <0x0f 0x30 0x0f 0x31 0x0f 0x2e 0x0f 0x2f 0x0f 0x32>; | |
| clock-names = "clk_apb\0clk_rtc\0clk_core\0clk_sys\0clk_axi"; | |
| resets = <0x10 0x15 0x10 0x16>; | |
| reset-names = "rst_apb\0rst_doma"; | |
| interrupts = <0x52>; | |
| current-clock = <0x7a1200>; | |
| status = "disabled"; | |
| phandle = <0x57>; | |
| }; | |
| can@130d0000 { | |
| compatible = "ipms,can"; | |
| reg = <0x00 0x130d0000 0x00 0x1000>; | |
| interrupts = <0x70>; | |
| clocks = <0x0f 0x73 0x0f 0x75 0x0f 0x74>; | |
| clock-names = "apb_clk\0core_clk\0timer_clk"; | |
| resets = <0x10 0x6f 0x10 0x70 0x10 0x71>; | |
| reset-names = "rst_apb\0rst_core\0rst_timer"; | |
| starfive,sys-syscon = <0x12 0x10 0x03 0x08>; | |
| syscon,can_or_canfd = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x58>; | |
| }; | |
| can@130e0000 { | |
| compatible = "ipms,can"; | |
| reg = <0x00 0x130e0000 0x00 0x1000>; | |
| interrupts = <0x71>; | |
| clocks = <0x0f 0x76 0x0f 0x78 0x0f 0x77>; | |
| clock-names = "apb_clk\0core_clk\0timer_clk"; | |
| resets = <0x10 0x72 0x10 0x73 0x10 0x74>; | |
| reset-names = "rst_apb\0rst_core\0rst_timer"; | |
| starfive,sys-syscon = <0x12 0x88 0x12 0x40000>; | |
| syscon,can_or_canfd = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x59>; | |
| }; | |
| tdm@10090000 { | |
| compatible = "starfive,sf-tdm"; | |
| reg = <0x00 0x10090000 0x00 0x1000>; | |
| reg-names = "tdm"; | |
| clocks = <0x0f 0x09 0x0f 0xb8 0x0f 0x0c 0x0f 0xb9 0x0f 0xba>; | |
| clock-names = "clk_ahb0\0clk_tdm_ahb\0clk_apb0\0clk_tdm_apb\0clk_tdm_intl"; | |
| resets = <0x10 0x69 0x10 0x6b 0x10 0x6a>; | |
| reset-names = "tdm_ahb\0tdm_apb\0tdm_rst"; | |
| dmas = <0x19 0x14 0x01 0x19 0x15 0x01>; | |
| dma-names = "rx\0tx"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x5a>; | |
| }; | |
| spdif0@100a0000 { | |
| compatible = "starfive,sf-spdif"; | |
| reg = <0x00 0x100a0000 0x00 0x1000>; | |
| clocks = <0x0f 0x9f 0x0f 0xa0 0x0f 0x12>; | |
| clock-names = "spdif-apb\0spdif-core\0audioclk"; | |
| resets = <0x10 0x5f>; | |
| reset-names = "rst_apb"; | |
| interrupts = <0x54>; | |
| interrupt-names = "tx"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x5b>; | |
| }; | |
| pwmdac@100b0000 { | |
| compatible = "starfive,pwmdac"; | |
| reg = <0x00 0x100b0000 0x00 0x1000>; | |
| clocks = <0x0f 0x0c 0x0f 0x9d 0x0f 0x9e>; | |
| clock-names = "apb0\0pwmdac-apb\0pwmdac-core"; | |
| resets = <0x10 0x60>; | |
| reset-names = "rst-apb"; | |
| dmas = <0x19 0x16 0x01>; | |
| dma-names = "tx"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x1f>; | |
| }; | |
| i2stx@100c0000 { | |
| compatible = "snps,designware-i2stx"; | |
| reg = <0x00 0x100c0000 0x00 0x1000>; | |
| clocks = <0x0f 0x0c>; | |
| clock-names = "i2sclk"; | |
| interrupt-names = "tx"; | |
| #sound-dai-cells = <0x00>; | |
| dmas = <0x19 0x1c 0x01>; | |
| dma-names = "rx"; | |
| status = "disabled"; | |
| phandle = <0x5c>; | |
| }; | |
| pdm@100d0000 { | |
| compatible = "starfive,sf-pdm"; | |
| reg = <0x00 0x100d0000 0x00 0x1000>; | |
| reg-names = "pdm"; | |
| clocks = <0x0f 0xb6 0x0f 0x0c 0x0f 0xb7 0x0f 0x130 0x0f 0x131 0x0f 0x132 0x0f 0x133 0x0f 0xb3>; | |
| clock-names = "pdm_dmic\0clk_apb0\0pdm_apb\0pdm_dmic0_bclk\0pdm_dmic0_lrck\0pdm_dmic1_bclk\0pdm_dmic1_lrck\0u0_i2srx_3ch_bclk"; | |
| resets = <0x10 0x61 0x10 0x62>; | |
| reset-names = "pdm_dmic\0pdm_apb"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x5d>; | |
| }; | |
| i2srx_3ch@100e0000 { | |
| compatible = "snps,designware-i2srx"; | |
| reg = <0x00 0x100e0000 0x00 0x1000>; | |
| clocks = <0x0f 0x0c 0x0f 0xaf 0x0f 0xb0>; | |
| clock-names = "apb0\03ch-apb\03ch-bclk"; | |
| resets = <0x10 0x63 0x10 0x64>; | |
| reset-names = "rst_apb_rx\0rst_bclk_rx"; | |
| interrupts = <0x2a>; | |
| interrupt-names = "rx"; | |
| dmas = <0x19 0x18 0x01>; | |
| dma-names = "rx"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x5e>; | |
| }; | |
| i2stx_4ch0@120b0000 { | |
| compatible = "snps,designware-i2stx-4ch0"; | |
| reg = <0x00 0x120b0000 0x00 0x1000>; | |
| clocks = <0x0f 0x11 0x0f 0xa2 0x0f 0xa4 0x0f 0x12 0x0f 0xa5 0x0f 0xa7>; | |
| clock-names = "inner\0bclk-mst\0lrck-mst\0mclk\0bclk0\0lrck0"; | |
| resets = <0x10 0x65 0x10 0x66>; | |
| reset-names = "rst_apb0\0rst_bclk0"; | |
| interrupts = <0x3a>; | |
| interrupt-names = "tx"; | |
| dmas = <0x19 0x2f 0x01>; | |
| dma-names = "tx"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x5f>; | |
| }; | |
| i2stx_4ch1@120c0000 { | |
| compatible = "snps,designware-i2stx-4ch1"; | |
| reg = <0x00 0x120c0000 0x00 0x1000>; | |
| clocks = <0x0f 0x11 0x0f 0xa9 0x0f 0xab 0x0f 0x12 0x0f 0xac 0x0f 0xae>; | |
| clock-names = "inner\0bclk-mst1\0lrck-mst1\0mclk\0bclk1\0lrck1"; | |
| resets = <0x10 0x67 0x10 0x68>; | |
| reset-names = "rst_apb1\0rst_bclk1"; | |
| interrupts = <0x3b>; | |
| interrupt-names = "tx"; | |
| dmas = <0x19 0x30 0x01>; | |
| dma-names = "tx"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x60>; | |
| }; | |
| pwm@120d0000 { | |
| compatible = "starfive,pwm0"; | |
| reg = <0x00 0x120d0000 0x00 0x10000>; | |
| reg-names = "control"; | |
| clocks = <0x0f 0x79>; | |
| resets = <0x10 0x6c>; | |
| starfive,approx-period = <0x1e8480>; | |
| #pwm-cells = <0x03>; | |
| starfive,npwm = <0x08>; | |
| status = "disabled"; | |
| phandle = <0x61>; | |
| }; | |
| spdif_transmitter { | |
| compatible = "linux,spdif-dit"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x62>; | |
| }; | |
| spdif_receiver { | |
| compatible = "linux,spdif-dir"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x63>; | |
| }; | |
| pwmdac-transmitter { | |
| compatible = "linux,pwmdac-dit"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x20>; | |
| }; | |
| dmic_codec { | |
| compatible = "dmic-codec"; | |
| #sound-dai-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x64>; | |
| }; | |
| spi@10060000 { | |
| compatible = "arm,pl022\0arm,primecell"; | |
| reg = <0x00 0x10060000 0x00 0x10000>; | |
| clocks = <0x0f 0x83>; | |
| clock-names = "apb_pclk"; | |
| resets = <0x10 0x45>; | |
| reset-names = "rst_apb"; | |
| interrupts = <0x26>; | |
| dmas = <0x19 0x0e 0x01 0x19 0x0f 0x01>; | |
| dma-names = "rx\0tx"; | |
| arm,primecell-periphid = <0x41022>; | |
| num-cs = <0x01>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x65>; | |
| }; | |
| pcie@2B000000 { | |
| compatible = "plda,pci-xpressrich3-axi"; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| #interrupt-cells = <0x01>; | |
| reg = <0x00 0x2b000000 0x00 0x1000000 0x09 0x40000000 0x00 0x10000000>; | |
| reg-names = "reg\0config"; | |
| device_type = "pci"; | |
| starfive,stg-syscon = <0x11 0xc0 0xc4 0x130>; | |
| bus-range = <0x00 0xff>; | |
| ranges = <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x6000000>; | |
| msi-parent = <0x02>; | |
| interrupts = <0x38>; | |
| interrupt-controller; | |
| interrupt-names = "msi"; | |
| interrupt-parent = <0x02>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x02 0x01 0x00 0x00 0x00 0x02 0x02 0x02 0x00 0x00 0x00 0x03 0x02 0x03 0x00 0x00 0x00 0x04 0x02 0x04>; | |
| resets = <0x10 0x8b 0x10 0x8c 0x10 0x8d 0x10 0x8e 0x10 0x8f 0x10 0x90>; | |
| reset-names = "rst_mst0\0rst_slv0\0rst_slv\0rst_brg\0rst_core\0rst_apb"; | |
| clocks = <0x0f 0xc8 0x0f 0xc6 0x0f 0xc7>; | |
| clock-names = "tl\0axi_mst0\0apb"; | |
| status = "disabled"; | |
| phandle = <0x66>; | |
| }; | |
| pcie@2C000000 { | |
| compatible = "plda,pci-xpressrich3-axi"; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| #interrupt-cells = <0x01>; | |
| reg = <0x00 0x2c000000 0x00 0x1000000 0x09 0xc0000000 0x00 0x10000000>; | |
| reg-names = "reg\0config"; | |
| device_type = "pci"; | |
| starfive,stg-syscon = <0x11 0x270 0x274 0x2e0>; | |
| bus-range = <0x00 0xff>; | |
| ranges = <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x6000000>; | |
| msi-parent = <0x02>; | |
| interrupts = <0x39>; | |
| interrupt-controller; | |
| interrupt-names = "msi"; | |
| interrupt-parent = <0x02>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x02 0x01 0x00 0x00 0x00 0x02 0x02 0x02 0x00 0x00 0x00 0x03 0x02 0x03 0x00 0x00 0x00 0x04 0x02 0x04>; | |
| resets = <0x10 0x91 0x10 0x92 0x10 0x93 0x10 0x94 0x10 0x95 0x10 0x96>; | |
| reset-names = "rst_mst0\0rst_slv0\0rst_slv\0rst_brg\0rst_core\0rst_apb"; | |
| clocks = <0x0f 0xcb 0x0f 0xc9 0x0f 0xca>; | |
| clock-names = "tl\0axi_mst0\0apb"; | |
| status = "disabled"; | |
| phandle = <0x67>; | |
| }; | |
| mailbox@0 { | |
| compatible = "starfive,mail_box"; | |
| reg = <0x00 0x13060000 0x00 0x1000>; | |
| clocks = <0x0f 0x71>; | |
| clock-names = "clk_apb"; | |
| resets = <0x10 0x44>; | |
| reset-names = "mbx_rre"; | |
| interrupts = <0x1a 0x1b>; | |
| #mbox-cells = <0x02>; | |
| status = "disabled"; | |
| phandle = <0x1a>; | |
| }; | |
| mailbox_client@0 { | |
| compatible = "starfive,mailbox-test"; | |
| mbox-names = "rx\0tx"; | |
| mboxes = <0x1a 0x00 0x01 0x1a 0x01 0x00>; | |
| status = "disabled"; | |
| phandle = <0x68>; | |
| }; | |
| dssctrl@295B0000 { | |
| compatible = "verisilicon,dss-ctrl\0syscon"; | |
| reg = <0x00 0x295b0000 0x00 0x90>; | |
| phandle = <0x1b>; | |
| }; | |
| hdmi-output { | |
| compatible = "verisilicon,hdmi-encoder"; | |
| verisilicon,dss-syscon = <0x1b>; | |
| verisilicon,mux-mask = <0x70 0x380>; | |
| verisilicon,mux-val = <0x40 0x280>; | |
| status = "disabled"; | |
| phandle = <0x69>; | |
| }; | |
| dc8200@29400000 { | |
| compatible = "verisilicon,dc8200"; | |
| reg = <0x00 0x29400000 0x00 0x100 0x00 0x29400800 0x00 0x2000 0x00 0x17030000 0x00 0x1000>; | |
| interrupts = <0x5f>; | |
| status = "disabled"; | |
| clocks = <0x0f 0x26 0x0f 0x27 0x0f 0x32 0x0f 0x4c 0x0f 0x52 0x0f 0x3c 0x0f 0x35 0x0f 0x60 0x0f 0x3a 0x0f 0x3e 0x0f 0x0a 0x0f 0x3d 0x0f 0x3f 0x0f 0xa2 0x1c 0x169 0x1c 0x16a 0x1c 0x166 0x1c 0x167 0x1c 0x168>; | |
| clock-names = "noc_cpu\0noc_cfg0\0noc_gpu\0noc_vdec\0noc_venc\0noc_disp\0noc_isp\0noc_stg\0vout_src\0top_vout_axi\0ahb1\0top_vout_ahb\0top_vout_hdmiTX0\0i2stx\0pix_clk\0vout_pix1\0axi_clk\0core_clk\0vout_ahb"; | |
| resets = <0x10 0x2b 0x10 0xe0 0x10 0xe1 0x10 0xe2 0x10 0x19 0x10 0x18 0x10 0x17 0x10 0x1b 0x10 0x1f 0x10 0x00 0x10 0x1a 0x10 0x1c 0x10 0x1e 0x10 0x1d>; | |
| reset-names = "rst_vout_src\0rst_axi\0rst_ahb\0rst_core\0rst_noc_cpu\0rst_noc_axicfg0\0rst_noc_apb\0rst_noc_gpu\0rst_noc_vdec\0rst_jtag2apb\0rst_noc_disp\0rst_noc_isp\0rst_noc_stg\0rst_noc_ddrc"; | |
| phandle = <0x6a>; | |
| }; | |
| mipi-dphy@295e0000 { | |
| compatible = "starfive,jh7100-mipi-dphy-tx"; | |
| reg = <0x00 0x295e0000 0x00 0x10000>; | |
| clocks = <0x1c 0x170>; | |
| clock-names = "dphy_txesc"; | |
| resets = <0x10 0xea 0x10 0xeb>; | |
| reset-names = "dphy_sys\0dphy_txbytehs"; | |
| #phy-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x1d>; | |
| }; | |
| mipi@295d0000 { | |
| compatible = "cdns,dsi"; | |
| reg = <0x00 0x295d0000 0x00 0x10000>; | |
| reg-names = "dsi"; | |
| clocks = <0x1c 0x16d 0x1c 0x16c 0x1c 0x16f 0x1c 0x16e>; | |
| clock-names = "sys\0apb\0txesc\0dpi"; | |
| resets = <0x10 0xe3 0x10 0xe4 0x10 0xe5 0x10 0xe6 0x10 0xe7 0x10 0xe8>; | |
| reset-names = "dsi_dpi\0dsi_apb\0dsi_rxesc\0dsi_sys\0dsi_txbytehs\0dsi_txesc"; | |
| phys = <0x1d>; | |
| phy-names = "dphy"; | |
| status = "disabled"; | |
| phandle = <0x6b>; | |
| port { | |
| endpoint { | |
| phandle = <0x6c>; | |
| }; | |
| }; | |
| panel@0 { | |
| status = "disabled"; | |
| phandle = <0x6d>; | |
| }; | |
| }; | |
| hdmi@29590000 { | |
| compatible = "rockchip,rk3036-inno-hdmi"; | |
| reg = <0x00 0x29590000 0x00 0x4000>; | |
| status = "disabled"; | |
| clocks = <0x1c 0x173 0x1c 0x171 0x1c 0x172>; | |
| clock-names = "sysclk\0mclk\0bclk"; | |
| resets = <0x10 0xe9>; | |
| reset-names = "hdmi_tx"; | |
| phandle = <0x6e>; | |
| }; | |
| snd-card { | |
| compatible = "simple-audio-card"; | |
| simple-audio-card,name = "Starfive-Multi-Sound-Card"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x6f>; | |
| simple-audio-card,dai-link@0 { | |
| reg = <0x00>; | |
| format = "left_j"; | |
| bitclock-master = <0x1e>; | |
| frame-master = <0x1e>; | |
| status = "okay"; | |
| cpu { | |
| sound-dai = <0x1f>; | |
| phandle = <0x1e>; | |
| }; | |
| codec { | |
| sound-dai = <0x20>; | |
| }; | |
| }; | |
| }; | |
| e24@0 { | |
| compatible = "starfive,e24"; | |
| reg = <0x00 0xc0110000 0x00 0x1000 0x00 0xc0111000 0x00 0x1f000>; | |
| reg-names = "ecmd\0espace"; | |
| clocks = <0x0f 0xd6 0x0f 0xd7 0x0f 0xd8>; | |
| clock-names = "clk_rtc\0clk_core\0clk_dbg"; | |
| resets = <0x10 0x84>; | |
| reset-names = "e24_core"; | |
| starfive,stg-syscon = <0x11>; | |
| interrupt-parent = <0x02>; | |
| firmware-name = "e24_elf"; | |
| irq-mode = <0x01>; | |
| mbox-names = "tx\0rx"; | |
| mboxes = <0x1a 0x00 0x02 0x1a 0x02 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges = <0xc0000000 0x00 0xc0000000 0x200000>; | |
| status = "disabled"; | |
| phandle = <0x70>; | |
| dsp@0 { | |
| }; | |
| }; | |
| dmc@100b0000 { | |
| compatible = "starfive,jh7110-dmc"; | |
| reg = <0x00 0x15700000 0x00 0x10000 0x00 0x13000000 0x00 0x10000>; | |
| resets = <0x10 0x26 0x10 0x27 0x10 0x28>; | |
| reset-names = "axi\0osc\0apb"; | |
| clock-frequency = <0x855>; | |
| u-boot,dm-spl; | |
| phandle = <0x71>; | |
| }; | |
| }; | |
| aliases { | |
| spi0 = "/soc/spi@13010000"; | |
| gpio0 = "/soc/gpio@13040000"; | |
| ethernet0 = "/soc/ethernet@16030000"; | |
| ethernet1 = "/soc/ethernet@16040000"; | |
| mmc0 = "/soc/sdio0@16010000"; | |
| mmc1 = "/soc/sdio1@16020000"; | |
| i2c0 = "/soc/i2c5@12050000"; | |
| }; | |
| chosen { | |
| stdout-path = "/soc/serial@10000000:115200"; | |
| starfive,boot-hart-id = <0x01>; | |
| u-boot,dm-spl; | |
| }; | |
| memory@80000000 { | |
| device_type = "memory"; | |
| reg = <0x00 0x40000000 0x01 0x00>; | |
| u-boot,dm-spl; | |
| }; | |
| firmware { | |
| spi0 = "/soc/qspi@11860000"; | |
| u-boot,dm-spl; | |
| }; | |
| config { | |
| u-boot,dm-spl; | |
| u-boot,spl-payload-offset = <0x100000>; | |
| }; | |
| __symbols__ { | |
| osc = "/osc"; | |
| gmac1_rmii_refin = "/gmac1_rmii_refin"; | |
| gmac1_rgmii_rxin = "/gmac1_rgmii_rxin"; | |
| i2stx_bclk_ext = "/i2stx_bclk_ext"; | |
| i2stx_lrck_ext = "/i2stx_lrck_ext"; | |
| i2srx_bclk_ext = "/i2srx_bclk_ext"; | |
| i2srx_lrck_ext = "/i2srx_lrck_ext"; | |
| tdm_ext = "/tdm_ext"; | |
| mclk_ext = "/mclk_ext"; | |
| jtag_tck_inner = "/jtag_tck_inner"; | |
| bist_apb = "/bist_apb"; | |
| stg_apb = "/stg_apb"; | |
| gmac0_rmii_refin = "/gmac0_rmii_refin"; | |
| gmac0_rgmii_rxin = "/gmac0_rgmii_rxin"; | |
| clk_rtc = "/clk_rtc"; | |
| hdmitx0_pixelclk = "/hdmitx0_pixelclk"; | |
| mipitx_dphy_rxesc = "/mipitx_dphy_rxesc"; | |
| mipitx_dphy_txbytehs = "/mipitx_dphy_txbytehs"; | |
| cpus = "/cpus"; | |
| cpu0 = "/cpus/cpu@0"; | |
| cpu0intctrl = "/cpus/cpu@0/interrupt-controller"; | |
| cpu1 = "/cpus/cpu@1"; | |
| cpu1intctrl = "/cpus/cpu@1/interrupt-controller"; | |
| cpu2 = "/cpus/cpu@2"; | |
| cpu2intctrl = "/cpus/cpu@2/interrupt-controller"; | |
| cpu3 = "/cpus/cpu@3"; | |
| cpu3intctrl = "/cpus/cpu@3/interrupt-controller"; | |
| cpu4 = "/cpus/cpu@4"; | |
| cpu4intctrl = "/cpus/cpu@4/interrupt-controller"; | |
| soc = "/soc"; | |
| cachectrl = "/soc/cache-controller@2010000"; | |
| aon_syscon = "/soc/aon_syscon@17010000"; | |
| stg_syscon = "/soc/stg_syscon@10240000"; | |
| sys_syscon = "/soc/sys_syscon@13030000"; | |
| clint = "/soc/clint@2000000"; | |
| plic = "/soc/plic@c000000"; | |
| clkgen = "/soc/clock-controller"; | |
| clkvout = "/soc/clock-controller@295C0000"; | |
| clkisp = "/soc/clock-controller@19810000"; | |
| qspi = "/soc/spi@13010000"; | |
| nor_flash = "/soc/spi@13010000/nor-flash@0"; | |
| otp = "/soc/otp@17050000"; | |
| usbdrd30 = "/soc/usbdrd"; | |
| usbdrd_cdns3 = "/soc/usbdrd/usb@10100000"; | |
| timer = "/soc/timer@13050000"; | |
| wdog = "/soc/wdog@13070000"; | |
| rtc = "/soc/rtc@17040000"; | |
| pmu = "/soc/pmu@17030000"; | |
| uart0 = "/soc/serial@10000000"; | |
| uart1 = "/soc/serial@10010000"; | |
| uart2 = "/soc/serial@10020000"; | |
| uart3 = "/soc/serial@12000000"; | |
| uart4 = "/soc/serial@12010000"; | |
| uart5 = "/soc/serial@12020000"; | |
| dma = "/soc/dma-controller@16050000"; | |
| gpio = "/soc/gpio@13040000"; | |
| uart0_pins = "/soc/gpio@13040000/uart0-0"; | |
| mmc0_pins = "/soc/gpio@13040000/mmc0-pins"; | |
| sdcard1_pins = "/soc/gpio@13040000/sdcard1-pins"; | |
| gpioa = "/soc/gpio@17020000"; | |
| trng = "/soc/trng@1600C000"; | |
| sec_dma = "/soc/sec_dma@16008000"; | |
| crypto = "/soc/crypto@16000000"; | |
| i2c6 = "/soc/i2c@12060000"; | |
| i2c0 = "/soc/i2c@10030000"; | |
| i2c1 = "/soc/i2c@10040000"; | |
| i2c5 = "/soc/i2c5@12050000"; | |
| pmic = "/soc/i2c5@12050000/axp15060_reg@36"; | |
| sdio0 = "/soc/sdio0@16010000"; | |
| sdio1 = "/soc/sdio1@16020000"; | |
| vin_sysctl = "/soc/vin_sysctl@19800000"; | |
| jpu = "/soc/jpu@11900000"; | |
| vpu_dec = "/soc/vpu_dec@130A0000"; | |
| vpu_enc = "/soc/vpu_enc@130B0000"; | |
| rstgen = "/soc/reset-controller"; | |
| stmmac_axi_setup = "/soc/stmmac-axi-config"; | |
| gmac0 = "/soc/ethernet@16030000"; | |
| phy0 = "/soc/ethernet@16030000/ethernet-phy@0"; | |
| gmac1 = "/soc/ethernet@16040000"; | |
| phy1 = "/soc/ethernet@16040000/ethernet-phy@1"; | |
| gpu = "/soc/gpu@18000000"; | |
| can0 = "/soc/can@130d0000"; | |
| can1 = "/soc/can@130e0000"; | |
| tdm = "/soc/tdm@10090000"; | |
| spdif0 = "/soc/spdif0@100a0000"; | |
| pwmdac = "/soc/pwmdac@100b0000"; | |
| i2stx = "/soc/i2stx@100c0000"; | |
| pdm = "/soc/pdm@100d0000"; | |
| i2srx_3ch = "/soc/i2srx_3ch@100e0000"; | |
| i2stx_4ch0 = "/soc/i2stx_4ch0@120b0000"; | |
| i2stx_4ch1 = "/soc/i2stx_4ch1@120c0000"; | |
| ptc = "/soc/pwm@120d0000"; | |
| spdif_transmitter = "/soc/spdif_transmitter"; | |
| spdif_receiver = "/soc/spdif_receiver"; | |
| pwmdac_codec = "/soc/pwmdac-transmitter"; | |
| dmic_codec = "/soc/dmic_codec"; | |
| spi0 = "/soc/spi@10060000"; | |
| pcie0 = "/soc/pcie@2B000000"; | |
| pcie1 = "/soc/pcie@2C000000"; | |
| mailbox_contrl0 = "/soc/mailbox@0"; | |
| mailbox_client0 = "/soc/mailbox_client@0"; | |
| dssctrl = "/soc/dssctrl@295B0000"; | |
| hdmi_output = "/soc/hdmi-output"; | |
| dc8200 = "/soc/dc8200@29400000"; | |
| mipi_dphy = "/soc/mipi-dphy@295e0000"; | |
| mipi_dsi = "/soc/mipi@295d0000"; | |
| dsi_out_port = "/soc/mipi@295d0000/port/endpoint"; | |
| mipi_panel = "/soc/mipi@295d0000/panel@0"; | |
| hdmi = "/soc/hdmi@29590000"; | |
| sound = "/soc/snd-card"; | |
| sndcpu0 = "/soc/snd-card/simple-audio-card,dai-link@0/cpu"; | |
| co_process = "/soc/e24@0"; | |
| dmc = "/soc/dmc@100b0000"; | |
| }; | |
| }; |
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