alternating counters

alt.v

/*
 * Generated by Digital. Don't modify this file!
 * Any changes will be lost if this file is regenerated.
 */

module DIG_CounterPreset #(
    parameter Bits = 2,
    parameter maxValue = 4
)
(
    input C,
    input en,
    input clr,
    input dir,
    input [(Bits-1):0] in,
    input ld,
    output [(Bits-1):0] out,
    output ovf
);

    reg [(Bits-1):0] count = 'h0;

    function [(Bits-1):0] maxVal (input [(Bits-1):0] maxv);
        if (maxv == 0)
            maxVal = (1 << Bits) - 1;
        else
            maxVal = maxv;
    endfunction

    assign out = count;
    assign ovf = ((count == maxVal(maxValue) & dir == 1'b0)
                  | (count == 'b0 & dir == 1'b1))? en : 1'b0;

    always @ (posedge C) begin
        if (clr == 1'b1)
            count <= 'h0;
        else if (ld == 1'b1)
            count <= in;
        else if (en == 1'b1) begin
            if (dir == 1'b0) begin
                if (count == maxVal(maxValue))
                    count <= 'h0;
                else
                    count <= count + 1'b1;
            end
            else begin
                if (count == 'h0)
                    count <= maxVal(maxValue);
                else
                    count <= count - 1;
            end
        end
    end
endmodule

module DIG_JK_FF
#(
    parameter Default = 1'b0
)
(
   input J,
   input C,
   input K,
   output Q,
   output \~Q
);
    reg state;

    assign Q = state;
    assign \~Q = ~state;

    always @ (posedge C) begin
        if (~J & K)
            state <= 1'b0;
         else if (J & ~K)
            state <= 1'b1;
         else if (J & K)
            state <= ~state;
    end

    initial begin
        state = Default;
    end
endmodule


module alt (
  input CLK,
  input \~RST ,
  output Q1,
  output Q2
);
  wire C;
  wire s0;
  wire [3:0] s1;
  wire s2;
  wire s3;
  wire [3:0] s4;
  wire s5;
  wire s6;
  wire s7;
  wire s8;
  wire s9;
  wire RST;
  assign RST = ~ \~RST ;
  assign C = (RST ^ CLK);
  DIG_CounterPreset #(
    .Bits(4),
    .maxValue(15)
  )
  DIG_CounterPreset_i0 (
    .en( 1'b1 ),
    .C( C ),
    .dir( 1'b0 ),
    .in( 4'b0 ),
    .ld( 1'b0 ),
    .clr( s0 ),
    .out( s1 ),
    .ovf( s2 )
  );
  DIG_CounterPreset #(
    .Bits(4),
    .maxValue(15)
  )
  DIG_CounterPreset_i1 (
    .en( 1'b1 ),
    .C( C ),
    .dir( 1'b0 ),
    .in( 4'b0 ),
    .ld( 1'b0 ),
    .clr( s3 ),
    .out( s4 ),
    .ovf( s5 )
  );
  DIG_JK_FF #(
    .Default(0)
  )
  DIG_JK_FF_i2 (
    .J( s6 ),
    .C( C ),
    .K( s2 ),
    .Q( Q1 ),
    .\~Q ( s7 )
  );
  DIG_JK_FF #(
    .Default(0)
  )
  DIG_JK_FF_i3 (
    .J( s2 ),
    .C( C ),
    .K( s8 ),
    .Q( Q2 ),
    .\~Q ( s9 )
  );
  assign s6 = (s5 | RST);
  assign s0 = (RST | s7);
  assign s3 = (RST | s9);
  assign s8 = (RST | s5);
endmodule