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Zilog Z16M2720ASC OY flags decoded
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| 00h: ICR0.EN_ATA_BHE|EN_CTR_IRQ|EN_RDY_BSY|EN_OVERIDE3 (ICR0.EN_RDY_BSY|EN_OVERIDE3|CLOCK_IN|CLOCK1|CLOCK0) | |
| 01h: IER.EN_INPACK (IER.UNSET) | |
| 02h: ICR1.UNSET | |
| 03h: ICR2._R7|EN_INVERT_ATRST|EN_ATT_MODE|EN_INDP_MODE (ICR2.PCMCIA_IO8) | |
| 04h: ICR3.UNSET | |
| 05h: CCRBaseAddress.EN_CRR_A10 (CCRBaseAddress.CCR_BASE_0000) | |
| 06h: 00h | |
| 07h: 00h | |
| 08h: 00h | |
| 09h: 00h | |
| 0Ah: CCR0.UNSET | |
| 0Bh: CCR1.UNSET (CCR1.IOIS8) | |
| 0Ch: CCR2.UNSET | |
| 0Dh: CCR3.UNSET | |
| 0Eh: 00h | |
| 0Fh: 00h | |
| 10h: W1CR.NRWAIT7 (W1CR.DIS_PAC1) | |
| 11h: W1SAL.UNSET | |
| 12h: W1SRAM.UNSET | |
| 13h: W1RAL.UNSET | |
| 14h: W2CR.DIS_PAC2 | |
| 15h: W2SAL.UNSET | |
| 16h: W2SRAM.UNSET | |
| 17h: W2RAL.UNSET | |
| 18h: W3CR.DIS_PAC3 | |
| 19h: W3SAL.UNSET | |
| 1Ah: W3SRAM.UNSET | |
| 1Bh: W3RAL.UNSET | |
| 1Ch: 00h | |
| 1Dh: 00h | |
| 1Eh: 1Ch | |
| 1Fh: 00h | |
| 20h: 00h | |
| 21h: 00h | |
| 22h: 00h | |
| 23h: 40h (00h) | |
| 24h: 00h | |
| 25h: 00h | |
| 26h: 82h (00h) | |
| 27h: FFh (00h) | |
| 28h: DDCR.UNSET | |
| 29h: 00h | |
| 2Ah: 00h | |
| 2Bh: PMCR.EN_EXPD_POL|EN_EXT_PD (PMCR.EN_8BIT_MODE) | |
| 2Ch: ICR4.UNSET | |
| 2Dh: CICR1.UNSET | |
| 2Eh: CICR2.UNSET (CICR2.EN_IO_INDP_INDX) | |
| 2Fh: BCR2.EN_BHE_POL (BCR2.UNSET) |
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Values in brackets are from the CardBarker firmware.