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ytsuboi/DAP_config.patch

Created April 2, 2013 09:33
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a patch for DAP_config.h of NXP's AN11321, to get works on my CMSIS-DAP adapter.
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README.md
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DAP_config.patch
--- DAP_config.h.orig 2013-04-02 16:54:01.248627100 +0900
+++ DAP_config.h 2013-03-31 13:48:38.999248900 +0900
@@ -38,6 +38,7 @@
//#include <LPC43xx.H> // Debug Unit Cortex-M Processor Header File
#include <LPC11Uxx.h>
+#include "gpio.h"
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
/// This value is used to calculate the SWD/JTAG clock speed.
@@ -57,7 +58,7 @@
/// Indicate that JTAG communication mode is available at the Debug Port.
/// This information is returned by the command ¥ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
@@ -136,8 +137,8 @@
#define PIN_SWDIO_TMS_BIT 20
// SWDIO Output Enable Pin PIO1_21
-#define PIN_SWDIO_OE_PORT 1
-#define PIN_SWDIO_OE_BIT 21
+//#define PIN_SWDIO_OE_PORT 1
+//#define PIN_SWDIO_OE_BIT 21
// TDI Pin PIO1_22
#define PIN_TDI_PORT 1
@@ -156,8 +157,8 @@
#define PIN_nRESET_BIT 26
// nRESET Output Enable Pin PIO1_27
-#define PIN_nRESET_OE_PORT 1
-#define PIN_nRESET_OE_BIT 27
+//#define PIN_nRESET_OE_PORT 1
+//#define PIN_nRESET_OE_BIT 27
// Debug Unit LEDs
@@ -241,10 +242,10 @@
static __inline void PORT_OFF (void) {
LPC_GPIO->SET[PIN_SWCLK_TCK_PORT] = (1 << PIN_SWCLK_TCK_BIT);
LPC_GPIO->SET[PIN_SWDIO_TMS_PORT] = (1 << PIN_SWDIO_TMS_BIT);
- LPC_GPIO->SET[PIN_SWDIO_OE_PORT] = (1 << PIN_SWDIO_OE_BIT);
+// LPC_GPIO->SET[PIN_SWDIO_OE_PORT] = (1 << PIN_SWDIO_OE_BIT);
LPC_GPIO->SET[PIN_TDI_PORT] = (1 << PIN_TDI_BIT);
LPC_GPIO->DIR[PIN_nRESET_PORT] &= ‾(1 << PIN_nRESET_BIT);
- LPC_GPIO->CLR[PIN_nRESET_OE_PORT] = (1 << PIN_nRESET_OE_BIT);
+// LPC_GPIO->CLR[PIN_nRESET_OE_PORT] = (1 << PIN_nRESET_OE_BIT);
}
@@ -254,21 +255,24 @@
¥return Current status of the SWCLK/TCK DAP hardware I/O pin.
*/
static __forceinline uint32_t PIN_SWCLK_TCK_IN (void) {
- return ((LPC_GPIO->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1);
+ // return ((LPC_GPIO->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1);
+ return ( GPIOGetPinValue(1,PIN_SWCLK_TCK_BIT) );
}
/** SWCLK/TCK I/O pin: Set Output to High.
Set the SWCLK/TCK DAP hardware I/O pin to high level.
*/
static __forceinline void PIN_SWCLK_TCK_SET (void) {
- LPC_GPIO->SET[PIN_SWCLK_TCK_PORT] = 1 << PIN_SWCLK_TCK_BIT;
+ //LPC_GPIO->SET[PIN_SWCLK_TCK_PORT] = 1 << PIN_SWCLK_TCK_BIT;
+ GPIOSetBitValue(1,PIN_SWCLK_TCK_BIT,1);
}
/** SWCLK/TCK I/O pin: Set Output to Low.
Set the SWCLK/TCK DAP hardware I/O pin to low level.
*/
static __forceinline void PIN_SWCLK_TCK_CLR (void) {
- LPC_GPIO->CLR[PIN_SWCLK_TCK_PORT] = 1 << PIN_SWCLK_TCK_BIT;
+ //LPC_GPIO->CLR[PIN_SWCLK_TCK_PORT] = 1 << PIN_SWCLK_TCK_BIT;
+ GPIOSetBitValue(1,PIN_SWCLK_TCK_BIT,0);
}
@@ -279,20 +283,23 @@
*/
static __forceinline uint32_t PIN_SWDIO_TMS_IN (void) {
return ((LPC_GPIO->PIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT) & 1);
+ //return ( GPIOGetPinValue(1,PIN_SWDIO_TMS_BIT) );
}
/** SWDIO/TMS I/O pin: Set Output to High.
Set the SWDIO/TMS DAP hardware I/O pin to high level.
*/
static __forceinline void PIN_SWDIO_TMS_SET (void) {
- LPC_GPIO->SET[PIN_SWDIO_TMS_PORT] = 1 << PIN_SWDIO_TMS_BIT;
+ //LPC_GPIO->SET[PIN_SWDIO_TMS_PORT] = 1 << PIN_SWDIO_TMS_BIT;
+ GPIOSetBitValue(1,PIN_SWDIO_TMS_BIT,1);
}
/** SWDIO/TMS I/O pin: Set Output to Low.
Set the SWDIO/TMS DAP hardware I/O pin to low level.
*/
static __forceinline void PIN_SWDIO_TMS_CLR (void) {
- LPC_GPIO->CLR[PIN_SWDIO_TMS_PORT] = 1 << PIN_SWDIO_TMS_BIT;
+ //LPC_GPIO->CLR[PIN_SWDIO_TMS_PORT] = 1 << PIN_SWDIO_TMS_BIT;
+ GPIOSetBitValue(1,PIN_SWDIO_TMS_BIT,0);
}
/** SWDIO I/O pin: Get Input (used in SWD mode only).
@@ -314,7 +321,8 @@
called prior ¥ref PIN_SWDIO_OUT function calls.
*/
static __forceinline void PIN_SWDIO_OUT_ENABLE (void) {
- LPC_GPIO->SET[PIN_SWDIO_OE_PORT] = 1 << PIN_SWDIO_OE_BIT;
+// LPC_GPIO->SET[PIN_SWDIO_OE_PORT] = 1 << PIN_SWDIO_OE_BIT;
+ GPIOSetDir( 1, PIN_SWDIO_TMS_BIT, 1 );
}
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -322,7 +330,8 @@
called prior ¥ref PIN_SWDIO_IN function calls.
*/
static __forceinline void PIN_SWDIO_OUT_DISABLE (void) {
- LPC_GPIO->CLR[PIN_SWDIO_OE_PORT] = 1 << PIN_SWDIO_OE_BIT;
+// LPC_GPIO->CLR[PIN_SWDIO_OE_PORT] = 1 << PIN_SWDIO_OE_BIT;
+ GPIOSetDir( 1, PIN_SWDIO_TMS_BIT, 0 );
}
@@ -386,13 +395,16 @@
- 1: release device hardware reset.
*/
static __forceinline void PIN_nRESET_OUT (uint32_t bit) {
- if (bit) {
- LPC_GPIO->DIR[PIN_nRESET_PORT] &= ‾(1 << PIN_nRESET_BIT);
- LPC_GPIO->CLR[PIN_nRESET_OE_PORT] = (1 << PIN_nRESET_OE_BIT);
+ if (bit & 1) {
+ //LPC_GPIO->DIR[PIN_nRESET_PORT] &= ‾(1 << PIN_nRESET_BIT);
+ //LPC_GPIO->CLR[PIN_nRESET_OE_PORT] = (1 << PIN_nRESET_OE_BIT);
+ GPIOSetDir( 1, PIN_nRESET_BIT, 0 ); //INPUT
} else {
- LPC_GPIO->SET[PIN_nRESET_OE_PORT] = (1 << PIN_nRESET_OE_BIT);
- LPC_GPIO->DIR[PIN_nRESET_PORT] |= (1 << PIN_nRESET_BIT);
- }
+ //LPC_GPIO->SET[PIN_nRESET_OE_PORT] = (1 << PIN_nRESET_OE_BIT);
+ //LPC_GPIO->DIR[PIN_nRESET_PORT] |= (1 << PIN_nRESET_BIT);
+ GPIOSetDir( 1, PIN_nRESET_BIT, 1 ); //OUTPUT
+ GPIOSetBitValue(1,PIN_nRESET_BIT,0);
+ }
}
///@}
@@ -417,7 +429,8 @@
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
*/
static __inline void LED_CONNECTED_OUT (uint32_t bit) {
- LPC_GPIO->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = bit;
+ //LPC_GPIO->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = bit;
+ GPIOSetBitValue(0,LED_CONNECTED_BIT,bit);
}
/** Debug Unit: Set status Target Running LED.
@@ -427,7 +440,8 @@
*/
static __inline void LED_RUNNING_OUT (uint32_t bit) {
//; // Not available
- LPC_GPIO->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = bit;
+ //LPC_GPIO->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = bit;
+ GPIOSetBitValue(0,LEDRUNNING_CONNECTED_BIT,bit);
}
///@}
@@ -469,23 +483,28 @@
/* nRESET_OE as output (low level) */
LPC_GPIO->SET[PIN_SWCLK_TCK_PORT] = (1 << PIN_SWCLK_TCK_BIT);
LPC_GPIO->SET[PIN_SWDIO_TMS_PORT] = (1 << PIN_SWDIO_TMS_BIT);
- LPC_GPIO->SET[PIN_SWDIO_OE_PORT] = (1 << PIN_SWDIO_OE_BIT);
+// LPC_GPIO->SET[PIN_SWDIO_OE_PORT] = (1 << PIN_SWDIO_OE_BIT);
LPC_GPIO->SET[PIN_TDI_PORT] = (1 << PIN_TDI_BIT);
LPC_GPIO->CLR[PIN_nRESET_PORT] = (1 << PIN_nRESET_BIT);
- LPC_GPIO->CLR[PIN_nRESET_OE_PORT] = (1 << PIN_nRESET_OE_BIT);
+// LPC_GPIO->CLR[PIN_nRESET_OE_PORT] = (1 << PIN_nRESET_OE_BIT);
LPC_GPIO->DIR[PIN_SWCLK_TCK_PORT] |= (1 << PIN_SWCLK_TCK_BIT);
LPC_GPIO->DIR[PIN_SWDIO_TMS_PORT] |= (1 << PIN_SWDIO_TMS_BIT);
- LPC_GPIO->DIR[PIN_SWDIO_OE_PORT] |= (1 << PIN_SWDIO_OE_BIT);
+// LPC_GPIO->DIR[PIN_SWDIO_OE_PORT] |= (1 << PIN_SWDIO_OE_BIT);
LPC_GPIO->DIR[PIN_TDI_PORT] |= (1 << PIN_TDI_BIT);
LPC_GPIO->DIR[PIN_TDO_PORT] &= ‾(1 << PIN_TDO_BIT);
- LPC_GPIO->DIR[PIN_nRESET_PORT] &= ‾(1 << PIN_nRESET_BIT);
- LPC_GPIO->DIR[PIN_nRESET_OE_PORT] |= (1 << PIN_nRESET_OE_BIT);
+// LPC_GPIO->DIR[PIN_nRESET_PORT] &= ‾(1 << PIN_nRESET_BIT);
+ GPIOSetDir( 1, PIN_nRESET_BIT, 0 ); //Input
+// LPC_GPIO->DIR[PIN_nRESET_OE_PORT] |= (1 << PIN_nRESET_OE_BIT);
/* Configure: LED as output (turned off) */
- LPC_GPIO->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
- LPC_GPIO->DIR[LED_CONNECTED_PORT] |= (1 << LED_CONNECTED_BIT);
- LPC_GPIO->CLR[LEDRUNNING_CONNECTED_PORT] = (1 << LEDRUNNING_CONNECTED_BIT);
- LPC_GPIO->DIR[LEDRUNNING_CONNECTED_PORT] |= (1 << LEDRUNNING_CONNECTED_BIT);
+ //LPC_GPIO->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
+ GPIOSetBitValue(0,LED_CONNECTED_BIT,0);
+ //LPC_GPIO->DIR[LED_CONNECTED_PORT] |= (1 << LED_CONNECTED_BIT);
+ GPIOSetDir(0, LED_CONNECTED_BIT, 1 ); //OUTPUT
+ //LPC_GPIO->CLR[LEDRUNNING_CONNECTED_PORT] = (1 << LEDRUNNING_CONNECTED_BIT);
+ GPIOSetBitValue(0,LEDRUNNING_CONNECTED_BIT,0);
+ //LPC_GPIO->DIR[LEDRUNNING_CONNECTED_PORT] |= (1 << LEDRUNNING_CONNECTED_BIT);
+ GPIOSetDir(0, LEDRUNNING_CONNECTED_BIT, 1 ); //OUTPUT
}
/** Reset Target Device with custom specific I/O pin or command sequence.
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