ML50x_AD9980_Initialization

init_seq.txt

https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/ML507-AD9980-I2C-bus/td-p/30165

By miggae

Hi Tannous

 

Below, there are the ADC registers "writes" of a working example on ML507.

 

First, you'll find general initialisation values to be written at the beginning. After that, do write the monitor timing dependent register values (which I appended for 3 different resolutions: VGA, SVGA, XGA).

 

Best

Miggae

 

// Initialize AD9980

   0x1E, 0xA4 // Input and Power Control // 9980
  ,0x1F, 0x14 // Output_Control {[7:5]=output_mode, [4]=primary_out_en,[3]=secondary_out_en,[2:1]=drive_strength,[0]=clk_inv}   // 9980
  ,0x20, 0x01 // Output Select 2
  ,0x05, 0x40 // Red Gain
  ,0x06, 0x00
  ,0x07, 0x40 // Green Gain
  ,0x08, 0x00
  ,0x09, 0x40 // Blue Gain
  ,0x0A, 0x00

  ,0x1B, 0x33 // Clamp and Offset (auto-offset every 64 clamps)

  ,0x0B, 0x02 // Red Offset  
  ,0x0C, 0x00
  ,0x0D, 0x02 // Green Offset  
  ,0x0E, 0x00
  ,0x0F, 0x02 // Blue Offset  
  ,0x10, 0x00

  ,0x18, 0x00
  ,0x12, 0x80 // Hsync control

 

  //analog 640x480P60 (VGA)
   0x01, 0x32 // PLL_div_msb {[7:0]=pll_div[11:4] }    // 800
  ,0x02, 0x00 // PLL_div_lsb {[7:4]=pll_div[3:0] }     // 800
  ,0x03, 0x48 // Clk_Gen_Ctrl {[7:6]=vco_range, [5:3]=charge_pump_current, [2]=ext_clk_en}
  ,0x04, 0xA0 // Phase_Adjust {[7:3]=phase_adjust}
  ,0x12, 0x10 // Hsync Control {...,[3]= hsync_out polarity} 
  ,0x13, 0x60 // Hsync_Duration {[7:0]= hsync_pulsewidth_duration }
  ,0x14, 0x10 // Vsync Control {...,[3]= vsync_out polarity}
  ,0x19, 0x04 // Clamp_Placement {[7:0]= clamp_placement }  
  ,0x1A, 0x1A // Clamp_Duration {[7:0]= clamp_duration}

  //analog 800x600P60 (SVGA)
  ,0x01, 0x42 // PLL_div_msb {[7:0]=pll_div[11:4] }   
  ,0x02, 0x00 // PLL_div_lsb {[7:4]=pll_div[3:0] } 
  ,0x03, 0x48 // Clk_Gen_Ctrl {[7:6]=vco_range, [5:3]=charge_pump_current, [2]=ext_clk_en}  
  ,0x04, 0x80 // Phase_Adjust {[7:3]=phase_adjust}
  ,0x12, 0x18 // Hsync Control {...,[3]= hsync_out polarity} 
  ,0x13, 0x80 // Hsync_Duration {[7:0]= hsync_pulsewidth_duration }
  ,0x14, 0x18 // Vsync Control {...,[3]= vsync_out polarity}
  ,0x19, 0x04 // Clamp_Placement {[7:0]= clamp_placement }  
  ,0x1A, 0x3C // Clamp_Duration {[7:0]= clamp_duration}

 

  //analog 1024x768P60 (XGA)
  ,0x01, 0x54 // PLL_div_msb {[7:0]=pll_div[11:4] }   
  ,0x02, 0x00 // PLL_div_lsb {[7:4]=pll_div[3:0] } 
  ,0x03, 0xA8 // Clk_Gen_Ctrl {[7:6]=vco_range, [5:3]=charge_pump_current, [2]=ext_clk_en}  
  ,0x04, 0x80 // Phase_Adjust {[7:3]=phase_adjust}
  ,0x12, 0x10 // Hsync Control {...,[3]= hsync_out polarity} 
  ,0x13, 0x88 // Hsync_Duration {[7:0]= hsync_pulsewidth_duration }
  ,0x14, 0x10 // Vsync Control {...,[3]= vsync_out polarity}
  ,0x19, 0x04 // Clamp_Placement {[7:0]= clamp_placement }  
  ,0x1A, 0x20 // Clamp_Duration {[7:0]= clamp_duration}