load and store for 8 bit ALU for ADD lab

load_store.v

module load_store(address,data,load_or_store);
input [7:0] address;
inout [7:0] data;
input load_or_store;
reg [7:0] regmem [255:0];
wire [7:0] address;

//assign load_or_store=1'b0;
always @(*)
begin
regmem[address] = load_or_store ? data : regmem[address];
end
assign data = load_or_store ? 8'bz : regmem[address];

endmodule

`module store_tb();
reg [7:0]address;
reg load_or_store;
store s(address,data,load_or_store);

initial begin
assign load_or_store=1;
assign address=0;
$finish(100);
end

initial begin
#5
load_or_store=0;
address=1;
//assign data=1?8'd1:8'bzzzzzzzz;
address=2;
//assign data=1?8'd2:8'bzzzzzzzz;
#5
load_or_store=1;
address=0;

#5
address=1;
#5
address=2;

end

	initial begin
	 $monitor("t=%3d x=%d,y=%d,z=%d \n",$time,address,data,load_or_store, );
	 end

endmodule`

not so working testbench for it ^^^