load and store for 8 bit ALU for ADD lab

load_store.v

module load_store(address,data,load_or_store);
input [7:0] address;
inout [7:0] data;
input load_or_store;
reg [7:0] regmem [255:0];
wire [7:0] address;

//assign load_or_store=1'b0;
always @(*)
begin
regmem[address] = load_or_store ? data : regmem[address];
end
assign data = load_or_store ? 8'bz : regmem[address];

endmodule

not so working testbench for it ^^^