This contains notes about using the Xilinx JTAG debugger for PCIe endpoints.
The Debug Options Tab in the DMA/Bridge Subsystem for PCI Express Product Guide (PG195) shows a JTAG Debugger option. That isn't present when using a XC7K160T. /opt/Xilinx/Vivado/2023.2/data/ip/xilinx/xdma_v4_1/xgui/xdma_v4_1.tcl shows the debug_options_tab isn't visible for a KINTEX7 family (among others).
With a XC7K160T, the JTAG Debugger can be enabled for the AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055) but noted:
- Once full the trace buffer one full doesn't record any more transitions, and the only way to get new captures seems to be to re-load the FPGA. Removing the PCIe device, reloading the FPGA and then performing a PCI scan may be a way to get the FPGA to re-enumerate on the PCIe bus without rebooting the PC.
/opt/Xilinx/Vivado/2023.2/data/ip/xilinx/axi_pcie_v2_9/ttcl/pcie_debugger/debug_probes_v.ttclseems to be the template for the verilog source of the JTAG trace code. It has hard-codedMAX_NUM_LTSSM_TRACEandLTSSM_WDATA_WIDTHvalues for the size of the trace buffer. They are defined usinglocalparamwhich can't be modifed with efparam statements or module instance parameter value assignments as per Difference between "parameter" and "localparam".- Running
draw_ltssm.tclcan get some errors about expected state changes. E.g.:Warning: unexpected transition: From: HOT_RESET To : Timeout To Detect Warning: unexpected transition: From: HOT_RESET To : Timeout To Detect - Running
draw_reset.tclcan abort with ankey "20" not known in dictionaryerror. E.g. see 5.1. After the PC had run the BIOS, and was paused the Windows boot menu
In Vivado 2025.1 for a XC7K160T there is still no JTAG Debugger option for the DMA/Bridge Subsystem for PCI Express.
The memmapped_blkram design was re-built using Vivado 2025.1, instead of the previous Vivado 2023.3
After building with Vivado 2025.1 attempting source test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl fails with:
# get_static_info
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
ERROR: [Xicom 50-38] xicom: AXI TRANSACTION TIMED OUT
INFO: [Labtoolstcl 44-481] READ DATA is:
run_hw_axi: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:11 . Memory (MB): peak = 10787.668 ; gain = 0.000 ; free physical = 4918 ; free virtual = 22549
ERROR: [Common 17-39] 'run_hw_axi' failed due to earlier errors.
while executing
"run_hw_axi [get_hw_axi_txns rd_txn_lite]"
("for" body line 5)
invoked from within
"for {set i 0 } { $i < $txn_cnt } { set i [expr $i +1] } {
set temp_addr [format %.4X [expr $txn_base_addr + $i]]
# puts "Read Address 0x{$temp_addr..."
(procedure "get_static_info" line 8)
invoked from within
"get_static_info"
(file "test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl" line 108)
Trying to identify changes between the working v2023.2 and v2025.1 by using Beyond Comapre on the directories used for the build:
test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/ip_0/synth/msys_axi_pcie_0_0_jtag.vhdchanged fromjtag_axi_v1_2_18_jtag_axitojtag_axi_v1_2_22_jtag_axi- The draw_ltssm.tcl, draw_reset.tcl, draw_rxdet.tcl and test_rd.tcl in
test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0are identical. These are the scripts read and decode the register values read via the JTAG debugger. - The msys_axi_pcie_0_0_debug_axi4l_s.v, msys_axi_pcie_0_0_debug_probes.v and msys_axi_pcie_0_0_debug_wrapper.v files in the
test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/sourcedirectory only differ in the year in a file header comment. These are the IP source files which provide trace memory, and a AXI interface to read the trace memory.
Attempting to issue a reset doesn't prevent the errors:
reset_hw_axi [get_hw_axis hw_axi_1]
source -notrace test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl
ERROR: [Xicom 50-38] xicom: AXI TRANSACTION TIMED OUT
INFO: [Labtoolstcl 44-481] READ DATA is:
run_hw_axi: Time (s): cpu = 00:00:00.8 ; elapsed = 00:00:11 . Memory (MB): peak = 11007.723 ; gain = 0.000 ; free physical = 20103 ; free virtual = 28974
ERROR: [Common 17-39] 'run_hw_axi' failed due to earlier errors.
while executing
"run_hw_axi [get_hw_axi_txns rd_txn_lite]"
(procedure "get_static_info" line 12)
invoked from within
"get_static_info"
(file "test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl" line 108)
Due to the issue with the PCIe JTAG debugger failing when tried to upgrade from Vivado 2023.2 to 2025.1, tried intermediate versions.
The memmapped_blkram design was re-built using Vivado 2024.1.
The pcie_debugger TCL scripts produced results which looked correct, and committed the changes.
The memmapped_blkram design was re-built using Vivado 2024.2.
Running source test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl results in all values being returned as zeros.
report_hw_axi_txn in the Vivado Design Suite Tcl Command Reference Guide (UG835) contains:
The JTAG to AXI Master core can only be controlled using Tcl commands. You can issue AXI read and write transactions using the
create_hw_axi_txnscommand. However, before issuing these commands, it is important to reset the JTAG to AXI Master core using thereset_hw_axicommand.
The test_rd.tcl script doesn't use reset_hw_axi. Attempted to use the reset command before running the test_rd.tcl, but that still resulted in the data reading as all zeros:
reset_hw_axi [get_hw_axis hw_axi_1]
source -notrace test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
phy_lane : 0
width : 00
speed : 00
Start with the memmapped_blkram rebuild.tcl created by v2024.1.
Remove the project:
$ git clean -f -d -x
Create the project using v2024.1
$ /opt/Xilinx/Vivado/2024.1/bin/vivado -source rebuild.tcl
After v2024.1 had created the project, exited Vivado without starting the build. I.e. the IP outputs hadn't been created.
Open the project created with v2024.1, using v2024.2:
$ /opt/Xilinx/Vivado/2024.2/bin/vivado test_board/test_board.xpr
At the Older Project Version dialog selected Automatically upgrade to the current version.
report_ip_status resulted in:
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part |
| | | | Log | | Version | | License | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_bram_ctrl_0_0 | IP revision change | Upgrade IP | *(1) | AXI BRAM | 4.1 | 4.1 (Rev. 11) | Included | xc7k160tfbg676-2 |
| | | | | Controller | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_bram_ctrl_1_0 | IP revision change | Upgrade IP | *(2) | AXI BRAM | 4.1 | 4.1 (Rev. 11) | Included | xc7k160tfbg676-2 |
| | | | | Controller | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_bram_ctrl_2_0 | IP revision change | Upgrade IP | *(3) | AXI BRAM | 4.1 | 4.1 (Rev. 11) | Included | xc7k160tfbg676-2 |
| | | | | Controller | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_pcie_0_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(4) | AXI Memory Mapped | 2.9 | 2.9 (Rev. 12) | Included | xc7k160tfbg676-2 |
| | | | | To PCI Express | (Rev. | | | |
| | | | | | 11) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_smc_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(5) | AXI SmartConnect | 1.0 | 1.0 (Rev. 25) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 23) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_blk_mem_gen_0_0 | IP revision change | Upgrade IP | *(6) | Block Memory | 8.4 | 8.4 (Rev. 9) | Included | xc7k160tfbg676-2 |
| | | | | Generator | (Rev. | | | |
| | | | | | 8) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_blk_mem_gen_1_0 | IP revision change | Upgrade IP | *(7) | Block Memory | 8.4 | 8.4 (Rev. 9) | Included | xc7k160tfbg676-2 |
| | | | | Generator | (Rev. | | | |
| | | | | | 8) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_blk_mem_gen_2_0 | IP revision change | Upgrade IP | *(8) | Block Memory | 8.4 | 8.4 (Rev. 9) | Included | xc7k160tfbg676-2 |
| | | | | Generator | (Rev. | | | |
| | | | | | 8) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_rst_mig_7series_0_125M_0 | IP revision change | Upgrade IP | *(9) | Processor System | 5.0 | 5.0 (Rev. 16) | Included | xc7k160tfbg676-2 |
| | | | | Reset | (Rev. | | | |
| | | | | | 15) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_util_ds_buf_2_0 | IP revision change | Upgrade IP | *(10) | Utility Buffer | 2.2 | 2.2 (Rev. 7) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 32) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_pcie_0_0_jtag | IP revision change | Upgrade parent IP | *(11) | JTAG to AXI Master | 1.2 | 1.2 (Rev. 20) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 19) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_arsw_0 | Up-to-date | No changes required | *(12) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7k160tfbg676-2 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 8) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_awsw_0 | Up-to-date | No changes required | *(13) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7k160tfbg676-2 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 8) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_bsw_0 | Up-to-date | No changes required | *(14) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7k160tfbg676-2 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 8) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m00arn_0 | IP revision change | Repackage parent IP | *(15) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m00awn_0 | IP revision change | Repackage parent IP | *(16) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m00bn_0 | IP revision change | Repackage parent IP | *(17) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m00e_0 | IP revision change | Repackage parent IP | *(18) | SC EXIT | 1.0 | 1.0 (Rev. 16) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 15) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m00rn_0 | IP revision change | Repackage parent IP | *(19) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m00s2a_0 | Up-to-date | No changes required | *(20) | SmartConnect | 1.0 | 1.0 (Rev. 10) | Included | xc7k160tfbg676-2 |
| | | | | SC2AXI Bridge | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m00wn_0 | IP revision change | Repackage parent IP | *(21) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m01arn_0 | IP revision change | Repackage parent IP | *(22) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m01awn_0 | IP revision change | Repackage parent IP | *(23) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m01bn_0 | IP revision change | Repackage parent IP | *(24) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m01e_0 | IP revision change | Repackage parent IP | *(25) | SC EXIT | 1.0 | 1.0 (Rev. 16) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 15) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m01rn_0 | IP revision change | Repackage parent IP | *(26) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m01s2a_0 | Up-to-date | No changes required | *(27) | SmartConnect | 1.0 | 1.0 (Rev. 10) | Included | xc7k160tfbg676-2 |
| | | | | SC2AXI Bridge | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m01wn_0 | IP revision change | Repackage parent IP | *(28) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m02arn_0 | IP revision change | Repackage parent IP | *(29) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m02awn_0 | IP revision change | Repackage parent IP | *(30) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m02bn_0 | IP revision change | Repackage parent IP | *(31) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m02e_0 | IP revision change | Repackage parent IP | *(32) | SC EXIT | 1.0 | 1.0 (Rev. 16) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 15) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m02rn_0 | IP revision change | Repackage parent IP | *(33) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m02s2a_0 | Up-to-date | No changes required | *(34) | SmartConnect | 1.0 | 1.0 (Rev. 10) | Included | xc7k160tfbg676-2 |
| | | | | SC2AXI Bridge | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_m02wn_0 | IP revision change | Repackage parent IP | *(35) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_one_0 | Up-to-date | No changes required | *(36) | Constant | 1.1 | 1.1 (Rev. 9) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 9) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_psr_aclk_0 | IP revision change | Repackage parent IP | *(37) | Processor System | 5.0 | 5.0 (Rev. 16) | Included | xc7k160tfbg676-2 |
| | | | | Reset | (Rev. | | | |
| | | | | | 15) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_rsw_0 | Up-to-date | No changes required | *(38) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7k160tfbg676-2 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 8) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_s00a2s_0 | Up-to-date | No changes required | *(39) | SmartConnect | 1.0 | 1.0 (Rev. 10) | Included | xc7k160tfbg676-2 |
| | | | | AXI2SC Bridge | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_s00mmu_0 | IP revision change | Repackage parent IP | *(40) | SC MMU | 1.0 | 1.0 (Rev. 14) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_s00sic_0 | IP revision change | Repackage parent IP | *(41) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 14) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_s00tr_0 | Up-to-date | No changes required | *(42) | SC | 1.0 | 1.0 (Rev. 11) | Included | xc7k160tfbg676-2 |
| | | | | TRANSACTION_REGULA | (Rev. | | | |
| | | | | | 11) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_sarn_0 | IP revision change | Repackage parent IP | *(43) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_sawn_0 | IP revision change | Repackage parent IP | *(44) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_sbn_0 | IP revision change | Repackage parent IP | *(45) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_srn_0 | IP revision change | Repackage parent IP | *(46) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_swn_0 | IP revision change | Repackage parent IP | *(47) | SmartConnect Node | 1.0 | 1.0 (Rev. 17) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_ed9b_wsw_0 | Up-to-date | No changes required | *(48) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7k160tfbg676-2 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 8) | | | |
+-------------------------------+------------------------------------------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
*(1) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/axi_bram_ctrl_v4_1/doc/axi_bram_ctrl_v4_1_changelog.txt
*(2) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/axi_bram_ctrl_v4_1/doc/axi_bram_ctrl_v4_1_changelog.txt
*(3) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/axi_bram_ctrl_v4_1/doc/axi_bram_ctrl_v4_1_changelog.txt
*(4) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/axi_pcie_v2_9/doc/axi_pcie_v2_9_changelog.txt
*(5) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/smartconnect_v1_0/doc/smartconnect_v1_0_changelog.txt
*(6) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/blk_mem_gen_v8_4/doc/blk_mem_gen_v8_4_changelog.txt
*(7) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/blk_mem_gen_v8_4/doc/blk_mem_gen_v8_4_changelog.txt
*(8) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/blk_mem_gen_v8_4/doc/blk_mem_gen_v8_4_changelog.txt
*(9) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(10) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/util_ds_buf_v2_2/doc/util_ds_buf_v2_2_changelog.txt
*(11) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/jtag_axi_v1_2/doc/jtag_axi_v1_2_changelog.txt
*(12) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt
*(13) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt
*(14) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt
*(15) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(16) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(17) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(18) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_exit_v1_0/doc/sc_exit_v1_0_changelog.txt
*(19) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(20) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_sc2axi_v1_0/doc/sc_sc2axi_v1_0_changelog.txt
*(21) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(22) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(23) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(24) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(25) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_exit_v1_0/doc/sc_exit_v1_0_changelog.txt
*(26) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(27) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_sc2axi_v1_0/doc/sc_sc2axi_v1_0_changelog.txt
*(28) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(29) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(30) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(31) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(32) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_exit_v1_0/doc/sc_exit_v1_0_changelog.txt
*(33) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(34) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_sc2axi_v1_0/doc/sc_sc2axi_v1_0_changelog.txt
*(35) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(36) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/xlconstant_v1_1/doc/xlconstant_v1_1_changelog.txt
*(37) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(38) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt
*(39) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_axi2sc_v1_0/doc/sc_axi2sc_v1_0_changelog.txt
*(40) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_mmu_v1_0/doc/sc_mmu_v1_0_changelog.txt
*(41) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_si_converter_v1_0/doc/sc_si_converter_v1_0_changelog.txt
*(42) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_transaction_regulator_v1_0/doc/sc_transaction_regulator_v1_0_changelog.txt
*(43) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(44) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(45) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(46) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(47) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt
*(48) /opt/Xilinx/Vivado/2024.2/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt
On the IP Status all IP is showing as requiring an upgrade. The tickboxes to allow opting of the upgrade for individual IPs are greyed out:
All IP is shown as being locked.
Start with the memmapped_blkram rebuild.tcl created by v2024.1.
Remove the project:
$ git clean -f -d -x
Create the project using v2024.1
$ /opt/Xilinx/Vivado/2024.1/bin/vivado -source rebuild.tcl
In v2024.1 selected Generate Output Products for the block design. After the generation had completed, exited v2024.1 and made a backup copy of the project:
$ cp -pr test_board/ test_board_2024.1-gen
Opened the project in v2024.2 and selected Automaticall upgrade to the current version:
$ /opt/Xilinx/Vivado/2024.2/bin/vivado test_board/test_board.xpr
The IP Status was still most IP cores as being unable to opt-out of the upgrade. Deselected all of the following for which it was possible to opt-out of the upgrade:
/axi_bram_ctrl_0/rst_mig_7_series_0_125M/util_ds_buf_2/axi_bram_ctrl_1/axi_bram_ctrl_2/axi_pcie_0
Then selected Upgrade Selected. Got the following and selected OK:
The following was in the Tcl Console after the upgrade:
WARNING: [BD 41-1661] One or more IPs have been locked in the design 'msys.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
msys_rst_mig_7series_0_125M_0
msys_axi_smc_0
msys_blk_mem_gen_0_0
msys_axi_bram_ctrl_0_0
msys_blk_mem_gen_1_0
msys_axi_bram_ctrl_1_0
msys_util_ds_buf_2_0
msys_blk_mem_gen_2_0
msys_axi_bram_ctrl_2_0
msys_axi_pcie_0_0
INFO: [Project 1-230] Project 'test_board.xpr' upgraded for this version of Vivado.
INFO: [Project 1-5579] Found utility IPs instantiated in one or more block designs which have equivalent inline hdl with improved performance and reduced diskspace. It is recommended to migrate these utility IPs to inline hdl using the command upgrade_project -migrate_to_inline_hdl. The utility IPs may be deprecated in future releases. More information on inline hdl is available in UG994.
open_project: Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 8006.793 ; gain = 526.555 ; free physical = 21946 ; free virtual = 29956
update_compile_order -fileset sources_1
report_ip_status -name ip_status
set_property USER_LOCKED 1 [get_ips msys_axi_bram_ctrl_0_0]
INFO: [IP_Flow 19-8015] Moving outputs for IP 'msys_axi_bram_ctrl_0_0' to '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/ip/msys_axi_bram_ctrl_0_0'
WARNING: [IP_Flow 19-2162] IP 'msys_axi_bram_ctrl_0_0' is locked:
* IP definition 'AXI BRAM Controller (4.1)' for IP 'msys_axi_bram_ctrl_0_0' (customized with software release 2024.1) has a different revision in the IP Catalog.
set_property USER_LOCKED 1 [get_ips msys_rst_mig_7series_0_125M_0]
INFO: [IP_Flow 19-8015] Moving outputs for IP 'msys_rst_mig_7series_0_125M_0' to '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/ip/msys_rst_mig_7series_0_125M_0'
WARNING: [IP_Flow 19-2162] IP 'msys_rst_mig_7series_0_125M_0' is locked:
* IP definition 'Processor System Reset (5.0)' for IP 'msys_rst_mig_7series_0_125M_0' (customized with software release 2024.1) has a different revision in the IP Catalog.
set_property USER_LOCKED 1 [get_ips msys_util_ds_buf_2_0]
INFO: [IP_Flow 19-8015] Moving outputs for IP 'msys_util_ds_buf_2_0' to '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/ip/msys_util_ds_buf_2_0'
WARNING: [IP_Flow 19-2162] IP 'msys_util_ds_buf_2_0' is locked:
* IP definition 'Utility Buffer (2.2)' for IP 'msys_util_ds_buf_2_0' (customized with software release 2024.1) has a different revision in the IP Catalog.
set_property USER_LOCKED 1 [get_ips msys_axi_pcie_0_0]
INFO: [IP_Flow 19-8015] Moving outputs for IP 'msys_axi_pcie_0_0' to '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/ip/msys_axi_pcie_0_0'
WARNING: [IP_Flow 19-2162] IP 'msys_axi_pcie_0_0_jtag' is locked:
* IP definition 'JTAG to AXI Master (1.2)' for IP 'msys_axi_pcie_0_0_jtag' (customized with software release 2024.1) has a different revision in the IP Catalog.
WARNING: [IP_Flow 19-2162] IP 'msys_axi_pcie_0_0' is locked:
* IP definition 'AXI Memory Mapped To PCI Express (2.9)' for IP 'msys_axi_pcie_0_0' (customized with software release 2024.1) has a different revision in the IP Catalog. * IP 'msys_axi_pcie_0_0' contains one or more locked subcores.
set_property USER_LOCKED 1 [get_ips msys_axi_bram_ctrl_1_0]
INFO: [IP_Flow 19-8015] Moving outputs for IP 'msys_axi_bram_ctrl_1_0' to '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/ip/msys_axi_bram_ctrl_1_0'
WARNING: [IP_Flow 19-2162] IP 'msys_axi_bram_ctrl_1_0' is locked:
* IP definition 'AXI BRAM Controller (4.1)' for IP 'msys_axi_bram_ctrl_1_0' (customized with software release 2024.1) has a different revision in the IP Catalog.
set_property USER_LOCKED 1 [get_ips msys_axi_bram_ctrl_2_0]
INFO: [IP_Flow 19-8015] Moving outputs for IP 'msys_axi_bram_ctrl_2_0' to '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/ip/msys_axi_bram_ctrl_2_0'
WARNING: [IP_Flow 19-2162] IP 'msys_axi_bram_ctrl_2_0' is locked:
* IP definition 'AXI BRAM Controller (4.1)' for IP 'msys_axi_bram_ctrl_2_0' (customized with software release 2024.1) has a different revision in the IP Catalog.
upgrade_ip [get_ips {msys_axi_smc_0 msys_blk_mem_gen_0_0 msys_blk_mem_gen_1_0 msys_blk_mem_gen_2_0}] -log ip_upgrade.log
Reading block design file </home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/msys.bd>...
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_0
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_1
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_2
Adding component instance block -- xilinx.com:ip:axi_pcie:2.9 - axi_pcie_0
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_1
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_2
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_mig_7series_0_125M
Adding component instance block -- xilinx.com:ip:util_ds_buf:2.2 - util_ds_buf_2
Successfully read diagram <msys> from block design file </home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/msys.bd>
Upgrading '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/msys.bd'
INFO: [IP_Flow 19-3422] Upgraded msys_axi_smc_0 (AXI SmartConnect 1.0) from revision 23 to revision 25
INFO: [IP_Flow 19-3422] Upgraded msys_blk_mem_gen_0_0 (Block Memory Generator 8.4) from revision 8 to revision 9
INFO: [IP_Flow 19-3422] Upgraded msys_blk_mem_gen_1_0 (Block Memory Generator 8.4) from revision 8 to revision 9
INFO: [IP_Flow 19-3422] Upgraded msys_blk_mem_gen_2_0 (Block Memory Generator 8.4) from revision 8 to revision 9
Wrote : </home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/msys.bd>
Wrote : </home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/ui/bd_2a9cc240.ui>
INFO: [Coretcl 2-1525] Wrote upgrade log to '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/ip_upgrade.log'.
upgrade_ip: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 8312.938 ; gain = 0.000 ; free physical = 19993 ; free virtual = 28136
Built the bitstream and test_rd.tcl read sensible values. Ableit the location of the pcie_debugger scripts directory had changed compared to the previous run, possibly due to IP being locked:
source -notrace test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl
couldn't read file "test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl": no such file or directory
source -notrace test_board/test_board.srcs/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
INFO: [Labtoolstcl 44-481] READ DATA is: 00000901
INFO: [Labtoolstcl 44-481] READ DATA is: 00000001
INFO: [Labtoolstcl 44-481] READ DATA is: 00000009
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00001001
INFO: [Labtoolstcl 44-481] READ DATA is: 0000abcd
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
phy_lane : 4
width : 04
speed : 02
Output of report_ip_status excluding the No changes required rows:
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part |
| | | | Log | | Version | | License | |
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_bram_ctrl_0_0 | Locked by user. IP revision change | Unlock BD Cell for upgrade. Upgrade IP | *(1) | AXI BRAM | 4.1 | 4.1 (Rev. 11) | Included | xc7k160tfbg676-2 |
| | | | | Controller | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_bram_ctrl_1_0 | Locked by user. IP revision change | Unlock BD Cell for upgrade. Upgrade IP | *(2) | AXI BRAM | 4.1 | 4.1 (Rev. 11) | Included | xc7k160tfbg676-2 |
| | | | | Controller | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_bram_ctrl_2_0 | Locked by user. IP revision change | Unlock BD Cell for upgrade. Upgrade IP | *(3) | AXI BRAM | 4.1 | 4.1 (Rev. 11) | Included | xc7k160tfbg676-2 |
| | | | | Controller | (Rev. | | | |
| | | | | | 10) | | | |
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_pcie_0_0 | Locked by user. IP revision change. IP contains locked subcore | Unlock BD Cell for upgrade. Upgrade IP | *(4) | AXI Memory Mapped | 2.9 | 2.9 (Rev. 12) | Included | xc7k160tfbg676-2 |
| | | | | To PCI Express | (Rev. | | | |
| | | | | | 11) | | | |
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_rst_mig_7series_0_125M_0 | Locked by user. IP revision change | Unlock BD Cell for upgrade. Upgrade IP | *(9) | Processor System | 5.0 | 5.0 (Rev. 16) | Included | xc7k160tfbg676-2 |
| | | | | Reset | (Rev. | | | |
| | | | | | 15) | | | |
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_util_ds_buf_2_0 | Locked by user. IP revision change | Unlock BD Cell for upgrade. Upgrade IP | *(10) | Utility Buffer | 2.2 | 2.2 (Rev. 7) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 32) | | | |
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| msys_axi_pcie_0_0_jtag | IP revision change | Upgrade parent IP | *(11) | JTAG to AXI Master | 1.2 | 1.2 (Rev. 20) | Included | xc7k160tfbg676-2 |
| | | | | | (Rev. | | | |
| | | | | | 19) | | | |
+-------------------------------+----------------------------------------------------------------+----------------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
Exited Vivado and saved a copy of the project:
$ cp -pr test_board/ test_board_2024.2-upgrade_opted_out
Re-opened the project from the previous step in v2024.2
On the IP Status window select to upgrade /axi_pcie_0 AXI Memory Mapped to PCI Express from 2.9 (Rev. 11) to 2.9 (Rev. 12). From the window, expect that to also upgrade the child IP JTAG to AXI Master from 1.2 (Rev. 19) to 1.2 (Rev. 20).
Tcl Console output:
set_property USER_LOCKED 0 [get_ips msys_axi_pcie_0_0]
INFO: [IP_Flow 19-8015] Moving outputs for IP 'msys_axi_pcie_0_0' to ''
WARNING: [IP_Flow 19-2162] IP 'msys_axi_pcie_0_0_jtag' is locked:
* IP definition 'JTAG to AXI Master (1.2)' for IP 'msys_axi_pcie_0_0_jtag' (customized with software release 2024.1) has a different revision in the IP Catalog.
WARNING: [IP_Flow 19-2162] IP 'msys_axi_pcie_0_0' is locked:
* IP 'msys_axi_pcie_0_0' was locked because its BD Cell is locked for upgrade. * IP definition 'AXI Memory Mapped To PCI Express (2.9)' for IP 'msys_axi_pcie_0_0' (customized with software release 2024.1) has a different revision in the IP Catalog. * IP 'msys_axi_pcie_0_0' contains one or more locked subcores.
upgrade_ip -vlnv xilinx.com:ip:axi_pcie:2.9 [get_ips msys_axi_pcie_0_0] -log ip_upgrade.log
Reading block design file </home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/msys.bd>...
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_0
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_1
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_2
Adding component instance block -- xilinx.com:ip:axi_pcie:2.9 - axi_pcie_0
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_1
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_2
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_mig_7series_0_125M
Adding component instance block -- xilinx.com:ip:util_ds_buf:2.2 - util_ds_buf_2
Successfully read diagram <msys> from block design file </home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/msys.bd>
Upgrading '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/msys.bd'
INFO: [IP_Flow 19-3422] Upgraded msys_axi_pcie_0_0 (AXI Memory Mapped To PCI Express 2.9) from revision 11 to revision 12
Wrote : </home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/test_board.srcs/sources_1/bd/msys/msys.bd>
INFO: [Coretcl 2-1525] Wrote upgrade log to '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_board/ip_upgrade.log'.
upgrade_ip: Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 8400.094 ; gain = 0.000 ; free physical = 16093 ; free virtual = 25989
While the console doesn't explicitly mention upgrading msys_axi_pcie_0_0_jtag the IP Status after the upgrade now reports as 1.2 (Rev. 20) which means has been upgraded.
After re-building the FPGA test_rd.tcl is now reading all zeros:
source -notrace test_board/test_board.srcs/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
phy_lane : 0
width : 00
speed : 00
An ILA was added to monitor the JTAX AXI interface in the design memmapped_blkram. When built with v2024.1:
- Timing constraints are met.
- test_rd.tcl returns sensible results.
- The ILA captures the AXI read transfers performed by test_rd.tcl. Albeit omitted to monitor the read address
The schematic shows a u_ila_0 chained to the dbg_hub:
When built with v2024.2:
- The timing constraints are not met for the
CLK_PCIe_100MHz_clk_p[0], which is the clock for the JTAG AXI and ILA:- Setup slack of -3.970 ns on u_ila_0 nets
- Hold slack of -10.501 ns on jtag_axi nets
- If load the bitstream the memory mapped PCIe endpoint works. However the JTAG AXI and ILA debug cores are not detected, with the console reporting:
INFO: [Labtools 27-1434] Device xc7k160t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3361] The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
The JTAG frequency is 6 MHz, and given the dubug cores are clocked at 100 MHz meets the following in Debug Cores Clocking Guidelines:
This clock synchronizes the internal state machine operation of the JTAG Boundary Scan (BSCAN) interface. You can choose the JTAG clock frequency in the Vivado Hardware Manager while connecting to the target device. If your design contains debug cores, ensure that the JTAG clock is 2.5x times slower than the debug hub clock.
Looking in both the v2024.1 and v2024.2, under Project Settings -> Implementation -> Settings the Strategy is Performance_NetDelayLow* (Vivado Implementation 2022).
In v2024.2 tried the following, none of which reduced timing closure failures nor removed the failure to find the debug cores:
- Various implenentation strategies as suggested by ILA Core and Timing Considerations.
- Reducing the amomunt of memory mapped blockram accessed by the PCIe endpoint, reduced the blockram usage from 323 out of 325 (99.38%) downto 48 out of 325 (14.77%).
- Increase the
C_INPUT_PIPE_STAGESproperty for the ILA from 1 to 4.
Based upon ILA Core and Timing Considerations tried changing the ILA settings. Changing from:
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores u_ila_0]To:
set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]Resulted in:
- For CLK_PCIe_100_MHz_clk_p:
- Setup being met
- Hold slack reducing to worst case of -1.601 ns
- When loaded the bitstream the
hw_axi_1core was detected. However, still failed to detect the ILA:WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device. - Attempting to run
test_rd.tclresulted in:ERROR: [Xicom 50-38] xicom: AXI TRANSACTION TIMED OUT - While the ILA Core and Timing Considerations article suggested increasing
C_INPUT_PIPE_STAGESstill resulted in the setup not being met.
The AXI debug probes are read only. memmapped_blkram commit 21e99df simplifed the AXI signals monitored to only:
m_axi_rdata[16]. While themsys_axi_pcie_0_0_debug_axi4l_smodule hasS_AXI_rdatain the interface as 32 bits, it usesassign S_AXI_rdata = {16'h0,trc_do};. So, with the most significants bits fixed as zeros assume the synthesis removes the top 16 bits from the net.m_axi_aradd[32]m_axi_rreadym_axi_rvalid
When built with v2024.1:
- test_rd.tcl returned sensible values
- The ILA capture the read transfers caused by test_rd.tcl
- The schematic for part of debug_wrapper_U showing the connections between
jtag_axi4l_m_instanddebug_axi4l_s_inst:
When built with v2024.2:
- Timing failed on CLK_PCIe_100_MHz_clk_p:
- Setup not met on 10 nets
- Hold not met on 10 nets
- After loading the bitstream the PCIe endpoint worked, but no debug cores were detected.
- The schematic for part of debug_wrapper_U showed the same connections between
jtag_axi4l_m_instanddebug_axi4l_s_instas for v2024.1
Attempting to build with v2025.1:
-
Failed with Opt Design error
[Chipscope 16-213] The debug port 'u_ila_0/probe1' has 32 unconnected channels (bits). This will cause errors during implementation.
-
There was also the critical warning:
[Common 17-162] Invalid option value specified for '-nets'[debug.xdc:18]
Which is on the
m_axi_araddr[15:0]net -
The schematic for part of debug_wrapper_U showing the connections between
jtag_axi4l_m_instanddebug_axi4l_s_inst:
The problem is that the following inputs to debug_axi4l_s_inst are connected to constants, instead of the output from jtag_axi4l_m_inst:
S_AXI_arvalidis 1S_AXI_araddr[31:0]is 0x00001020
The generated test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/source/msys_axi_pcie_0_0_debug_wrapper.v has the following block:
//debugging simulation
//translate off
initial begin
#4840;
force AXI_arvalid = 1'b1;
force AXI_araddr = 32'h1020;
while(~AXI_arready) @(posedge AXI_aclk);
force AXI_arvalid = 1'b0;
while (~AXI_rvalid) @(posedge AXI_aclk);
$display("%t get data %h, with response %h", $realtime, AXI_rdata, AXI_rresp);
force AXI_rready = 1'b1;
@(posedge AXI_aclk);
force AXI_rready = 1'b0;
repeat(20) @(posedge AXI_aclk);
// $finish;
end
//translate onWhere the above is forcing AXI_arvalid and AXI_araddr to the same constant values as seen on the schematic.
The test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/source/msys_axi_pcie_0_0_debug_wrapper.v generated by v2024.1 and v2025.1 is identical.
According to the TRANSLATE_OFF/TRANSLATE_ON OFF/ON section in Vivado Design Suite User Guide: Synthesis (UG901) the comment style to use is the following:
// synthesis translate_off
Code....
// synthesis translate_on
// synthesis off
Code....
// synthesis on
The contents of UG901 are the same for the v2024.1 and v2025.1 document versions of the above section.
Not sure if there has been a change in Vivado versions about comments may be used to disable translation.
The template for the generated msys_axi_pcie_0_0_debug_wrapper.v is Vivado/data/ip/xilinx/axi_pcie_v2_9/ttcl/pcie_debugger/debug_wrapper_v.ttcl in the v2025.1 installation.
The v2025.1 installation also has the same debug_wrapper_v.ttcl template in:
Vivado/data/ip/xilinx/pcie3_7x_v4_3/ttcl/pcie_debuggerVivado/data/ip/xilinx/pcie_7x_v3_3/ttcl/pcie_debugger
The 2018.2/data/ip/xilinx/axi_pcie_v2_9/ttcl/pcie_debugger/debug_wrapper_v.ttcl matches that from v2025.1, so no recent changes to the template. v2018.2 is the oldest Vivado version installed on the PC.
The generated msys_axi_pcie_0_0_debug_wrapper.v is marked read only in the Vivado. Attempted to edit the file outside of Vivado and remove the "debugging simulation" block. However, couldn't seem to get the edited file to fix the issue with the synthesis output.
Searching the installed v2025.1 IP for translate off finds the following:
$ grep -r "translate off" /opt/Xilinx/2025.1/Vivado/data/
/opt/Xilinx/2025.1/Vivado/data/sysgen/hdl/xlsgn.v://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/sysgen/hdl/xlsgn.v://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/sysgen/hdl/xlsgn.v://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/sysgen/hdl/kcpsm6.vhd:--synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/sysgen/hdl/kcpsm6.vhd: --synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/pcie3_7x_v4_3/ttcl/pcie_debugger/debug_wrapper_v.ttcl://translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mig_rld3_phy_v1_2/data/dlib/ultrascale/common/xiphy_files/mig_rld3_phy_v1_2_xiphy_byte_wrapper.sv://pragma translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/clk_gen_sim_v1_0/hdl/clk_gen_sim_v1_0_vl_rfs.sv:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/clk_gen_sim_v1_0/ttcl/top.ttcl://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_4/phy/xiphy/mem_v1_4_phy_xiphy_byte_wrapper.sv://pragma translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_4/ip/axi_tg/mem_v1_4_prbs_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_4/ip/axi_tg/mem_v1_4_boot_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_4/ip/axi_tg/mem_v1_4_custom_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_4/ip/axi_tg/mem_v1_4_axi_opcode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_4/ip/axi_tg/mem_v1_4_axi_wrapper.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_4/ip/axi_tg/mem_v1_4_axi_tg_top.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_4/ip/axi_tg/mem_v1_4_data_chk.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/sim_trig_v1_0/ttcl/traffic_shaping.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mig_ddrx_phy_v1_2/data/dlib/ultrascale/common/xiphy_files/mig_ddrx_phy_v1_2_xiphy_byte_wrapper.sv://pragma translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_3/phy/xiphy/mem_v1_3_phy_xiphy_byte_wrapper.sv://pragma translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_3/ip/axi_tg/mem_v1_3_boot_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_3/ip/axi_tg/mem_v1_3_data_chk.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_3/ip/axi_tg/mem_v1_3_prbs_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_3/ip/axi_tg/mem_v1_3_axi_tg_top.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_3/ip/axi_tg/mem_v1_3_custom_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_0/phy/xiphy/mem_v1_0_phy_xiphy_byte_wrapper.sv://pragma translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_1/phy/xiphy/mem_v1_1_phy_xiphy_byte_wrapper.sv://pragma translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/pcie_7x_v3_3/ttcl/pcie_debugger/debug_wrapper_v.ttcl://translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/hdl/hbm_v1_0_vl_rfs.sv:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/hdl/hbm_v1_0_vl_rfs.sv:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/hdl/hbm_v1_0_vl_rfs.sv:// // synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_syn.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/ttcl/example_top_sim.ttcl:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/verif/tg/adv_axi_tg/atg_cfg/hbm_atg_axi_for_stack_1.sv:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/verif/tg/adv_axi_tg/atg_cfg/hbm_atg_axi_for_stack_0.sv:// synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/hbm_v1_0/verif/tg/phy_only_tg/phy_tg.sv: //synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/axi_pcie_v2_9/ttcl/pcie_debugger/debug_wrapper_v.ttcl://translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mig_qdriip_phy_v1_2/data/dlib/ultrascale/common/xiphy_files/mig_qdriip_phy_v1_2_xiphy_byte_wrapper.sv://pragma translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_2/phy/xiphy/mem_v1_2_phy_xiphy_byte_wrapper.sv://pragma translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_2/ip/axi_tg/mem_v1_2_prbs_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_2/ip/axi_tg/mem_v1_2_axi_tg_top.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_2/ip/axi_tg/mem_v1_2_custom_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_2/ip/axi_tg/mem_v1_2_boot_mode_gen.sv://synthesis translate off
/opt/Xilinx/2025.1/Vivado/data/ip/xilinx/mem_v1_2/ip/axi_tg/mem_v1_2_data_chk.sv://synthesis translate off
The only case of //translate off is in the pcie_debugger/debug_wrapper_v.ttcl files. The others have a procedding synthesis or pragma.
Attempt to use modified IP by:
- Taking a copy:
$ cp -p /opt/Xilinx/2025.1/Vivado/data/ip/xilinx/axi_pcie_v2_9/ttcl/pcie_debugger/debug_wrapper_v.{ttcl,bak} - Editing to add a
synthesisprefix:$ diff /opt/Xilinx/2025.1/Vivado/data/ip/xilinx/axi_pcie_v2_9/ttcl/pcie_debugger/debug_wrapper_v.{ttcl,bak} 217c217 < //synthesis translate off --- > //translate off 233c233 < //synthesis translate on --- > //translate on - Create a clean project:
$ /opt/Xilinx/2025.1/Vivado/bin/vivado -source rebuild.tcl - Generate the output products, and checked the
test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/source/msys_axi_pcie_0_0_debug_wrapper.vin the project had the modifications. - Run Synthesis and the the schmatic for
debug_wrapper_Unow shows the same connections as Vivado v2024.1. - Implementation completes, but get a timing failure on 10 nets on
CLK_PCIe_100MHz_clk_p[0]for hold time onu_ila_0. Worst case slack is -2.848 ns - Programmed the device. The PCIe endpoint works, but got the following Program Device pop-up from the Hardware Manager:
ERROR: [Labtools 27-3412] Mismatch between the design programmed into the device 'xc7k160t' (JTAG device index = '0' and the probes file(s) '/home/mr_halfword/fpga_sio/fpga_tests/memmapped_blkram/test_ board/test_board.runs/impl_1/msys_wrapper.ltx'. The hw_probe 'msys_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_ wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/debug_wrapper_U/jtag_axi4l_m_ inst/m_axi_araddr' in the probes file has port index '1'. This port location for the ILA core at location (uuid_23E7D65A79BC59F7BC47406C1714DFAE), does not support a data probe. . Resolution:
- Ensure that the clock signal connected to the debug core and/or debug hub is clean and free-running.
- Ensure that the clock connected to the debug core and/or debug hub meets all timing constraints.
- Ensure that the JTAG clock frequency is 2.5x times slower than the frequency of the clock connected to your debug hub.
- The Hardware Manager does show a
hw_axi_1andhw_ila_1. The ILA isn't usable due to the conflict over the probes. source -notrace test_board/test_board.gen/sources_1/bd/msys/ip/msys_axi_pcie_0_0/msys_axi_pcie_0_0/pcie_debugger/test_rd.tclcompletes without error. The results look sensible.
This shows that adding the synthesis to the translate off/on comments has fixed the issue with test_rd.tcl not being able to read the correct values.
The hold timing failures are only on the ILA, which was only added to the design to try and debug the issue with the PCIe debugger.
This uses Vivado 2025.1
With a UltraScale+ device the JTAG Debugger option is available as an option in the DMA/Bridge Subsystem for PCI Express IP, unlike the case for Kintex 7 devices.
This uses the DMA/Bridge Subsystem for PCI Express design, fitted in a HP Z4 G4 slot 5. For reasons not yet understood this only enumerates at x4 width.
In the DMA/Bridge Subsystem for PCI Express IP configuration on the Basic tab set Mode to Advanced. On the Debug Options selected the following:
- JTAG Debugger
- LTSSM state Debug logic
- In System IBERT
- Add Mark Debug Utility
- Enable Descrambler
On connecting the Hardware Manager In System IBERT is shown but:
- Quad_226 and Quad_227 are shown, yet from the report_io Quad_224 and Quad_225 are used for the PCIe
- Even when the link is up at x4, "Auto-detect links" doesn't find any links.
The draw_ltssm.tcl, draw_reset.tcl and draw_rxdet.tcl scripts don't produce any meaningful results.
For a given run of test_rd.tcl all values read have the same value, but where the value can changed from run-to-run. Have seen:
- 0x00000402
- 0x00000000
- 0x00000b18
For a given run the same values are stored in all of the follwing created by test_rd.tcl
- pcie_debug_info_trc.dat
- pcie_debug_ltssm_trc.dat
- pcie_debug_rst_trc.dat
- pcie_debug_static_info.dat
- rxdet.dat
Rebuilt the FPGA with only JTAG Debugger enabled in the Debug options.
This showed the same issue in that for a given run, every read by test_rd.tcl returned the same value.
If use the Vivado 2025.1 Hardware Manager to run the scripts from memmapped_blkram which was for a xc7k160t built with Vivado v2023.2 then get sensible results, so the v2025.1 Hardware Manager doesn't seem to be the cause of the problem.
Using the AS02MC04_enum/gen3_x8_reversed_lane_order project:
- Create a clean project using
opt/Xilinx/2025.1/Vivado/bin/vivado -source create_project.tcl - Enable the JTAG Debugger in the XMDA.
- Run Synthesis. In trhe schematic for
debug_wrapper_U:- The
m_axi_araddr[31:0]andm_axi_arvalidnets are not shown connected tojtag_axi4l_m_instnordebug_axi4l_s_inst. AS02MC04_enum/AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/source/AS02MC04_enum_xdma_0_0_pcie4_ip_debug_axi4l_s.vhas the following used to selecttrc_addras either the write or read address:/*******************************************************************************/ // TRACE access /*******************************************************************************/ always @ (posedge AXI_aclk) begin if (~AXI_aresetn) trc_addr <= 17'h0; else if (cur_st == WR_ST) trc_addr <= S_AXI_awaddr[16:0]; else if (cur_st == RD_ST) trc_addr <= S_AXI_araddr[16:0]; end
- Looking at the schematic
LUT2's are used to generate thetrc_addrwhere:I0is thecur_st[2]bit of the state, where 0 means write and 1 means read.I1is the write address bit- The LUT equation selects the write address input, or a fixed value for the read address.
- Can't seem to determine what
m_axi_arvalidis connected to insidedebug_axi4l_s_inst, as the nets seem to have been optimised.
- The
- Changed the Target Language for the project from Verilog to VHDL. The
debug_axi4l_s_instwas still implemented with Verilog and didn't fix the issue.
Wasn't sure which debug_wrapper_v.ttcl in the IP gets used for the Ultrascale+ XDMA. Initially tried modifying the pcie3_7x_v4_3 version:
$ cp -p /opt/Xilinx/2025.1/Vivado/data/ip/xilinx/pcie3_7x_v4_3/ttcl/pcie_debugger/debug_wrapper_v.{ttcl,bak}
$ gedit /opt/Xilinx/2025.1/Vivado/data/ip/xilinx/pcie3_7x_v4_3/ttcl/pcie_debugger/debug_wrapper_v.ttcl
$ diff /opt/Xilinx/2025.1/Vivado/data/ip/xilinx/pcie3_7x_v4_3/ttcl/pcie_debugger/debug_wrapper_v.{ttcl,bak}
217c217
< //synthesis translate off
---
> //translate off
233c233
< //synthesis translate on
---
> //translate on
But the generated AS02MC04_enum/AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/source/AS02MC04_enum_xdma_0_0_pcie4_ip_debug_wrapper.v still had //translate off.
Modified the pcie_7x_v3_3 file:
$ cp -p /opt/Xilinx/2025.1/Vivado/data/ip/xilinx/pcie_7x_v3_3/ttcl/pcie_debugger/debug_wrapper_v.{ttcl,bak}
$ gedit /opt/Xilinx/2025.1/Vivado/data/ip/xilinx/pcie_7x_v3_3/ttcl/pcie_debugger/debug_wrapper_v.ttcl
$ diff /opt/Xilinx/2025.1/Vivado/data/ip/xilinx/pcie_7x_v3_3/ttcl/pcie_debugger/debug_wrapper_v.{ttcl,bak}
217c217
< //synthesis translate off
---
> //translate off
233c233
< //synthesis translate on
---
> //translate on
But the generated file still had //translate off.
The generated AS02MC04_enum/AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/source/AS02MC04_enum_xdma_0_0_pcie4_ip_debug_wrapper.v has the following, which matches that from the version used with the Kinex 7:
//debugging simulation
//translate off
initial begin
#4840;
force AXI_arvalid = 1'b1;
force AXI_araddr = 32'h1020;
while(~AXI_arready) @(posedge AXI_aclk);
force AXI_arvalid = 1'b0;
while (~AXI_rvalid) @(posedge AXI_aclk);
$display("%t get data %h, with response %h", $realtime, AXI_rdata, AXI_rresp);
force AXI_rready = 1'b1;
@(posedge AXI_aclk);
force AXI_rready = 1'b0;
repeat(20) @(posedge AXI_aclk);
// $finish;
end
//translate onHowever, on searching the v2025.1 IP for force AXI_araddr = 32'h1020; can't find any files which haven't modified.
The XDMA is using Ultrascale+ Integrated Block (PCIE4) for PCI Express version 1.3 Rev. 30).
Performing a filename search finds the following, where the data files seem to be encrypted:
$ find /opt/Xilinx/2025.1 -name '*debug_wrapper_v.ttcl' | xargs file
/opt/Xilinx/2025.1/data/ip/xilinx/pcie_versal_v1_1/ttcl/pcie_debugger/src/src_debug_wrapper_v.ttcl: data
/opt/Xilinx/2025.1/data/ip/xilinx/pcie4_uscale_plus_v1_3/ttcl/pcie_debugger/src/src_debug_wrapper_v.ttcl: data
/opt/Xilinx/2025.1/data/ip/xilinx/pcie3_7x_v4_3/ttcl/pcie_debugger/debug_wrapper_v.ttcl: ASCII text
/opt/Xilinx/2025.1/data/ip/xilinx/pcie3_ultrascale_v4_4/ttcl/pcie_debugger/src/src_debug_wrapper_v.ttcl: data
/opt/Xilinx/2025.1/data/ip/xilinx/pcie4c_uscale_plus_v1_0/ttcl/pcie_debugger/src/src_debug_wrapper_v.ttcl: data
/opt/Xilinx/2025.1/data/ip/xilinx/pcie4ce_uscale_plus_v1_0/ttcl/pcie_debugger/src/src_debug_wrapper_v.ttcl: data
/opt/Xilinx/2025.1/data/ip/xilinx/pcie_7x_v3_3/ttcl/pcie_debugger/debug_wrapper_v.ttcl: ASCII text
/opt/Xilinx/2025.1/data/ip/xilinx/axi_pcie_v2_9/ttcl/pcie_debugger/debug_wrapper_v.ttcl: ASCII text
Attempted to run the create_project.tcl created by v2025.1 with v2024.2 but got the errors:
-
[BD::TCL 103-2012] The following IPs are not found in the IP Catalog: xilinx.com:ip:xdma:4.2
Resolution: Please add the repository containing the IP(s) to the project.
-
[Common 17-161] Invalid option value 'Vivado Synthesis 2025' specified for 'value'.
Performed the following manual edits to create_project.tcl:
- Downagrade
xilinx.com:ip:xdma:4.2toxilinx.com:ip:xdma:4.1 - Change the year in the flow names from 2025 to 2024.
After these manual edits /opt/Xilinx/Vivado/2024.2/bin/vivado -source create_project.tcl was able to create a usable project. Got the error [Common 17-54] The object 'report' does not have a property 'options.routable_nets'. and seemed to have defaulted to 2024 flow defaults. Added back copy_bitstream.tcl as the steps.write_bitstream.tcl.post property.
After synthesis had run, the schematic now showed m_axi_araddr[16:0] and m_axi_arvalid as outputs from jtag_axi4l_m_inst connected to inputs on debug_ax4l_s_inst.
The AS02MC04_axi_jtag design was created for a XCKU3P to test the JTAG-to-AXI Master Debug Core. Created with v2023.2 and will re-build with later versions to see if stops working.
parse_bitstream_file reports the user access as:
Type 1 packet opcode write register AXSS 7C333509 - 15/08/2025 19:20:09
The expected value is read:
source -notrace read_user_access.tcl
User access : 0x7c333509
Can cycle over all the LED values:
source -notrace increment_leds.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000000
LED : 0x00000003 -> 0x00000000
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000001
LED : 0x00000000 -> 0x00000001
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000002
LED : 0x00000001 -> 0x00000002
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000003
LED : 0x00000002 -> 0x00000003
parse_bitstream_file reports the user access as:
Type 1 packet opcode write register AXSS 7C337362 - 15/08/2025 23:13:34
The expected value is read:
source -notrace read_user_access.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
User access : 0x7c337362
Can cycle over all the LED values:
source -notrace increment_leds.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000000
LED : 0x00000003 -> 0x00000000
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000001
LED : 0x00000000 -> 0x00000001
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000002
LED : 0x00000001 -> 0x00000002
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000003
LED : 0x00000002 -> 0x00000003
parse_bitstream_file reports the user access as:
Type 1 packet opcode write register AXSS 7C337BB3 - 15/08/2025 23:46:51
The expected value is read:
source -notrace read_user_access.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
User access : 0x7c337bb3
Can cycle over all the LED values:
source -notrace increment_leds.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000000
LED : 0x00000003 -> 0x00000000
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000001
LED : 0x00000000 -> 0x00000001
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000002
LED : 0x00000001 -> 0x00000002
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000003
LED : 0x00000002 -> 0x00000003
parse_bitstream_file reports the user access as:
Type 1 packet opcode write register AXSS 843204C3 - 16/08/2025 00:19:03
The expected value is read:
source -notrace read_user_access.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
User access : 0x843204c3
Can cycle over all the LED values:
source -notrace increment_leds.tcl
WARNING: [Labtoolstcl 44-227] No matching hw_axi_txns were found
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000000
LED : 0x00000003 -> 0x00000000
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000001
LED : 0x00000000 -> 0x00000001
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000002
LED : 0x00000001 -> 0x00000002
source -notrace increment_leds.tcl
INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00000003
LED : 0x00000002 -> 0x00000003
Looking at the schematic in Vivado:
- There is a
jtag_axi_0block with:m_axi_*signals for the master AXI port, connected internally to the AXI interfaces under testsl_oport0[16:0]connected to adbg_hubon the top levelsl_iport0[36:0]connected to adbg_hubon the top levelaclkconnected to the same clock as the rest of the AXI interfaces. In this design the input clock is a 100MHz differential clock input.aresetnconnected to the same reset as the rest of the AXI interfaces. In this design is thelockedoutput from the clock wizard which generatesaclk.
- If try and expand the
jtag_axi_0block get<hidden>displayed for the internal blocks. According to 72319 - IP Encryption – Why am I seeing module names inside encrypted IPs as “” in Vivado? this means jtag_axi_0 is encrypted IP.