My setting of coding style of verilog. Use verible-verilog-format to re-format the code.

coding_style_format.sh

#!/bin/sh
verible-verilog-format \ 
    --inplace \
    --column_limit=200 \
    --indentation_spaces=4 \
    --line_break_penalty=4 \
    --assignment_statement_alignment=align \
    --case_items_alignment=align \
    --class_member_variable_alignment=align \
    --formal_parameters_alignment=align \
    --formal_parameters_indentation=indent \
    --named_port_alignment=align \
    --named_parameter_alignment=align \
    --module_net_variable_alignment=align \
    --port_declarations_alignment=align \
    --port_declarations_alignment=align \
    --struct_union_members_alignment=align \
    -- "$*"
# Above flags can be put into a file. Then, use following commmand to format the verilog.
# Note, one flag per line. The leading space and trailing backslash need to be omitted.
# > verible-verilog-format --flagfile=coding-style.f -- "$*"