Martoni

package multsum

import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
import chisel3.formal.Formal

/* Unsigned multiplication */
class MultSum(val bsize: Int = 16) extends Module with Formal {
  val io = IO(new Bundle {

Martoni

import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}

class CICFilter(val bsize: Int = 16,
                val rising: Boolean = true, //currently only one channel
                val cicstages: Int = 3,
                val cicrate: Int = 23,
                val cicdelay: Int = 1) extends Module{
  val io = IO(new Bundle {

Martoni

import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}

class SimplePWM(val insize: Int = 16) extends Module {
  val io = IO(new Bundle {
    val inval = Flipped(Decoupled(UInt(insize.W)))
    val pwm_o = Output(Bool())
  })

Martoni

//Copyright (C)2014-2020 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//GOWIN Version: V1.9.7.01Beta
//Part Number: GW1NSR-LV4CQN48PC7/I6
//Device: GW1NSR-4C
//Created Time: Tue Nov 03 14:39:26 2020

module TMDS_PLLVR (clkout, lock, clkoutd, clkin);

Martoni

#!/usr/bin/python3

import os
import re
import subprocess
import mmap

def patch(filename : str, bytes):
    subprocess.run(["cp",filename, filename + '_patched'])
    with open(filename + "_patched", "r+b") as f: