Skip to content

Instantly share code, notes, and snippets.

@SteveGotthardt
Last active May 14, 2024 02:41
Show Gist options
  • Save SteveGotthardt/33bdef27d1430f62b4fee5d723d0cde9 to your computer and use it in GitHub Desktop.
Save SteveGotthardt/33bdef27d1430f62b4fee5d723d0cde9 to your computer and use it in GitHub Desktop.
Get Klipper to run on Creality mainboard CR-FDM-V2.4.S4.170

Klipper for Crealty mainboard: CR-FDM-V2.4.S4.170

updating firmware: use SD card with filename firmware.bin in directory /user

  • /user/firmware.bin

Attaching to target with Atmel SAM-ICE

physical connection: Atmel SAM-ICE 20-pin to P6 4-pin

P6: Pin 1  (3.3V) -> ICE Pin 1  (VTref)  (square pin)
P6: Pin 2 (SWDIO) -> ICE Pin 7    (TMS)
P6: Pin 3 (SWCLK) -> ICE Pin 9    (TCK)
P6: Pin 4   (GND) -> ICE Pin 20   (GND)

running J-link commander

  • Device: Cortex-M4
  • Target Interface: SWD
  • Interface Speed: 4000 KHz (default)

inspecting bootloader state with J-Mem

  • VTOR is at 0xE000ED08
  • which shows vector table start now at 0x8000 (where bootloader will put new bins)
  • which shows stack pointer at 0x20002878 and reset at 0x843D - this is for firmware that shipped with my board

What is the clock running at: Crystal is 8.000MHz

PLL config @ 0x4005_4100 (CMU_PLLCFGR) = 0x3330_3100

So it looks like 8MHz XTAL * 50 / 2 is 200MHz system clock

  • MPLLM[0:4] = 0, divide by 1
  • PLLSRC = 0, XTAL selected (8MHz)
  • MPLLN[8:0] = 0x031 = multiply by 50d
  • MPLLR[3:0] = 3, divide by 4
  • MPLLQ[3:0] = 3, divide by 4
  • MPLLP[3:0] = 3, divide by 4

another run shows: PLL config @ 0x4005_4100 (CMU_PLLCFGR) = 0x11102900

So it looks like 8MHz XTAL * 42 / 2 is 168MHz system clock

  • MPLLM[0:4] = 0, divide by 1
  • PLLSRC = 0, XTAL selected (8MHz)
  • MPLLN[8:0] = 0x029 = multiply by 42
  • MPLLR[3:0] = 1, divide by 2
  • MPLLQ[3:0] = 1, divide by 2
  • MPLLP[3:0] = 1, divide by 2

XTAL selection: 0x40054032 CMU_XTALCR = 0, oscillates

XTAL configure: 0x40054410 CMU_XTALCFGR = 0, high-drive, not ultra, oscillates

Clock division of 200MHz system clock

  • CMU_SCFGR (32-bit) @ 0x40054020 after boot: 0x0011_2210
  • PCLK0: 0 divide by 1 = 200 - max 200, Timer6
  • PCLK1: 1 divide by 2 = 100 - max 100, USART, Timers, AES
  • PCLK2: 2 divide by 4 = 50 - max 60, ADC
  • PCLK3: 2 divide by 4 = 50 - max 50, RTC, I2C, CMP, WDT, SWDT control
  • PCLK4: 1 divide by 2 = 100 - max 100, ADC control, TRNG
  • EXCKS: 1 divide by 2 = 100 - max 100, SDIO, CAN
  • HCLKS: 0 divide by 1 = 200 - max 200, CPU, DMA, SRAM, INTC, QSPI, GPIO, DCU

Pinmap

  • CH340G TXD (2) = PA7 (to micro-USB connector)
  • CG340G RXD (3) = PA8
  • TB Bed Temperature = PC4
  • Bed Heater = PB10
  • TH Extruder Temp = PC5
  • Extruder Heater = PA1
  • E Dir = PA15
  • E Step = PB3
  • E Enable = PB4
  • X Dir = PC0
  • X Step = PC1
  • X Enable = PC2
  • X- endstop = PA5
  • X+ (extra?) = PA4 (found on pin 1 of 3-pin X+ header)
  • Y Dir = PB8
  • Y Step = PB9
  • Y Enable = PH2
  • Y- endstop = PA6
  • Z Dir = PB5
  • Z Step = PB6
  • Z Enable = PB7
  • Z- endstop = PB0
  • K-FAN1 = K-FAN2 = PA0
  • BLTouch pin 3 (IN) = PB1
  • BLTouch pin 5 (OUT) = PB2
  • LCD 1 (5V)
  • LCD 2 (GND)
  • LCD 3 (MOSI) = PB12
  • LCD 4 (N/C) = PB15
  • LCD 5 (CLK) = PB14
  • LCD 6 (MISO) = PB13
  • LCD 7 (RX) = PA3
  • LCD 8 (TX) = PA2
  • LCD 9 (RST) = PC7
  • LCD 10 (ENC) = PC6

The FAN terminals next to the power input terminals are wired directly to +24V

K-FAN1 and K-FAN2 are wired in parallel

IMG_20221213_172422 IMG_20221214_082648

@Ryz3nLV
Copy link

Ryz3nLV commented Dec 28, 2022

Not moving Y motor. Everything else are working good.

@ellensp
Copy link

ellensp commented May 13, 2024

@SteveGotthardt

can you check LCD 4 (N/C) Labeled as NCC on PCB

It is looking like LCD 4 is PB15 MarlinFirmware/Marlin#27074

@SteveGotthardt
Copy link
Author

SteveGotthardt commented May 14, 2024

@ellensp
I used my Ohm meter and I can confirm that the NCC (pin 4) does go to PB15 on the HC32F460

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment