Th3Fanbus

#!/usr/bin/env sh

# POSIX-compatible scripts cannot use the non-POSIX
# `seq` command or any shell-specific functionality.
# This is a helper function to make number lists to
# be used in for-loops. This is a reduced subset of
# the functionality `seq` provides, but is portable.
range() {
	loopcnt=$1
	while [ "$loopcnt" -le "$2" ]

Th3Fanbus

#include <boot/coreboot_tables.h>
#include <device/device.h>
#include <device/pci.h>
#include <fw_config.h>
#include <static.h>
#include "cpu/intel/model_206ax/chip.h"
#include "northbridge/intel/sandybridge/chip.h"
#include "southbridge/intel/bd82x6x/chip.h"

#if !DEVTREE_EARLY

Th3Fanbus

#include <inttypes.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>

#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

static const bool is_ivybridge = true;

Th3Fanbus

! Custom dark colorscheme

! special
*.background:	#000000
*.foreground:	#e5e5e5
*.cursorColor:	#a47996

! black
*.color0:	#000000
*.color8:	#666666

Th3Fanbus

# Instructions derived from: https://wiki.archlinux.org/index.php/DSDT

########################################################################
# Recompiling it yourself                                              #
# https://wiki.archlinux.org/index.php/DSDT#Recompiling_it_yourself    #
########################################################################

# Extract the binary ACPI tables
sudo cat /sys/firmware/acpi/tables/DSDT > dsdt.dat

Th3Fanbus

00:00.0 Host bridge: Intel Corporation Xeon E7 v3/Xeon E5 v3/Core i7 DMI2 (rev 02)
	Subsystem: Intel Corporation Device 0000
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin A routed to IRQ 0
	NUMA node: 0
	Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0
			ExtTag- RBE+
		DevCtl:	CorrErr- NonFatalErr- FatalErr- UnsupReq-

Th3Fanbus

R1D0    [33d] <=        0 (0000)
R500 C0 [b61] <=        0 (0000)
R500 C1 [b61] <=        0 (0000)
R1D0    [151] <=        4 (0004)
R1D0    [142] <=        0 (0000)
R500 C1 [6b3] <=        1 (0001)
R500 C1 [6cf] <=        1 (0001)
R1D0    [33d] <=        0 (0000)
R1D0    [33d] <=        0 (0000)

Th3Fanbus

https://review.coreboot.org/c/coreboot/+/46943 cpu/intel/Makefile.inc: Use correct Kconfig symbols https://review.coreboot.org/c/coreboot/+/46977 sb/intel/lynxpoint: Use common code to generate HPET table https://review.coreboot.org/c/coreboot/+/46719 sb/intel/lynxpoint: Drop unnecessary 'UL' suffix https://review.coreboot.org/c/coreboot/+/46720 {cpu,nb}/intel/haswell: Drop unnecessary 'UL' suffix https://review.coreboot.org/c/coreboot/+/46725 sb/intel/lynxpoint/lpc.c: Simplify PM init sequence https://review.coreboot.org/c/coreboot/+/46726 sb/intel/lynxpoint: Align with Broadwell https://review.coreboot.org/c/coreboot/+/46727 azalia: Treat all negative return values as errors https://review.coreboot.org/c/coreboot/+/46728 azalia: Use 'HDA_GCTL_CRST' macro as unset-mask https://review.coreboot.org/c/coreboot/+/46734 Revert "broadwell: Switch to using common ACPI _SWS code" https://review.coreboot.org/c/coreboot/+/46732 soc/intel/broadwell/gma.c: Align struct with Haswell

Th3Fanbus

usuario@bloodfest ~ $ lspci
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller (rev 06)
00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor PCI Express x16 Controller (rev 06)
00:02.0 VGA compatible controller: Intel Corporation 4th Gen Core Processor Integrated Graphics Controller (rev 06)
00:03.0 Audio device: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor HD Audio Controller (rev 06)
00:14.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB xHCI (rev 04)
00:16.0 Communication controller: Intel Corporation 8 Series/C220 Series Chipset Family MEI Controller #1 (rev 04)
00:1a.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #2 (rev 04)
00:1b.0 Audio device: Intel Corporation 8 Series/C220 Series Chipset High Definition Audio Controller (rev 04)
00:1c.0 PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express Root Port #1 (rev d4)

Th3Fanbus

int smbus_stub(int slv_addr, int reg, int length, unsigned char *b)
{
	struct mrc_params *p = wrapper_params;
	unsigned char *spd_data;

	switch (slv_addr) {
	case FAKE_SPD_ADDR_CH0:
		spd_data = p->mainboard.dram_data[0];
		break;
	case FAKE_SPD_ADDR_CH1: