broadwell_breakdown.md

https://review.coreboot.org/c/coreboot/+/46943 cpu/intel/Makefile.inc: Use correct Kconfig symbols https://review.coreboot.org/c/coreboot/+/46977 sb/intel/lynxpoint: Use common code to generate HPET table https://review.coreboot.org/c/coreboot/+/46719 sb/intel/lynxpoint: Drop unnecessary 'UL' suffix https://review.coreboot.org/c/coreboot/+/46720 {cpu,nb}/intel/haswell: Drop unnecessary 'UL' suffix https://review.coreboot.org/c/coreboot/+/46725 sb/intel/lynxpoint/lpc.c: Simplify PM init sequence https://review.coreboot.org/c/coreboot/+/46726 sb/intel/lynxpoint: Align with Broadwell https://review.coreboot.org/c/coreboot/+/46727 azalia: Treat all negative return values as errors https://review.coreboot.org/c/coreboot/+/46728 azalia: Use 'HDA_GCTL_CRST' macro as unset-mask https://review.coreboot.org/c/coreboot/+/46734 Revert "broadwell: Switch to using common ACPI _SWS code" https://review.coreboot.org/c/coreboot/+/46732 soc/intel/broadwell/gma.c: Align struct with Haswell https://review.coreboot.org/c/coreboot/+/46733 cpu/intel/haswell: Move smmrelocate.c MSR definitions to header https://review.coreboot.org/c/coreboot/+/46754 soc/intel/broadwell: Relocate PCH ACPI files https://review.coreboot.org/c/coreboot/+/46755 nb/intel/haswell/acpi: Align with Broadwell https://review.coreboot.org/c/coreboot/+/46756 nb/intel/haswell: Place CTDP ASL code in a separate scope https://review.coreboot.org/c/coreboot/+/46757 soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint https://review.coreboot.org/c/coreboot/+/46758 soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs https://review.coreboot.org/c/coreboot/+/46759 soc/intel/broadwell: Use common irqlinks.asl https://review.coreboot.org/c/coreboot/+/46760 sb/intel/common/acpi/irqlinks.asl: Clean up cosmetics https://review.coreboot.org/c/coreboot/+/46761 soc/intel/broadwell/pch/acpi: Add PCIe register offsets https://review.coreboot.org/c/coreboot/+/46762 sb/intel/common/acpi/pcie.asl: Generalise file comment https://review.coreboot.org/c/coreboot/+/46763 soc/intel/broadwell/pch: Use common PCIe ACPI code https://review.coreboot.org/c/coreboot/+/46764 sb/intel/lynxpoint: Expose full LPC device ID in ACPI https://review.coreboot.org/c/coreboot/+/46765 sb/intel/*/acpi/lpc.asl: Drop unnecessary RCBA offset https://review.coreboot.org/c/coreboot/+/46766 soc/intel/broadwell: Include EC and IRQ links ACPI early https://review.coreboot.org/c/coreboot/+/46773 soc/intel/broadwell: Merge 'device_nvs.asl' into 'globalnvs.asl' https://review.coreboot.org/c/coreboot/+/46774 sb/intel/lynxpoint/acpi: Put together LP GPIO code https://review.coreboot.org/c/coreboot/+/46775 sb/intel/lynxpoint: Align LP GPIO ACPI with Broadwell https://review.coreboot.org/c/coreboot/+/46776 sb/intel/lynxpoint/acpi/gpio.asl: Simplify constants https://review.coreboot.org/c/coreboot/+/46777 sb/intel/lynxpoint/acpi: Clean up cosmetics https://review.coreboot.org/c/coreboot/+/46778 soc/intel/broadwell/pch/acpi: Clean up cosmetics https://review.coreboot.org/c/coreboot/+/46779 soc/intel/broadwell/pch/acpi/hda.asl: Rename to 'audio.asl' https://review.coreboot.org/c/coreboot/+/46780 sb/intel/lynxpoint/acpi: Statically define _PRW values https://review.coreboot.org/c/coreboot/+/46781 sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource https://review.coreboot.org/c/coreboot/+/46782 sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI https://review.coreboot.org/c/coreboot/+/46783 sb/intel/lynxpoint/acpi/gpio.asl: Serialize GWAK method https://review.coreboot.org/c/coreboot/+/46784 sb/intel/lynxpoint/acpi/pch.asl: Drop unused FD definitions https://review.coreboot.org/c/coreboot/+/46785 haswell/lynxpoint: Drop remaining uses of 'ISLP' method https://review.coreboot.org/c/coreboot/+/46786 soc/intel/broadwell/acpi: Rename 'systemagent.asl' https://review.coreboot.org/c/coreboot/+/46787 nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN https://review.coreboot.org/c/coreboot/+/46788 nb/intel/haswell/acpi/hostbridge.asl: Drop unused registers https://review.coreboot.org/c/coreboot/+/46789 nb/intel/haswell/acpi: Merge 'haswell.asl' into 'hostbridge.asl' https://review.coreboot.org/c/coreboot/+/46790 nb/intel/haswell/acpi: Move PEG and CTDP includes downwards https://review.coreboot.org/c/coreboot/+/46791 nb/intel/haswell/acpi: Do not add PEG devices for LP https://review.coreboot.org/c/coreboot/+/46792 broadwell: Factor out 'acpi_fill_madt' function https://review.coreboot.org/c/coreboot/+/46793 broadwell: Flatten 'acpi_init_gnvs' function https://review.coreboot.org/c/coreboot/+/46794 soc/intel/broadwell: Relocate CPU files https://review.coreboot.org/c/coreboot/+/46795 soc/intel/broadwell: Flatten northbridge folder structure https://review.coreboot.org/c/coreboot/+/46796 soc/intel/broadwell: Split up acpi.c https://review.coreboot.org/c/coreboot/+/46797 soc/intel/broadwell/systemagent.c: Rename to 'hostbridge.c' https://review.coreboot.org/c/coreboot/+/46798 soc/intel/broadwell: Clean up headers https://review.coreboot.org/c/coreboot/+/46886 soc/intel/broadwell: Use 'mp_cpu_bus_init' https://review.coreboot.org/c/coreboot/+/46887 soc/intel/broadwell/pch/acpi.c: Remove unnecessary variable https://review.coreboot.org/c/coreboot/+/46888 soc/intel/broadwell/pch: Drop 'acpi_sci_irq' function https://review.coreboot.org/c/coreboot/+/46889 soc/intel/broadwell: Use common MADT code https://review.coreboot.org/c/coreboot/+/46890 soc/intel/broadwell/pch: Drop some 'config_of' uses https://review.coreboot.org/c/coreboot/+/46891 soc/intel/broadwell/pch: Simplify PCI RMW operations https://review.coreboot.org/c/coreboot/+/46892 soc/intel/broadwell: Align PCI device macros with Haswell https://review.coreboot.org/c/coreboot/+/46893 soc/intel/broadwell/pch: Remove inexistent IDE device macros https://review.coreboot.org/c/coreboot/+/46907 mb/intel/baskingridge: Replace invalid C-state values https://review.coreboot.org/c/coreboot/+/46908 cpu/intel/haswell: Factor out ACPI C-state values https://review.coreboot.org/c/coreboot/+/46910 cpu/intel/haswell: Rename 'HASWELL_BCLK' to 'CPU_BCLK' https://review.coreboot.org/c/coreboot/+/46912 cpu/intel/haswell: Do not determine CPU type at runtime https://review.coreboot.org/c/coreboot/+/46913 cpu/intel/haswell: Align cosmetics with Broadwell https://review.coreboot.org/c/coreboot/+/46914 cpu/intel/haswell/haswell.h: Align with Broadwell https://review.coreboot.org/c/coreboot/+/46915 cpu/intel/haswell: Clean up CPUID definitions https://review.coreboot.org/c/coreboot/+/46916 cpu/intel/haswell: Enable timed MWAIT if supported https://review.coreboot.org/c/coreboot/+/46917 cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR https://review.coreboot.org/c/coreboot/+/46918 cpu/intel/haswell: Enable turbo ratio if available https://review.coreboot.org/c/coreboot/+/46919 cpu/intel/haswell: Raise PSI1 threshold to 20A https://review.coreboot.org/c/coreboot/+/46920 cpu/intel/haswell: Allow tuning VR for C-state operations https://review.coreboot.org/c/coreboot/+/46921 cpu/intel/haswell: Add fast ramp voltage for Broadwell https://review.coreboot.org/c/coreboot/+/46922 cpu/intel/haswell: Set C9/C10 vccmin https://review.coreboot.org/c/coreboot/+/46923 cpu/intel/haswell/acpi.c: Use C-state enum definitions https://review.coreboot.org/c/coreboot/+/46924 cpu/intel/haswell: Add s0ix support https://review.coreboot.org/c/coreboot/+/46941 cpu/intel/haswell: Add delay for TPM before Flex Ratio reboot https://review.coreboot.org/c/coreboot/+/46942 cpu/intel/haswell: Add Broadwell CPUIDs and microcode https://review.coreboot.org/c/coreboot/+/46944 broadwell: Allow to use Haswell CPU code instead https://review.coreboot.org/c/coreboot/+/46945 mb/google/auron: Use Haswell CPU code https://review.coreboot.org/c/coreboot/+/46946 mb/google/jecht: Use Haswell CPU code https://review.coreboot.org/c/coreboot/+/46947 mb/intel/wtm2: Use Haswell CPU code https://review.coreboot.org/c/coreboot/+/46948 mb/purism/librem_bdw: Use Haswell CPU code https://review.coreboot.org/c/coreboot/+/46949 soc/intel/broadwell: Use Haswell CPU headers https://review.coreboot.org/c/coreboot/+/46950 broadwell: Drop now-unused CPU code https://review.coreboot.org/c/coreboot/+/46951 soc/intel/broadwell: Move romstage.c to Haswell https://review.coreboot.org/c/coreboot/+/46952 mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8 https://review.coreboot.org/c/coreboot/+/46953 soc/intel/broadwell: Select CPU_INTEL_HASWELL https://review.coreboot.org/c/coreboot/+/46955 Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL" https://review.coreboot.org/c/coreboot/+/46956 soc/intel/broadwell: Align memmap.h with Haswell https://review.coreboot.org/c/coreboot/+/46958 soc/intel/broadwell: Select INTEL_LYNXPOINT_LP https://review.coreboot.org/c/coreboot/+/46959 sb/intel/lynxpoint/acpi: Add missing USB ports https://review.coreboot.org/c/coreboot/+/46960 sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT https://review.coreboot.org/c/coreboot/+/46966 soc/intel/broadwell: Drop enable check from LPD0/LPD3 https://review.coreboot.org/c/coreboot/+/46967 soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods https://review.coreboot.org/c/coreboot/+/46969 sb/intel/lynxpoint: Use Broadwell SerialIO implementation https://review.coreboot.org/c/coreboot/+/46972 soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices https://review.coreboot.org/c/coreboot/+/46973 soc/intel/broadwell: Add ACPI CIDs for SerialIO devices https://review.coreboot.org/c/coreboot/+/46974 soc/intel/broadwell: Shorten LPT/WPT _HID choosing methods https://review.coreboot.org/c/coreboot/+/46975 sb/intel/lynxpoint: Add WildcatPoint SerialIO HIDs https://review.coreboot.org/c/coreboot/+/46954 broadwell boards: Switch to Lynxpoint ACPI https://review.coreboot.org/c/coreboot/+/46978 soc/intel/broadwell: Use common southbridge RCBA https://review.coreboot.org/c/coreboot/+/46979 soc/intel/broadwell: Iron out more cosmetic differences https://review.coreboot.org/c/coreboot/+/46980 nb/intel/haswell: Use 'chromeos_reserve_ram_oops' function https://review.coreboot.org/c/coreboot/+/46981 nb/intel/haswell: Align more stuff with Broadwell https://review.coreboot.org/c/coreboot/+/46982 soc/intel/broadwell: Drop unnecessary 'sa_dev' https://review.coreboot.org/c/coreboot/+/46987 nb/intel/haswell/northbridge.c: Correct DPR handling https://review.coreboot.org/c/coreboot/+/46988 soc/intel/broadwell/northbridge.c: Use TXT DPR definition https://review.coreboot.org/c/coreboot/+/46989 soc/intel/broadwell: Inline single-use functions https://review.coreboot.org/c/coreboot/+/46990 nb/intel/haswell: Create RMRR for iGPU https://review.coreboot.org/c/coreboot/+/46991 nb/intel/haswell: Calculate TSEG limit from registers https://review.coreboot.org/c/coreboot/+/46992 soc/intel/broadwell/memmap.c: Use Haswell implementation https://review.coreboot.org/c/coreboot/+/46993 nb/intel/haswell/memmap.h: Clean up https://review.coreboot.org/c/coreboot/+/46994 nb/intel/haswell: Drop invalid MMIO_PAVP_MSG write https://review.coreboot.org/c/coreboot/+/46995 soc/intel/broadwell/chip.h: Drop unused fields https://review.coreboot.org/c/coreboot/+/46996 broadwell: Clean up pei_data callbacks https://review.coreboot.org/c/coreboot/+/46997 mb/google/auron: Clean up romstage logic https://review.coreboot.org/c/coreboot/+/46998 broadwell: Simplify 'mainboard_post_raminit' callback https://review.coreboot.org/c/coreboot/+/46999 soc/intel/broadwell: Get rid of 'struct romstage_params' https://review.coreboot.org/c/coreboot/+/47000 soc/intel/broadwell: Refactor MRC entry https://review.coreboot.org/c/coreboot/+/47001 soc/intel/{broadwell,quark}: Drop 'PEI_DATA' typedef https://review.coreboot.org/c/coreboot/+/47002 nb/intel/haswell/pei_data.h: Rename 'over_current_pin' fields https://review.coreboot.org/c/coreboot/+/47003 soc/intel/broadwell/pei_data: Rename and retype fields https://review.coreboot.org/c/coreboot/+/37568 [WIP] mb/acer: Add Acer E5-573 mainboard [WIP]