Created
January 18, 2022 12:46
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yosys -p 'read_verilog -DFPGA hazard3_core.v hazard3_cpu_1port.v hazard3_cpu_2port.v arith/hazard3_alu.v arith/hazard3_shift_barrel.v arith/hazard3_priority_encode.v arith/hazard3_muldiv_seq.v arith/hazard3_mul_fast.v hazard3_frontend.v hazard3_instr_decompress.v hazard3_decode.v hazard3_csr.v hazard3_regfile_1w2r.v; hierarchy -top hazard3_cpu_2port; synth_ice40' |
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