Skip to content

Instantly share code, notes, and snippets.

View Wren6991's full-sized avatar

Luke Wren Wren6991

  • Cambridge, UK
View GitHub Profile
@Wren6991
Wren6991 / 1. test.c
Last active January 19, 2022 19:42
BruceMIPS/MHz
#ifdef HAZARD3
#include "tb_cxxrtl_io.h"
#define printf tb_printf
#else
#include <stdio.h>
#endif
#include <stdint.h>
int __attribute__((noinline)) test(int x) {
int count = 0;
yosys -p 'read_verilog -DFPGA hazard3_core.v hazard3_cpu_1port.v hazard3_cpu_2port.v arith/hazard3_alu.v arith/hazard3_shift_barrel.v arith/hazard3_priority_encode.v arith/hazard3_muldiv_seq.v arith/hazard3_mul_fast.v hazard3_frontend.v hazard3_instr_decompress.v hazard3_decode.v hazard3_csr.v hazard3_regfile_1w2r.v; hierarchy -top hazard3_cpu_2port; synth_ice40'
@Wren6991
Wren6991 / hazard3_config.vh
Created January 18, 2022 12:39
RV32IMZbaZbbZbs config
/*****************************************************************************\
| Copyright (C) 2021 Luke Wren |
| SPDX-License-Identifier: Apache-2.0 |
\*****************************************************************************/
// Hazard3 CPU configuration parameters
// To configure Hazard3 you can either edit this file, or set parameters on
// your top-level instantiation, it's up to you. These parameters are all
// plumbed through Hazard3's internal hierarchy to the appropriate places.
@Wren6991
Wren6991 / hazard3_config.vh
Created January 18, 2022 12:37
RV32I config
/*****************************************************************************\
| Copyright (C) 2021 Luke Wren |
| SPDX-License-Identifier: Apache-2.0 |
\*****************************************************************************/
// Hazard3 CPU configuration parameters
// To configure Hazard3 you can either edit this file, or set parameters on
// your top-level instantiation, it's up to you. These parameters are all
// plumbed through Hazard3's internal hierarchy to the appropriate places.
// Custom CSRs
#define meie0 0xbe0 // External interrupt enable
#define meip0 0xfe0 // External interrupt pending
#define mlei 0xfe4 // Lowest external interrupt, left shifted by 2.
_external_irq_vector:
// Begin critical section
addi sp, sp, -16
sw a0, 0(sp)
#define OPCODE_AMO 0x2f
#define FUNCT5_AMOSWAP 0x01
#define FUNCT5_AMOADD 0x00
#define FUNCT5_AMOXOR 0x04
#define FUNCT5_AMOAND 0x0c
#define FUNCT5_AMOOR 0x08
#define FUNCT5_AMOMIN 0x10
#define FUNCT5_AMOMAX 0x14
#define FUNCT5_AMOMINU 0x18

RISCBoy Audio Processing Unit (APU)

Goals:

  • Resource budget: 100 LUTs (excluding system interface and digital DACs), two BRAMs
  • 48 kHz 8 bit stereo output when running at 36 MHz
  • Provide similar capability to an original Gameboy with default microcode
  • Be rather more capable with user-supplied microcode
  • Easy to use as a dumb wave-out ring buffer interface
  • Fun to program
module priority_select #(
parameter N = 16 // any positive integer
) (
input wire [N-1:0] req,
output wire [N-1:0] gnt
);
generate
if (N == 1) begin: base_case0
assign gnt = req;
@Wren6991
Wren6991 / bug.ys
Created August 23, 2020 15:18
hazard5_alu CXXRTL repro
read_verilog hazard5_alu.v hazard5_shift_barrel.v
write_cxxrtl foo.cpp
.syntax unified
.cpu cortex-m0plus
.thumb
#ifndef FONT_BLIT_UNROLL
#define FONT_BLIT_UNROLL 4
#endif
.macro decl_func name
.global \name