arduino.ide.2.0.3.console

Debug: 4105 10249 riscv.c:3517 riscv_get_register(): [esp32c3] tp: 0 (cached)
Debug: 4106 10249 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tp (valid=1)
Debug: 4107 10249 esp_riscv.c:321 esp_riscv_start_algorithm(): save t0
Debug: 4108 10249 riscv.c:3517 riscv_get_register(): [esp32c3] t0: 0 (cached)
Debug: 4109 10249 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t0 (valid=1)
Debug: 4110 10250 esp_riscv.c:321 esp_riscv_start_algorithm(): save t1
Debug: 4111 10250 riscv.c:3517 riscv_get_register(): [esp32c3] t1: 0 (cached)
Debug: 4112 10250 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t1 (valid=1)
Debug: 4113 10250 esp_riscv.c:321 esp_riscv_start_algorithm(): save t2
Debug: 4114 10250 riscv.c:3517 riscv_get_register(): [esp32c3] t2: 0 (cached)
Debug: 4115 10251 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t2 (valid=1)
Debug: 4116 10251 esp_riscv.c:321 esp_riscv_start_algorithm(): save fp
Debug: 4117 10251 riscv.c:3517 riscv_get_register(): [esp32c3] s0: 0 (cached)
Debug: 4118 10251 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from fp (valid=1)
Debug: 4119 10251 esp_riscv.c:321 esp_riscv_start_algorithm(): save s1
Debug: 4120 10252 riscv.c:3517 riscv_get_register(): [esp32c3] s1: 0 (cached)
Debug: 4121 10252 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s1 (valid=1)
Debug: 4122 10252 esp_riscv.c:321 esp_riscv_start_algorithm(): save a0
Debug: 4123 10252 riscv.c:3517 riscv_get_register(): [esp32c3] a0: 0 (cached)
Debug: 4124 10252 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a0 (valid=1)
Debug: 4125 10253 esp_riscv.c:321 esp_riscv_start_algorithm(): save a1
Debug: 4126 10253 riscv.c:3517 riscv_get_register(): [esp32c3] a1: 0 (cached)
Debug: 4127 10253 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a1 (valid=1)
Debug: 4128 10253 esp_riscv.c:321 esp_riscv_start_algorithm(): save a2
Debug: 4129 10253 riscv.c:3517 riscv_get_register(): [esp32c3] a2: 0 (cached)
Debug: 4130 10254 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a2 (valid=1)
Debug: 4131 10254 esp_riscv.c:321 esp_riscv_start_algorithm(): save a3
Debug: 4132 10254 riscv.c:3517 riscv_get_register(): [esp32c3] a3: 0 (cached)
Debug: 4133 10254 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a3 (valid=1)
Debug: 4134 10254 esp_riscv.c:321 esp_riscv_start_algorithm(): save a4
Debug: 4135 10254 riscv.c:3517 riscv_get_register(): [esp32c3] a4: 0 (cached)
Debug: 4136 10255 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a4 (valid=1)
Debug: 4137 10255 esp_riscv.c:321 esp_riscv_start_algorithm(): save a5
Debug: 4138 10255 riscv.c:3517 riscv_get_register(): [esp32c3] a5: 0 (cached)
Debug: 4139 10255 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a5 (valid=1)
Debug: 4140 10255 esp_riscv.c:321 esp_riscv_start_algorithm(): save a6
Debug: 4141 10255 riscv.c:3517 riscv_get_register(): [esp32c3] a6: 0 (cached)
Debug: 4142 10255 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a6 (valid=1)
Debug: 4143 10255 esp_riscv.c:321 esp_riscv_start_algorithm(): save a7
Debug: 4144 10257 riscv.c:3517 riscv_get_register(): [esp32c3] a7: 0 (cached)
Debug: 4145 10257 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a7 (valid=1)
Debug: 4146 10257 esp_riscv.c:321 esp_riscv_start_algorithm(): save s2
Debug: 4147 10257 riscv.c:3517 riscv_get_register(): [esp32c3] s2: 0 (cached)
Debug: 4148 10257 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s2 (valid=1)
Debug: 4149 10258 esp_riscv.c:321 esp_riscv_start_algorithm(): save s3
Debug: 4150 10258 riscv.c:3517 riscv_get_register(): [esp32c3] s3: 0 (cached)
Debug: 4151 10258 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s3 (valid=1)
Debug: 4152 10258 esp_riscv.c:321 esp_riscv_start_algorithm(): save s4
Debug: 4153 10258 riscv.c:3517 riscv_get_register(): [esp32c3] s4: 0 (cached)
Debug: 4154 10259 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s4 (valid=1)
Debug: 4155 10259 esp_riscv.c:321 esp_riscv_start_algorithm(): save s5
Debug: 4156 10259 riscv.c:3517 riscv_get_register(): [esp32c3] s5: 0 (cached)
Debug: 4157 10259 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s5 (valid=1)
Debug: 4158 10259 esp_riscv.c:321 esp_riscv_start_algorithm(): save s6
Debug: 4159 10260 riscv.c:3517 riscv_get_register(): [esp32c3] s6: 0 (cached)
Debug: 4160 10260 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s6 (valid=1)
Debug: 4161 10260 esp_riscv.c:321 esp_riscv_start_algorithm(): save s7
Debug: 4162 10260 riscv.c:3517 riscv_get_register(): [esp32c3] s7: 0 (cached)
Debug: 4163 10260 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s7 (valid=1)
Debug: 4164 10261 esp_riscv.c:321 esp_riscv_start_algorithm(): save s8
Debug: 4165 10261 riscv.c:3517 riscv_get_register(): [esp32c3] s8: 0 (cached)
Debug: 4166 10261 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s8 (valid=1)
Debug: 4167 10261 esp_riscv.c:321 esp_riscv_start_algorithm(): save s9
Debug: 4168 10261 riscv.c:3517 riscv_get_register(): [esp32c3] s9: 0 (cached)
Debug: 4169 10261 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s9 (valid=1)
Debug: 4170 10262 esp_riscv.c:321 esp_riscv_start_algorithm(): save s10
Debug: 4171 10262 riscv.c:3517 riscv_get_register(): [esp32c3] s10: 0 (cached)
Debug: 4172 10262 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s10 (valid=1)
Debug: 4173 10262 esp_riscv.c:321 esp_riscv_start_algorithm(): save s11
Debug: 4174 10262 riscv.c:3517 riscv_get_register(): [esp32c3] s11: 0 (cached)
Debug: 4175 10263 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s11 (valid=1)
Debug: 4176 10263 esp_riscv.c:321 esp_riscv_start_algorithm(): save t3
Debug: 4177 10263 riscv.c:3517 riscv_get_register(): [esp32c3] t3: 0 (cached)
Debug: 4178 10263 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t3 (valid=1)
Debug: 4179 10263 esp_riscv.c:321 esp_riscv_start_algorithm(): save t4
Debug: 4180 10264 riscv.c:3517 riscv_get_register(): [esp32c3] t4: 0 (cached)
Debug: 4181 10264 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t4 (valid=1)
Debug: 4182 10264 esp_riscv.c:321 esp_riscv_start_algorithm(): save t5
Debug: 4183 10264 riscv.c:3517 riscv_get_register(): [esp32c3] t5: 0 (cached)
Debug: 4184 10264 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t5 (valid=1)
Debug: 4185 10265 esp_riscv.c:321 esp_riscv_start_algorithm(): save t6
Debug: 4186 10265 riscv.c:3517 riscv_get_register(): [esp32c3] t6: 0 (cached)
Debug: 4187 10265 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t6 (valid=1)
Debug: 4188 10265 esp_riscv.c:321 esp_riscv_start_algorithm(): save pc
Debug: 4189 10265 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 4190 10266 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 4191 10268 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40000000
Debug: 4192 10268 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40000000
Debug: 4193 10268 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40000000
Debug: 4194 10268 riscv.c:3888 register_get(): [esp32c3] read 0x40000000 from pc (valid=0)
Debug: 4195 10268 esp_riscv.c:321 esp_riscv_start_algorithm(): save mstatus
Debug: 4196 10268 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mstatus
Debug: 4197 10269 riscv-013.c:800 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300
Debug: 4198 10271 riscv-013.c:1504 register_read_direct(): {0} mstatus = 0x201800
Debug: 4199 10271 riscv.c:3534 riscv_get_register(): [esp32c3] mstatus: 201800
Debug: 4200 10271 riscv.c:3888 register_get(): [esp32c3] read 0x00201800 from mstatus (valid=1)
Debug: 4201 10271 esp_riscv.c:321 esp_riscv_start_algorithm(): save misa
Debug: 4202 10272 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register misa
Debug: 4203 10272 riscv-013.c:800 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301
Debug: 4204 10274 riscv-013.c:1504 register_read_direct(): {0} misa = 0x40101104
Debug: 4205 10274 riscv.c:3534 riscv_get_register(): [esp32c3] misa: 40101104
Debug: 4206 10274 riscv.c:3888 register_get(): [esp32c3] read 0x40101104 from misa (valid=1)
Debug: 4207 10274 esp_riscv.c:321 esp_riscv_start_algorithm(): save mtvec
Debug: 4208 10274 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr773
Debug: 4209 10274 riscv-013.c:800 execute_abstract_command(): command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305
Debug: 4210 10277 riscv-013.c:1504 register_read_direct(): {0} csr773 = 0x1
Debug: 4211 10277 riscv.c:3534 riscv_get_register(): [esp32c3] csr773: 1
Debug: 4212 10277 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from mtvec (valid=0)
Debug: 4213 10277 esp_riscv.c:321 esp_riscv_start_algorithm(): save mscratch
Debug: 4214 10277 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr832
Debug: 4215 10278 riscv-013.c:800 execute_abstract_command(): command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340
Debug: 4216 10279 riscv-013.c:1504 register_read_direct(): {0} csr832 = 0x0
Debug: 4217 10279 riscv.c:3534 riscv_get_register(): [esp32c3] csr832: 0
Debug: 4218 10280 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from mscratch (valid=0)
Debug: 4219 10280 esp_riscv.c:321 esp_riscv_start_algorithm(): save mepc
Debug: 4220 10280 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mepc
Debug: 4221 10281 riscv-013.c:800 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341
Debug: 4222 10284 riscv-013.c:1504 register_read_direct(): {0} mepc = 0x0
Debug: 4223 10284 riscv.c:3534 riscv_get_register(): [esp32c3] mepc: 0
Debug: 4224 10284 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from mepc (valid=1)
Debug: 4225 10285 esp_riscv.c:321 esp_riscv_start_algorithm(): save mcause
Debug: 4226 10285 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mcause
Debug: 4227 10285 riscv-013.c:800 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342
Debug: 4228 10288 riscv-013.c:1504 register_read_direct(): {0} mcause = 0x0
Debug: 4229 10288 riscv.c:3534 riscv_get_register(): [esp32c3] mcause: 0
Debug: 4230 10288 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from mcause (valid=1)
Debug: 4231 10289 esp_riscv.c:321 esp_riscv_start_algorithm(): save mtval
Debug: 4232 10289 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr835
Debug: 4233 10289 riscv-013.c:800 execute_abstract_command(): command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343
Debug: 4234 10291 riscv-013.c:1504 register_read_direct(): {0} csr835 = 0x0
Debug: 4235 10291 riscv.c:3534 riscv_get_register(): [esp32c3] csr835: 0
Debug: 4236 10291 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from mtval (valid=0)
Debug: 4237 10292 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg0
Debug: 4238 10292 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr928
Debug: 4239 10292 riscv-013.c:800 execute_abstract_command(): command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0
Debug: 4240 10296 riscv-013.c:1504 register_read_direct(): {0} csr928 = 0x0
Debug: 4241 10297 riscv.c:3534 riscv_get_register(): [esp32c3] csr928: 0
Debug: 4242 10297 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpcfg0 (valid=0)
Debug: 4243 10297 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg1
Debug: 4244 10297 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr929
Debug: 4245 10297 riscv-013.c:800 execute_abstract_command(): command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1
Debug: 4246 10299 riscv-013.c:1504 register_read_direct(): {0} csr929 = 0x0
Debug: 4247 10299 riscv.c:3534 riscv_get_register(): [esp32c3] csr929: 0
Debug: 4248 10300 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpcfg1 (valid=0)
Debug: 4249 10300 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg2
Debug: 4250 10300 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr930
Debug: 4251 10300 riscv-013.c:800 execute_abstract_command(): command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2
Debug: 4252 10302 riscv-013.c:1504 register_read_direct(): {0} csr930 = 0x0
Debug: 4253 10303 riscv.c:3534 riscv_get_register(): [esp32c3] csr930: 0
Debug: 4254 10303 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpcfg2 (valid=0)
Debug: 4255 10303 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg3
Debug: 4256 10303 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr931
Debug: 4257 10303 riscv-013.c:800 execute_abstract_command(): command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3
Debug: 4258 10306 riscv-013.c:1504 register_read_direct(): {0} csr931 = 0x0
Debug: 4259 10306 riscv.c:3534 riscv_get_register(): [esp32c3] csr931: 0
Debug: 4260 10306 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpcfg3 (valid=0)
Debug: 4261 10306 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr0
Debug: 4262 10306 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr944
Debug: 4263 10307 riscv-013.c:800 execute_abstract_command(): command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0
Debug: 4264 10309 riscv-013.c:1504 register_read_direct(): {0} csr944 = 0x0
Debug: 4265 10309 riscv.c:3534 riscv_get_register(): [esp32c3] csr944: 0
Debug: 4266 10309 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr0 (valid=0)
Debug: 4267 10309 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr1
Debug: 4268 10310 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr945
Debug: 4269 10310 riscv-013.c:800 execute_abstract_command(): command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1
Debug: 4270 10312 riscv-013.c:1504 register_read_direct(): {0} csr945 = 0x0
Debug: 4271 10312 riscv.c:3534 riscv_get_register(): [esp32c3] csr945: 0
Debug: 4272 10313 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr1 (valid=0)
Debug: 4273 10313 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr2
Debug: 4274 10314 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr946
Debug: 4275 10314 riscv-013.c:800 execute_abstract_command(): command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2
Debug: 4276 10321 riscv-013.c:1504 register_read_direct(): {0} csr946 = 0x0
Debug: 4277 10321 riscv.c:3534 riscv_get_register(): [esp32c3] csr946: 0
Debug: 4278 10321 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr2 (valid=0)
Debug: 4279 10321 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr3
Debug: 4280 10322 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr947
Debug: 4281 10322 riscv-013.c:800 execute_abstract_command(): command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3
Debug: 4282 10324 riscv-013.c:1504 register_read_direct(): {0} csr947 = 0x0
Debug: 4283 10324 riscv.c:3534 riscv_get_register(): [esp32c3] csr947: 0
Debug: 4284 10325 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr3 (valid=0)
Debug: 4285 10325 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr4
Debug: 4286 10325 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr948
Debug: 4287 10325 riscv-013.c:800 execute_abstract_command(): command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4
Debug: 4288 10328 riscv-013.c:1504 register_read_direct(): {0} csr948 = 0x0
Debug: 4289 10329 riscv.c:3534 riscv_get_register(): [esp32c3] csr948: 0
Debug: 4290 10329 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr4 (valid=0)
Debug: 4291 10329 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr5
Debug: 4292 10329 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr949
Debug: 4293 10330 riscv-013.c:800 execute_abstract_command(): command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5
Debug: 4294 10333 riscv-013.c:1504 register_read_direct(): {0} csr949 = 0x0
Debug: 4295 10333 riscv.c:3534 riscv_get_register(): [esp32c3] csr949: 0
Debug: 4296 10333 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr5 (valid=0)
Debug: 4297 10334 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr6
Debug: 4298 10334 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr950
Debug: 4299 10334 riscv-013.c:800 execute_abstract_command(): command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6
Debug: 4300 10339 riscv-013.c:1504 register_read_direct(): {0} csr950 = 0x0
Debug: 4301 10339 riscv.c:3534 riscv_get_register(): [esp32c3] csr950: 0
Debug: 4302 10339 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr6 (valid=0)
Debug: 4303 10340 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr7
Debug: 4304 10340 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr951
Debug: 4305 10340 riscv-013.c:800 execute_abstract_command(): command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7
Debug: 4306 10345 riscv-013.c:1504 register_read_direct(): {0} csr951 = 0x0
Debug: 4307 10345 riscv.c:3534 riscv_get_register(): [esp32c3] csr951: 0
Debug: 4308 10345 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr7 (valid=0)
Debug: 4309 10345 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr8
Debug: 4310 10345 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr952
Debug: 4311 10345 riscv-013.c:800 execute_abstract_command(): command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8
Debug: 4312 10349 riscv-013.c:1504 register_read_direct(): {0} csr952 = 0x0
Debug: 4313 10349 riscv.c:3534 riscv_get_register(): [esp32c3] csr952: 0
Debug: 4314 10349 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr8 (valid=0)
Debug: 4315 10349 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr9
Debug: 4316 10350 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr953
Debug: 4317 10350 riscv-013.c:800 execute_abstract_command(): command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9
Debug: 4318 10354 riscv-013.c:1504 register_read_direct(): {0} csr953 = 0x0
Debug: 4319 10355 riscv.c:3534 riscv_get_register(): [esp32c3] csr953: 0
Debug: 4320 10355 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr9 (valid=0)
Debug: 4321 10355 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr10
Debug: 4322 10355 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr954
Debug: 4323 10355 riscv-013.c:800 execute_abstract_command(): command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba
Debug: 4324 10359 riscv-013.c:1504 register_read_direct(): {0} csr954 = 0x0
Debug: 4325 10359 riscv.c:3534 riscv_get_register(): [esp32c3] csr954: 0
Debug: 4326 10359 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr10 (valid=0)
Debug: 4327 10360 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr11
Debug: 4328 10360 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr955
Debug: 4329 10360 riscv-013.c:800 execute_abstract_command(): command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb
Debug: 4330 10362 riscv-013.c:1504 register_read_direct(): {0} csr955 = 0x0
Debug: 4331 10363 riscv.c:3534 riscv_get_register(): [esp32c3] csr955: 0
Debug: 4332 10363 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr11 (valid=0)
Debug: 4333 10364 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr12
Debug: 4334 10364 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr956
Debug: 4335 10364 riscv-013.c:800 execute_abstract_command(): command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc
Debug: 4336 10366 riscv-013.c:1504 register_read_direct(): {0} csr956 = 0x0
Debug: 4337 10366 riscv.c:3534 riscv_get_register(): [esp32c3] csr956: 0
Debug: 4338 10366 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr12 (valid=0)
Debug: 4339 10367 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr13
Debug: 4340 10367 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr957
Debug: 4341 10367 riscv-013.c:800 execute_abstract_command(): command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd
Debug: 4342 10370 riscv-013.c:1504 register_read_direct(): {0} csr957 = 0x0
Debug: 4343 10370 riscv.c:3534 riscv_get_register(): [esp32c3] csr957: 0
Debug: 4344 10370 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr13 (valid=0)
Debug: 4345 10370 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr14
Debug: 4346 10370 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr958
Debug: 4347 10371 riscv-013.c:800 execute_abstract_command(): command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be
Debug: 4348 10373 riscv-013.c:1504 register_read_direct(): {0} csr958 = 0x0
Debug: 4349 10373 riscv.c:3534 riscv_get_register(): [esp32c3] csr958: 0
Debug: 4350 10374 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr14 (valid=0)
Debug: 4351 10374 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr15
Debug: 4352 10374 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr959
Debug: 4353 10374 riscv-013.c:800 execute_abstract_command(): command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf
Debug: 4354 10377 riscv-013.c:1504 register_read_direct(): {0} csr959 = 0x0
Debug: 4355 10377 riscv.c:3534 riscv_get_register(): [esp32c3] csr959: 0
Debug: 4356 10377 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from pmpaddr15 (valid=0)
Debug: 4357 10378 esp_riscv.c:321 esp_riscv_start_algorithm(): save tselect
Debug: 4358 10378 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 4359 10378 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 4360 10380 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 4361 10381 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 0
Debug: 4362 10381 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tselect (valid=0)
Debug: 4363 10381 esp_riscv.c:321 esp_riscv_start_algorithm(): save tdata1
Debug: 4364 10381 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 4365 10381 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 4366 10383 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 4367 10383 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 4368 10383 riscv.c:3888 register_get(): [esp32c3] read 0x23e00000 from tdata1 (valid=0)
Debug: 4369 10384 esp_riscv.c:321 esp_riscv_start_algorithm(): save tdata2
Debug: 4370 10384 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata2
Debug: 4371 10384 riscv-013.c:800 execute_abstract_command(): command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2
Debug: 4372 10387 riscv-013.c:1504 register_read_direct(): {0} tdata2 = 0x0
Debug: 4373 10387 riscv.c:3534 riscv_get_register(): [esp32c3] tdata2: 0
Debug: 4374 10387 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tdata2 (valid=0)
Debug: 4375 10387 esp_riscv.c:321 esp_riscv_start_algorithm(): save tcontrol
Debug: 4376 10387 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1957
Debug: 4377 10388 riscv-013.c:800 execute_abstract_command(): command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5
Debug: 4378 10390 riscv-013.c:1504 register_read_direct(): {0} csr1957 = 0x0
Debug: 4379 10390 riscv.c:3534 riscv_get_register(): [esp32c3] csr1957: 0
Debug: 4380 10391 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tcontrol (valid=0)
Debug: 4381 10391 esp_riscv.c:321 esp_riscv_start_algorithm(): save dcsr
Debug: 4382 10391 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dcsr
Debug: 4383 10391 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 4384 10393 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3
Debug: 4385 10394 riscv.c:3534 riscv_get_register(): [esp32c3] dcsr: 4000b0c3
Debug: 4386 10394 riscv.c:3888 register_get(): [esp32c3] read 0x4000b0c3 from dcsr (valid=1)
Debug: 4387 10394 esp_riscv.c:321 esp_riscv_start_algorithm(): save dpc
Debug: 4388 10394 riscv.c:3517 riscv_get_register(): [esp32c3] dpc: 40000000 (cached)
Debug: 4389 10394 riscv.c:3888 register_get(): [esp32c3] read 0x40000000 from dpc (valid=1)
Debug: 4390 10395 esp_riscv.c:321 esp_riscv_start_algorithm(): save dscratch0
Debug: 4391 10395 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dscratch0
Debug: 4392 10395 riscv-013.c:800 execute_abstract_command(): command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2
Debug: 4393 10397 riscv-013.c:1504 register_read_direct(): {0} dscratch0 = 0x0
Debug: 4394 10397 riscv.c:3534 riscv_get_register(): [esp32c3] dscratch0: 0
Debug: 4395 10397 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from dscratch0 (valid=1)
Debug: 4396 10397 esp_riscv.c:321 esp_riscv_start_algorithm(): save dscratch1
Debug: 4397 10397 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1971
Debug: 4398 10398 riscv-013.c:800 execute_abstract_command(): command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3
Debug: 4399 10400 riscv-013.c:1504 register_read_direct(): {0} csr1971 = 0x0
Debug: 4400 10400 riscv.c:3534 riscv_get_register(): [esp32c3] csr1971: 0
Debug: 4401 10400 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from dscratch1 (valid=0)
Debug: 4402 10400 esp_riscv.c:321 esp_riscv_start_algorithm(): save hpmcounter16
Debug: 4403 10400 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr3088
Debug: 4404 10401 riscv-013.c:800 execute_abstract_command(): command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10
Debug: 4405 10403 riscv-013.c:1504 register_read_direct(): {0} csr3088 = 0x3
Debug: 4406 10403 riscv.c:3534 riscv_get_register(): [esp32c3] csr3088: 3
Debug: 4407 10403 riscv.c:3888 register_get(): [esp32c3] read 0x00000003 from hpmcounter16 (valid=0)
Debug: 4408 10403 esp_riscv.c:321 esp_riscv_start_algorithm(): save priv
Debug: 4409 10403 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register priv
Debug: 4410 10403 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 4411 10406 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3
Debug: 4412 10407 riscv.c:3534 riscv_get_register(): [esp32c3] priv: 3
Debug: 4413 10407 riscv.c:3888 register_get(): [esp32c3] read 0x03 from priv (valid=0)
Debug: 4414 10407 esp_riscv.c:350 esp_riscv_start_algorithm(): set sp
Debug: 4415 10407 riscv.c:3901 register_set(): [esp32c3] write 0x3fc84920 to sp (valid=1)
Debug: 4416 10407 riscv.c:3477 riscv_set_register(): [esp32c3] sp <- 3fc84920
Debug: 4417 10407 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc84920 to register sp
Debug: 4418 10407 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fc84920
Debug: 4419 10408 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002
Debug: 4420 10410 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc84920 to sp valid=1
Debug: 4421 10410 esp_riscv.c:350 esp_riscv_start_algorithm(): set a7
Debug: 4422 10410 riscv.c:3901 register_set(): [esp32c3] write 0x403810d2 to a7 (valid=1)
Debug: 4423 10410 riscv.c:3477 riscv_set_register(): [esp32c3] a7 <- 403810d2
Debug: 4424 10410 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x403810d2 to register a7
Debug: 4425 10411 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x403810d2
Debug: 4426 10411 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011
Debug: 4427 10413 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x403810d2 to a7 valid=1
Debug: 4428 10413 esp_riscv.c:350 esp_riscv_start_algorithm(): set a0
Debug: 4429 10413 riscv.c:3901 register_set(): [esp32c3] write 0x00000005 to a0 (valid=1)
Debug: 4430 10413 riscv.c:3477 riscv_set_register(): [esp32c3] a0 <- 5
Debug: 4431 10413 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x5 to register a0
Debug: 4432 10413 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x5
Debug: 4433 10414 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 4434 10415 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x5 to a0 valid=1
Debug: 4435 10415 esp_riscv.c:350 esp_riscv_start_algorithm(): set a1
Debug: 4436 10415 riscv.c:3901 register_set(): [esp32c3] write 0xffffffff to a1 (valid=1)
Debug: 4437 10415 riscv.c:3477 riscv_set_register(): [esp32c3] a1 <- ffffffff
Debug: 4438 10415 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xffffffff to register a1
Debug: 4439 10417 riscv-013.c:1315 register_write_direct(): {0} a1 <- 0xffffffff
Debug: 4440 10417 riscv-013.c:800 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b
Debug: 4441 10419 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xffffffff to a1 valid=1
Debug: 4442 10419 esp_riscv.c:350 esp_riscv_start_algorithm(): set a2
Debug: 4443 10419 riscv.c:3901 register_set(): [esp32c3] write 0x3fc8493c to a2 (valid=1)
Debug: 4444 10419 riscv.c:3477 riscv_set_register(): [esp32c3] a2 <- 3fc8493c
Debug: 4445 10420 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc8493c to register a2
Debug: 4446 10420 riscv-013.c:1315 register_write_direct(): {0} a2 <- 0x3fc8493c
Debug: 4447 10421 riscv-013.c:800 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c
Debug: 4448 10422 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc8493c to a2 valid=1
Debug: 4449 10422 riscv.c:3293 riscv_interrupts_disable(): Disabling Interrupts
Debug: 4450 10422 riscv.c:3517 riscv_get_register(): [esp32c3] mstatus: 201800 (cached)
Debug: 4451 10423 riscv.c:3888 register_get(): [esp32c3] read 0x00201800 from mstatus (valid=1)
Debug: 4452 10423 riscv.c:3901 register_set(): [esp32c3] write 0x00201800 to mstatus (valid=1)
Debug: 4453 10423 riscv.c:3477 riscv_set_register(): [esp32c3] mstatus <- 201800
Debug: 4454 10423 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x201800 to register mstatus
Debug: 4455 10424 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x201800
Debug: 4456 10424 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300
Debug: 4457 10427 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x201800 to mstatus valid=0
Debug: 4458 10427 esp_riscv.c:387 esp_riscv_start_algorithm(): resume at 0x40381ce4
Debug: 4459 10427 riscv.c:1472 riscv_resume(): handle_breakpoints=0
Debug: 4460 10427 riscv.c:1399 resume_prep(): [0]
Debug: 4461 10428 riscv.c:3477 riscv_set_register(): [esp32c3] pc <- 40381ce4
Debug: 4462 10428 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40381ce4 to register pc
Debug: 4463 10428 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40381ce4
Debug: 4464 10428 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40381ce4
Debug: 4465 10429 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 4466 10430 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 4467 10432 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce4
Debug: 4468 10432 riscv-013.c:4124 riscv013_set_register(): [0]   actual DPC written: 0x0000000040381ce4
Debug: 4469 10433 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40381ce4 to pc valid=0
Debug: 4470 10433 riscv.c:1289 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 4471 10434 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 4472 10434 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 4473 10434 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 4474 10434 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 4475 10434 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 4476 10435 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 4477 10435 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 4478 10437 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 4479 10438 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3
Debug: 4480 10439 riscv.c:3477 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3
Debug: 4481 10439 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr
Debug: 4482 10439 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3
Debug: 4483 10440 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 4484 10441 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0
Debug: 4485 10441 riscv.c:1300 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 4486 10441 riscv.c:1424 resume_prep(): [0] mark as prepped
Debug: 4487 10441 riscv.c:3276 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 4488 10442 riscv-013.c:4190 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 4489 10442 riscv-013.c:4815 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 4490 10445 riscv.c:3397 riscv_invalidate_register_cache(): [0]
Debug: 4491 10445 target.c:1860 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c3
Debug: 4492 10445 esp32c3.c:188 esp32c3_handle_target_event(): 18
Debug: 4493 10445 esp_riscv.c:281 esp_riscv_handle_target_event(): 18
Debug: 4494 10445 esp_algorithm.c:218 algorithm_run(): Wait algorithm completion
Debug: 4495 10447 riscv.c:2078 riscv_poll_hart():   triggered a halt
Debug: 4496 10447 riscv.c:2258 riscv_openocd_poll():   hart 0 halted
Debug: 4497 10448 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 4498 10450 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 4499 10450 riscv-013.c:4345 riscv013_halt_reason(): dcsr.cause: 0x1
Debug: 4500 10450 riscv.c:2113 set_debug_reason(): [esp32c3] debug_reason=1
Debug: 4501 10450 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 4502 10451 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 4503 10453 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce6
Debug: 4504 10453 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381ce6
Debug: 4505 10453 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40381ce6
Debug: 4506 10454 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381ce2
Debug: 4507 10459 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 4508 10459 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381ce6
Debug: 4509 10466 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 4510 10467 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381cea
Debug: 4511 10472 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 4512 10472 riscv_semihosting.c:108 riscv_semihosting(): check 9882bd19 47d99002 1141b7c5 from 0x40381ce6-4
Debug: 4513 10472 riscv_semihosting.c:112 riscv_semihosting():    -> NONE (no magic)
Debug: 4514 10473 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 4515 10473 esp32c3.c:188 esp32c3_handle_target_event(): 0
Debug: 4516 10473 esp_riscv.c:281 esp_riscv_handle_target_event(): 0
Debug: 4517 10473 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 4518 10474 target.c:5153 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: 
    esp32c3_wdt_disable

Debug: 4519 10474 command.c:166 script_debug(): command - command mode
Debug: 4520 10475 command.c:166 script_debug(): command - mww 0x6001f064 0x50D83AA1
Debug: 4521 10479 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 4522 10480 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 4523 10480 command.c:166 script_debug(): command - mww 0x6001F048 0
Debug: 4524 10483 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 4525 10485 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 4526 10485 command.c:166 script_debug(): command - mww 0x60020064 0x50D83AA1
Debug: 4527 10488 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 4528 10489 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 4529 10489 command.c:166 script_debug(): command - mww 0x60020048 0
Debug: 4530 10494 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 4531 10495 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 4532 10495 command.c:166 script_debug(): command - mww 0x600080a8 0x50D83AA1
Debug: 4533 10498 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 4534 10499 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 4535 10499 command.c:166 script_debug(): command - mww 0x60008090 0
Debug: 4536 10502 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 4537 10503 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 4538 10503 command.c:166 script_debug(): command - mww 0x600080b0 0x8F1D312A
Debug: 4539 10505 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080b0
Debug: 4540 10507 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 4541 10507 command.c:166 script_debug(): command - mww 0x600080ac 0x84B00000
Debug: 4542 10510 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080ac
Debug: 4543 10511 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 4544 10512 esp32c3.c:188 esp32c3_handle_target_event(): 1
Debug: 4545 10512 esp_riscv.c:281 esp_riscv_handle_target_event(): 1
Debug: 4546 10512 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 4547 10512 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 4548 10514 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce6
Debug: 4549 10514 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381ce6
Debug: 4550 10514 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40381ce6
Debug: 4551 10515 riscv.c:3888 register_get(): [esp32c3] read 0x40381ce6 from pc (valid=0)
Debug: 4552 10515 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a0
Debug: 4553 10515 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 4554 10517 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x0
Debug: 4555 10518 riscv.c:3534 riscv_get_register(): [esp32c3] a0: 0
Debug: 4556 10518 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a0 (valid=1)
Debug: 4557 10518 esp_riscv.c:465 esp_riscv_wait_algorithm(): Read mem params
Debug: 4558 10518 esp_riscv.c:467 esp_riscv_wait_algorithm(): Check mem param @ 0x3fc8493c
Debug: 4559 10518 esp_riscv.c:469 esp_riscv_wait_algorithm(): Read mem param @ 0x3fc8493c
Debug: 4560 10519 target.c:2536 target_read_buffer(): reading buffer of 28 byte at 0x3fc8493c
Debug: 4561 10524 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 4562 10524 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore ra
Debug: 4563 10524 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to ra (valid=0)
Debug: 4564 10525 riscv.c:3477 riscv_set_register(): [esp32c3] ra <- 0
Debug: 4565 10525 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register ra
Debug: 4566 10525 riscv-013.c:1315 register_write_direct(): {0} ra <- 0x0
Debug: 4567 10525 riscv-013.c:800 execute_abstract_command(): command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001
Debug: 4568 10528 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to ra valid=1
Debug: 4569 10528 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore sp
Debug: 4570 10528 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to sp (valid=0)
Debug: 4571 10528 riscv.c:3477 riscv_set_register(): [esp32c3] sp <- 0
Debug: 4572 10529 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register sp
Debug: 4573 10529 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x0
Debug: 4574 10530 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002
Debug: 4575 10531 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to sp valid=1
Debug: 4576 10532 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore gp
Debug: 4577 10532 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to gp (valid=0)
Debug: 4578 10532 riscv.c:3477 riscv_set_register(): [esp32c3] gp <- 0
Debug: 4579 10532 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register gp
Debug: 4580 10532 riscv-013.c:1315 register_write_direct(): {0} gp <- 0x0
Debug: 4581 10533 riscv-013.c:800 execute_abstract_command(): command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003
Debug: 4582 10534 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to gp valid=1
Debug: 4583 10534 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tp
Debug: 4584 10534 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tp (valid=0)
Debug: 4585 10534 riscv.c:3477 riscv_set_register(): [esp32c3] tp <- 0
Debug: 4586 10534 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tp
Debug: 4587 10535 riscv-013.c:1315 register_write_direct(): {0} tp <- 0x0
Debug: 4588 10535 riscv-013.c:800 execute_abstract_command(): command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004
Debug: 4589 10537 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tp valid=1
Debug: 4590 10537 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t0
Debug: 4591 10538 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t0 (valid=0)
Debug: 4592 10538 riscv.c:3477 riscv_set_register(): [esp32c3] t0 <- 0
Debug: 4593 10538 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t0
Debug: 4594 10538 riscv-013.c:1315 register_write_direct(): {0} t0 <- 0x0
Debug: 4595 10539 riscv-013.c:800 execute_abstract_command(): command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005
Debug: 4596 10540 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t0 valid=1
Debug: 4597 10540 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t1
Debug: 4598 10540 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t1 (valid=0)
Debug: 4599 10541 riscv.c:3477 riscv_set_register(): [esp32c3] t1 <- 0
Debug: 4600 10541 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t1
Debug: 4601 10541 riscv-013.c:1315 register_write_direct(): {0} t1 <- 0x0
Debug: 4602 10542 riscv-013.c:800 execute_abstract_command(): command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006
Debug: 4603 10544 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t1 valid=1
Debug: 4604 10544 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t2
Debug: 4605 10544 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t2 (valid=0)
Debug: 4606 10544 riscv.c:3477 riscv_set_register(): [esp32c3] t2 <- 0
Debug: 4607 10544 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t2
Debug: 4608 10545 riscv-013.c:1315 register_write_direct(): {0} t2 <- 0x0
Debug: 4609 10545 riscv-013.c:800 execute_abstract_command(): command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007
Debug: 4610 10547 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t2 valid=1
Debug: 4611 10547 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore fp
Debug: 4612 10548 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to fp (valid=0)
Debug: 4613 10548 riscv.c:3477 riscv_set_register(): [esp32c3] s0 <- 0
Debug: 4614 10548 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s0
Debug: 4615 10548 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x0
Debug: 4616 10549 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008
Debug: 4617 10550 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to fp valid=1
Debug: 4618 10551 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s1
Debug: 4619 10551 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s1 (valid=0)
Debug: 4620 10551 riscv.c:3477 riscv_set_register(): [esp32c3] s1 <- 0
Debug: 4621 10551 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s1
Debug: 4622 10552 riscv-013.c:1315 register_write_direct(): {0} s1 <- 0x0
Debug: 4623 10553 riscv-013.c:800 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009
Debug: 4624 10554 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s1 valid=1
Debug: 4625 10554 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a0
Debug: 4626 10554 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a0 (valid=1)
Debug: 4627 10554 riscv.c:3477 riscv_set_register(): [esp32c3] a0 <- 0
Debug: 4628 10555 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a0
Debug: 4629 10555 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x0
Debug: 4630 10555 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 4631 10558 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a0 valid=1
Debug: 4632 10558 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a1
Debug: 4633 10558 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a1 (valid=0)
Debug: 4634 10559 riscv.c:3477 riscv_set_register(): [esp32c3] a1 <- 0
Debug: 4635 10559 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a1
Debug: 4636 10559 riscv-013.c:1315 register_write_direct(): {0} a1 <- 0x0
Debug: 4637 10560 riscv-013.c:800 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b
Debug: 4638 10562 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a1 valid=1
Debug: 4639 10563 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a2
Debug: 4640 10563 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a2 (valid=0)
Debug: 4641 10563 riscv.c:3477 riscv_set_register(): [esp32c3] a2 <- 0
Debug: 4642 10563 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a2
Debug: 4643 10564 riscv-013.c:1315 register_write_direct(): {0} a2 <- 0x0
Debug: 4644 10564 riscv-013.c:800 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c
Debug: 4645 10566 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a2 valid=1
Debug: 4646 10566 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a3
Debug: 4647 10566 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a3 (valid=0)
Debug: 4648 10566 riscv.c:3477 riscv_set_register(): [esp32c3] a3 <- 0
Debug: 4649 10567 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a3
Debug: 4650 10567 riscv-013.c:1315 register_write_direct(): {0} a3 <- 0x0
Debug: 4651 10569 riscv-013.c:800 execute_abstract_command(): command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d
Debug: 4652 10570 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a3 valid=1
Debug: 4653 10571 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a4
Debug: 4654 10571 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a4 (valid=0)
Debug: 4655 10571 riscv.c:3477 riscv_set_register(): [esp32c3] a4 <- 0
Debug: 4656 10571 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a4
Debug: 4657 10571 riscv-013.c:1315 register_write_direct(): {0} a4 <- 0x0
Debug: 4658 10572 riscv-013.c:800 execute_abstract_command(): command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e
Debug: 4659 10574 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a4 valid=1
Debug: 4660 10574 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a5
Debug: 4661 10574 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a5 (valid=0)
Debug: 4662 10575 riscv.c:3477 riscv_set_register(): [esp32c3] a5 <- 0
Debug: 4663 10575 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a5
Debug: 4664 10575 riscv-013.c:1315 register_write_direct(): {0} a5 <- 0x0
Debug: 4665 10576 riscv-013.c:800 execute_abstract_command(): command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f
Debug: 4666 10578 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a5 valid=1
Debug: 4667 10578 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a6
Debug: 4668 10578 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a6 (valid=0)
Debug: 4669 10578 riscv.c:3477 riscv_set_register(): [esp32c3] a6 <- 0
Debug: 4670 10578 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a6
Debug: 4671 10579 riscv-013.c:1315 register_write_direct(): {0} a6 <- 0x0
Debug: 4672 10580 riscv-013.c:800 execute_abstract_command(): command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010
Debug: 4673 10581 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a6 valid=1
Debug: 4674 10581 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a7
Debug: 4675 10581 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a7 (valid=0)
Debug: 4676 10582 riscv.c:3477 riscv_set_register(): [esp32c3] a7 <- 0
Debug: 4677 10582 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a7
Debug: 4678 10582 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x0
Debug: 4679 10583 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011
Debug: 4680 10584 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a7 valid=1
Debug: 4681 10586 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s2
Debug: 4682 10586 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s2 (valid=0)
Debug: 4683 10586 riscv.c:3477 riscv_set_register(): [esp32c3] s2 <- 0
Debug: 4684 10586 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s2
Debug: 4685 10586 riscv-013.c:1315 register_write_direct(): {0} s2 <- 0x0
Debug: 4686 10587 riscv-013.c:800 execute_abstract_command(): command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012
Debug: 4687 10588 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s2 valid=1
Debug: 4688 10588 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s3
Debug: 4689 10589 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s3 (valid=0)
Debug: 4690 10589 riscv.c:3477 riscv_set_register(): [esp32c3] s3 <- 0
Debug: 4691 10589 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s3
Debug: 4692 10589 riscv-013.c:1315 register_write_direct(): {0} s3 <- 0x0
Debug: 4693 10590 riscv-013.c:800 execute_abstract_command(): command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013
Debug: 4694 10592 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s3 valid=1
Debug: 4695 10593 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s4
Debug: 4696 10593 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s4 (valid=0)
Debug: 4697 10593 riscv.c:3477 riscv_set_register(): [esp32c3] s4 <- 0
Debug: 4698 10593 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s4
Debug: 4699 10593 riscv-013.c:1315 register_write_direct(): {0} s4 <- 0x0
Debug: 4700 10594 riscv-013.c:800 execute_abstract_command(): command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014
Debug: 4701 10596 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s4 valid=1
Debug: 4702 10596 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s5
Debug: 4703 10596 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s5 (valid=0)
Debug: 4704 10597 riscv.c:3477 riscv_set_register(): [esp32c3] s5 <- 0
Debug: 4705 10597 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s5
Debug: 4706 10597 riscv-013.c:1315 register_write_direct(): {0} s5 <- 0x0
Debug: 4707 10598 riscv-013.c:800 execute_abstract_command(): command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015
Debug: 4708 10600 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s5 valid=1
Debug: 4709 10600 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s6
Debug: 4710 10600 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s6 (valid=0)
Debug: 4711 10601 riscv.c:3477 riscv_set_register(): [esp32c3] s6 <- 0
Debug: 4712 10601 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s6
Debug: 4713 10601 riscv-013.c:1315 register_write_direct(): {0} s6 <- 0x0
Debug: 4714 10602 riscv-013.c:800 execute_abstract_command(): command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016
Debug: 4715 10604 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s6 valid=1
Debug: 4716 10604 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s7
Debug: 4717 10604 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s7 (valid=0)
Debug: 4718 10605 riscv.c:3477 riscv_set_register(): [esp32c3] s7 <- 0
Debug: 4719 10605 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s7
Debug: 4720 10605 riscv-013.c:1315 register_write_direct(): {0} s7 <- 0x0
Debug: 4721 10606 riscv-013.c:800 execute_abstract_command(): command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017
Debug: 4722 10608 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s7 valid=1
Debug: 4723 10608 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s8
Debug: 4724 10608 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s8 (valid=0)
Debug: 4725 10609 riscv.c:3477 riscv_set_register(): [esp32c3] s8 <- 0
Debug: 4726 10609 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s8
Debug: 4727 10610 riscv-013.c:1315 register_write_direct(): {0} s8 <- 0x0
Debug: 4728 10611 riscv-013.c:800 execute_abstract_command(): command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018
Debug: 4729 10612 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s8 valid=1
Debug: 4730 10612 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s9
Debug: 4731 10613 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s9 (valid=0)
Debug: 4732 10613 riscv.c:3477 riscv_set_register(): [esp32c3] s9 <- 0
Debug: 4733 10613 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s9
Debug: 4734 10613 riscv-013.c:1315 register_write_direct(): {0} s9 <- 0x0
Debug: 4735 10615 riscv-013.c:800 execute_abstract_command(): command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019
Debug: 4736 10616 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s9 valid=1
Debug: 4737 10617 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s10
Debug: 4738 10617 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s10 (valid=0)
Debug: 4739 10617 riscv.c:3477 riscv_set_register(): [esp32c3] s10 <- 0
Debug: 4740 10617 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s10
Debug: 4741 10617 riscv-013.c:1315 register_write_direct(): {0} s10 <- 0x0
Debug: 4742 10618 riscv-013.c:800 execute_abstract_command(): command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a
Debug: 4743 10620 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s10 valid=1
Debug: 4744 10620 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s11
Debug: 4745 10620 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s11 (valid=0)
Debug: 4746 10620 riscv.c:3477 riscv_set_register(): [esp32c3] s11 <- 0
Debug: 4747 10621 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s11
Debug: 4748 10621 riscv-013.c:1315 register_write_direct(): {0} s11 <- 0x0
Debug: 4749 10622 riscv-013.c:800 execute_abstract_command(): command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b
Debug: 4750 10623 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s11 valid=1
Debug: 4751 10623 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t3
Debug: 4752 10624 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t3 (valid=0)
Debug: 4753 10624 riscv.c:3477 riscv_set_register(): [esp32c3] t3 <- 0
Debug: 4754 10624 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t3
Debug: 4755 10624 riscv-013.c:1315 register_write_direct(): {0} t3 <- 0x0
Debug: 4756 10626 riscv-013.c:800 execute_abstract_command(): command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c
Debug: 4757 10628 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t3 valid=1
Debug: 4758 10628 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t4
Debug: 4759 10628 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t4 (valid=0)
Debug: 4760 10629 riscv.c:3477 riscv_set_register(): [esp32c3] t4 <- 0
Debug: 4761 10629 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t4
Debug: 4762 10629 riscv-013.c:1315 register_write_direct(): {0} t4 <- 0x0
Debug: 4763 10630 riscv-013.c:800 execute_abstract_command(): command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d
Debug: 4764 10631 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t4 valid=1
Debug: 4765 10631 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t5
Debug: 4766 10631 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t5 (valid=0)
Debug: 4767 10632 riscv.c:3477 riscv_set_register(): [esp32c3] t5 <- 0
Debug: 4768 10632 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t5
Debug: 4769 10632 riscv-013.c:1315 register_write_direct(): {0} t5 <- 0x0
Debug: 4770 10633 riscv-013.c:800 execute_abstract_command(): command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e
Debug: 4771 10635 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t5 valid=1
Debug: 4772 10635 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t6
Debug: 4773 10635 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t6 (valid=0)
Debug: 4774 10635 riscv.c:3477 riscv_set_register(): [esp32c3] t6 <- 0
Debug: 4775 10636 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t6
Debug: 4776 10636 riscv-013.c:1315 register_write_direct(): {0} t6 <- 0x0
Debug: 4777 10637 riscv-013.c:800 execute_abstract_command(): command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f
Debug: 4778 10638 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t6 valid=1
Debug: 4779 10638 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pc
Debug: 4780 10638 riscv.c:3901 register_set(): [esp32c3] write 0x40000000 to pc (valid=0)
Debug: 4781 10639 riscv.c:3477 riscv_set_register(): [esp32c3] pc <- 40000000
Debug: 4782 10639 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40000000 to register pc
Debug: 4783 10639 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40000000
Debug: 4784 10639 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40000000
Debug: 4785 10640 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 4786 10642 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 4787 10644 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40000000
Debug: 4788 10644 riscv-013.c:4124 riscv013_set_register(): [0]   actual DPC written: 0x0000000040000000
Debug: 4789 10644 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40000000 to pc valid=0
Debug: 4790 10644 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mstatus
Debug: 4791 10644 riscv.c:3901 register_set(): [esp32c3] write 0x00201800 to mstatus (valid=0)
Debug: 4792 10645 riscv.c:3477 riscv_set_register(): [esp32c3] mstatus <- 201800
Debug: 4793 10645 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x201800 to register mstatus
Debug: 4794 10645 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x201800
Debug: 4795 10646 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300
Debug: 4796 10648 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x201800 to mstatus valid=0
Debug: 4797 10648 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore misa
Debug: 4798 10648 riscv.c:3901 register_set(): [esp32c3] write 0x40101104 to misa (valid=0)
Debug: 4799 10648 riscv.c:3477 riscv_set_register(): [esp32c3] misa <- 40101104
Debug: 4800 10649 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40101104 to register misa
Debug: 4801 10649 riscv-013.c:1315 register_write_direct(): {0} misa <- 0x40101104
Debug: 4802 10650 riscv-013.c:800 execute_abstract_command(): command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301
Debug: 4803 10651 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40101104 to misa valid=0
Debug: 4804 10651 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mtvec
Debug: 4805 10651 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to mtvec (valid=0)
Debug: 4806 10651 riscv.c:3477 riscv_set_register(): [esp32c3] csr773 <- 1
Debug: 4807 10652 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register csr773
Debug: 4808 10652 riscv-013.c:1315 register_write_direct(): {0} csr773 <- 0x1
Debug: 4809 10653 riscv-013.c:800 execute_abstract_command(): command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305
Debug: 4810 10654 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to mtvec valid=0
Debug: 4811 10654 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mscratch
Debug: 4812 10654 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to mscratch (valid=0)
Debug: 4813 10655 riscv.c:3477 riscv_set_register(): [esp32c3] csr832 <- 0
Debug: 4814 10655 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr832
Debug: 4815 10655 riscv-013.c:1315 register_write_direct(): {0} csr832 <- 0x0
Debug: 4816 10656 riscv-013.c:800 execute_abstract_command(): command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340
Debug: 4817 10657 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to mscratch valid=0
Debug: 4818 10657 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mepc
Debug: 4819 10657 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to mepc (valid=0)
Debug: 4820 10658 riscv.c:3477 riscv_set_register(): [esp32c3] mepc <- 0
Debug: 4821 10658 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register mepc
Debug: 4822 10658 riscv-013.c:1315 register_write_direct(): {0} mepc <- 0x0
Debug: 4823 10659 riscv-013.c:800 execute_abstract_command(): command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341
Debug: 4824 10660 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to mepc valid=0
Debug: 4825 10661 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mcause
Debug: 4826 10661 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to mcause (valid=0)
Debug: 4827 10661 riscv.c:3477 riscv_set_register(): [esp32c3] mcause <- 0
Debug: 4828 10661 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register mcause
Debug: 4829 10661 riscv-013.c:1315 register_write_direct(): {0} mcause <- 0x0
Debug: 4830 10662 riscv-013.c:800 execute_abstract_command(): command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342
Debug: 4831 10663 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to mcause valid=0
Debug: 4832 10663 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mtval
Debug: 4833 10663 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to mtval (valid=0)
Debug: 4834 10664 riscv.c:3477 riscv_set_register(): [esp32c3] csr835 <- 0
Debug: 4835 10664 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr835
Debug: 4836 10664 riscv-013.c:1315 register_write_direct(): {0} csr835 <- 0x0
Debug: 4837 10665 riscv-013.c:800 execute_abstract_command(): command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343
Debug: 4838 10666 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to mtval valid=0
Debug: 4839 10666 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg0
Debug: 4840 10667 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpcfg0 (valid=0)
Debug: 4841 10667 riscv.c:3477 riscv_set_register(): [esp32c3] csr928 <- 0
Debug: 4842 10667 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr928
Debug: 4843 10668 riscv-013.c:1315 register_write_direct(): {0} csr928 <- 0x0
Debug: 4844 10669 riscv-013.c:800 execute_abstract_command(): command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0
Debug: 4845 10670 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg0 valid=0
Debug: 4846 10670 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg1
Debug: 4847 10670 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpcfg1 (valid=0)
Debug: 4848 10670 riscv.c:3477 riscv_set_register(): [esp32c3] csr929 <- 0
Debug: 4849 10671 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr929
Debug: 4850 10671 riscv-013.c:1315 register_write_direct(): {0} csr929 <- 0x0
Debug: 4851 10672 riscv-013.c:800 execute_abstract_command(): command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1
Debug: 4852 10673 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg1 valid=0
Debug: 4853 10673 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg2
Debug: 4854 10673 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpcfg2 (valid=0)
Debug: 4855 10674 riscv.c:3477 riscv_set_register(): [esp32c3] csr930 <- 0
Debug: 4856 10674 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr930
Debug: 4857 10674 riscv-013.c:1315 register_write_direct(): {0} csr930 <- 0x0
Debug: 4858 10675 riscv-013.c:800 execute_abstract_command(): command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2
Debug: 4859 10676 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg2 valid=0
Debug: 4860 10676 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg3
Debug: 4861 10676 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpcfg3 (valid=0)
Debug: 4862 10677 riscv.c:3477 riscv_set_register(): [esp32c3] csr931 <- 0
Debug: 4863 10677 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr931
Debug: 4864 10677 riscv-013.c:1315 register_write_direct(): {0} csr931 <- 0x0
Debug: 4865 10679 riscv-013.c:800 execute_abstract_command(): command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3
Debug: 4866 10680 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg3 valid=0
Debug: 4867 10680 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr0
Debug: 4868 10680 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr0 (valid=0)
Debug: 4869 10681 riscv.c:3477 riscv_set_register(): [esp32c3] csr944 <- 0
Debug: 4870 10681 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr944
Debug: 4871 10681 riscv-013.c:1315 register_write_direct(): {0} csr944 <- 0x0
Debug: 4872 10682 riscv-013.c:800 execute_abstract_command(): command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0
Debug: 4873 10683 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr0 valid=0
Debug: 4874 10683 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr1
Debug: 4875 10683 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr1 (valid=0)
Debug: 4876 10684 riscv.c:3477 riscv_set_register(): [esp32c3] csr945 <- 0
Debug: 4877 10684 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr945
Debug: 4878 10684 riscv-013.c:1315 register_write_direct(): {0} csr945 <- 0x0
Debug: 4879 10685 riscv-013.c:800 execute_abstract_command(): command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1
Debug: 4880 10686 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr1 valid=0
Debug: 4881 10686 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr2
Debug: 4882 10686 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr2 (valid=0)
Debug: 4883 10686 riscv.c:3477 riscv_set_register(): [esp32c3] csr946 <- 0
Debug: 4884 10686 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr946
Debug: 4885 10687 riscv-013.c:1315 register_write_direct(): {0} csr946 <- 0x0
Debug: 4886 10688 riscv-013.c:800 execute_abstract_command(): command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2
Debug: 4887 10689 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr2 valid=0
Debug: 4888 10690 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr3
Debug: 4889 10690 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr3 (valid=0)
Debug: 4890 10690 riscv.c:3477 riscv_set_register(): [esp32c3] csr947 <- 0
Debug: 4891 10690 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr947
Debug: 4892 10690 riscv-013.c:1315 register_write_direct(): {0} csr947 <- 0x0
Debug: 4893 10691 riscv-013.c:800 execute_abstract_command(): command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3
Debug: 4894 10693 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr3 valid=0
Debug: 4895 10693 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr4
Debug: 4896 10693 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr4 (valid=0)
Debug: 4897 10693 riscv.c:3477 riscv_set_register(): [esp32c3] csr948 <- 0
Debug: 4898 10694 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr948
Debug: 4899 10694 riscv-013.c:1315 register_write_direct(): {0} csr948 <- 0x0
Debug: 4900 10696 riscv-013.c:800 execute_abstract_command(): command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4
Debug: 4901 10697 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr4 valid=0
Debug: 4902 10697 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr5
Debug: 4903 10697 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr5 (valid=0)
Debug: 4904 10697 riscv.c:3477 riscv_set_register(): [esp32c3] csr949 <- 0
Debug: 4905 10698 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr949
Debug: 4906 10698 riscv-013.c:1315 register_write_direct(): {0} csr949 <- 0x0
Debug: 4907 10699 riscv-013.c:800 execute_abstract_command(): command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5
Debug: 4908 10700 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr5 valid=0
Debug: 4909 10700 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr6
Debug: 4910 10700 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr6 (valid=0)
Debug: 4911 10701 riscv.c:3477 riscv_set_register(): [esp32c3] csr950 <- 0
Debug: 4912 10701 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr950
Debug: 4913 10701 riscv-013.c:1315 register_write_direct(): {0} csr950 <- 0x0
Debug: 4914 10702 riscv-013.c:800 execute_abstract_command(): command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6
Debug: 4915 10703 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr6 valid=0
Debug: 4916 10703 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr7
Debug: 4917 10704 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr7 (valid=0)
Debug: 4918 10704 riscv.c:3477 riscv_set_register(): [esp32c3] csr951 <- 0
Debug: 4919 10704 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr951
Debug: 4920 10704 riscv-013.c:1315 register_write_direct(): {0} csr951 <- 0x0
Debug: 4921 10705 riscv-013.c:800 execute_abstract_command(): command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7
Debug: 4922 10707 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr7 valid=0
Debug: 4923 10707 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr8
Debug: 4924 10707 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr8 (valid=0)
Debug: 4925 10707 riscv.c:3477 riscv_set_register(): [esp32c3] csr952 <- 0
Debug: 4926 10708 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr952
Debug: 4927 10708 riscv-013.c:1315 register_write_direct(): {0} csr952 <- 0x0
Debug: 4928 10709 riscv-013.c:800 execute_abstract_command(): command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8
Debug: 4929 10710 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr8 valid=0
Debug: 4930 10710 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr9
Debug: 4931 10711 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr9 (valid=0)
Debug: 4932 10711 riscv.c:3477 riscv_set_register(): [esp32c3] csr953 <- 0
Debug: 4933 10711 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr953
Debug: 4934 10711 riscv-013.c:1315 register_write_direct(): {0} csr953 <- 0x0
Debug: 4935 10712 riscv-013.c:800 execute_abstract_command(): command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9
Debug: 4936 10713 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr9 valid=0
Debug: 4937 10713 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr10
Debug: 4938 10714 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr10 (valid=0)
Debug: 4939 10714 riscv.c:3477 riscv_set_register(): [esp32c3] csr954 <- 0
Debug: 4940 10714 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr954
Debug: 4941 10715 riscv-013.c:1315 register_write_direct(): {0} csr954 <- 0x0
Debug: 4942 10715 riscv-013.c:800 execute_abstract_command(): command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba
Debug: 4943 10717 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr10 valid=0
Debug: 4944 10717 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr11
Debug: 4945 10717 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr11 (valid=0)
Debug: 4946 10717 riscv.c:3477 riscv_set_register(): [esp32c3] csr955 <- 0
Debug: 4947 10718 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr955
Debug: 4948 10718 riscv-013.c:1315 register_write_direct(): {0} csr955 <- 0x0
Debug: 4949 10719 riscv-013.c:800 execute_abstract_command(): command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb
Debug: 4950 10721 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr11 valid=0
Debug: 4951 10721 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr12
Debug: 4952 10721 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr12 (valid=0)
Debug: 4953 10722 riscv.c:3477 riscv_set_register(): [esp32c3] csr956 <- 0
Debug: 4954 10722 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr956
Debug: 4955 10722 riscv-013.c:1315 register_write_direct(): {0} csr956 <- 0x0
Debug: 4956 10723 riscv-013.c:800 execute_abstract_command(): command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc
Debug: 4957 10725 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr12 valid=0
Debug: 4958 10725 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr13
Debug: 4959 10725 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr13 (valid=0)
Debug: 4960 10725 riscv.c:3477 riscv_set_register(): [esp32c3] csr957 <- 0
Debug: 4961 10725 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr957
Debug: 4962 10726 riscv-013.c:1315 register_write_direct(): {0} csr957 <- 0x0
Debug: 4963 10726 riscv-013.c:800 execute_abstract_command(): command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd
Debug: 4964 10728 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr13 valid=0
Debug: 4965 10730 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr14
Debug: 4966 10730 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr14 (valid=0)
Debug: 4967 10730 riscv.c:3477 riscv_set_register(): [esp32c3] csr958 <- 0
Debug: 4968 10730 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr958
Debug: 4969 10731 riscv-013.c:1315 register_write_direct(): {0} csr958 <- 0x0
Debug: 4970 10731 riscv-013.c:800 execute_abstract_command(): command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be
Debug: 4971 10733 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr14 valid=0
Debug: 4972 10733 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr15
Debug: 4973 10733 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to pmpaddr15 (valid=0)
Debug: 4974 10733 riscv.c:3477 riscv_set_register(): [esp32c3] csr959 <- 0
Debug: 4975 10734 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr959
Debug: 4976 10734 riscv-013.c:1315 register_write_direct(): {0} csr959 <- 0x0
Debug: 4977 10735 riscv-013.c:800 execute_abstract_command(): command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf
Debug: 4978 10736 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr15 valid=0
Debug: 4979 10736 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tselect
Debug: 4980 10736 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tselect (valid=0)
Debug: 4981 10737 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 4982 10737 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 4983 10737 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 4984 10738 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 4985 10740 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 4986 10740 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tdata1
Debug: 4987 10740 riscv.c:3901 register_set(): [esp32c3] write 0x23e00000 to tdata1 (valid=0)
Debug: 4988 10740 riscv.c:3477 riscv_set_register(): [esp32c3] tdata1 <- 23e00000
Debug: 4989 10741 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x23e00000 to register tdata1
Debug: 4990 10741 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x23e00000
Debug: 4991 10742 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 4992 10744 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x23e00000 to tdata1 valid=0
Debug: 4993 10744 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tdata2
Debug: 4994 10744 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tdata2 (valid=0)
Debug: 4995 10744 riscv.c:3477 riscv_set_register(): [esp32c3] tdata2 <- 0
Debug: 4996 10745 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tdata2
Debug: 4997 10745 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x0
Debug: 4998 10745 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 4999 10748 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tdata2 valid=0
Debug: 5000 10748 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tcontrol
Debug: 5001 10748 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tcontrol (valid=0)
Debug: 5002 10749 riscv.c:3477 riscv_set_register(): [esp32c3] csr1957 <- 0
Debug: 5003 10749 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr1957
Debug: 5004 10749 riscv-013.c:1315 register_write_direct(): {0} csr1957 <- 0x0
Debug: 5005 10750 riscv-013.c:800 execute_abstract_command(): command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5
Debug: 5006 10751 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tcontrol valid=0
Debug: 5007 10752 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dcsr
Debug: 5008 10752 riscv.c:3901 register_set(): [esp32c3] write 0x4000b0c3 to dcsr (valid=0)
Debug: 5009 10752 riscv.c:3477 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3
Debug: 5010 10752 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr
Debug: 5011 10753 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3
Debug: 5012 10754 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 5013 10755 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0
Debug: 5014 10755 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dpc
Debug: 5015 10755 riscv.c:3901 register_set(): [esp32c3] write 0x40000000 to dpc (valid=0)
Debug: 5016 10757 riscv.c:3477 riscv_set_register(): [esp32c3] dpc <- 40000000
Debug: 5017 10757 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40000000 to register dpc
Debug: 5018 10757 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40000000
Debug: 5019 10758 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 5020 10760 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40000000 to dpc valid=1
Debug: 5021 10760 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dscratch0
Debug: 5022 10760 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to dscratch0 (valid=0)
Debug: 5023 10761 riscv.c:3477 riscv_set_register(): [esp32c3] dscratch0 <- 0
Debug: 5024 10761 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register dscratch0
Debug: 5025 10761 riscv-013.c:1315 register_write_direct(): {0} dscratch0 <- 0x0
Debug: 5026 10762 riscv-013.c:800 execute_abstract_command(): command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2
Debug: 5027 10763 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch0 valid=0
Debug: 5028 10764 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dscratch1
Debug: 5029 10764 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to dscratch1 (valid=0)
Debug: 5030 10764 riscv.c:3477 riscv_set_register(): [esp32c3] csr1971 <- 0
Debug: 5031 10764 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr1971
Debug: 5032 10764 riscv-013.c:1315 register_write_direct(): {0} csr1971 <- 0x0
Debug: 5033 10766 riscv-013.c:800 execute_abstract_command(): command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3
Debug: 5034 10767 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch1 valid=0
Debug: 5035 10767 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore hpmcounter16
Debug: 5036 10767 riscv.c:3901 register_set(): [esp32c3] write 0x00000003 to hpmcounter16 (valid=0)
Debug: 5037 10768 riscv.c:3477 riscv_set_register(): [esp32c3] csr3088 <- 3
Debug: 5038 10768 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register csr3088
Debug: 5039 10768 riscv-013.c:1315 register_write_direct(): {0} csr3088 <- 0x3
Debug: 5040 10769 riscv-013.c:800 execute_abstract_command(): command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10
Debug: 5041 10771 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to hpmcounter16 valid=0
Debug: 5042 10771 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore priv
Debug: 5043 10771 riscv.c:3901 register_set(): [esp32c3] write 0x03 to priv (valid=0)
Debug: 5044 10771 riscv.c:3477 riscv_set_register(): [esp32c3] priv <- 3
Debug: 5045 10771 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register priv
Debug: 5046 10773 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 5047 10775 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3
Debug: 5048 10775 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3
Debug: 5049 10776 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 5050 10777 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to priv valid=0
Debug: 5051 10778 esp_algorithm.c:246 algorithm_run(): Got algorithm RC 0x0
Debug: 5052 10779 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc8493c
Debug: 5053 10782 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 5054 10783 target.c:2206 target_free_working_area_restore(): freed 28 bytes of working area at address 0x3fc8493c
Debug: 5055 10783 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 5056 10783 target.c:1986 print_wa_layout(): b* 0x3fc84428-0x3fc8493b (1300 bytes)
Debug: 5057 10784 target.c:1986 print_wa_layout():    0x3fc8493c-0x3fca3fff (128708 bytes)
Debug: 5058 10787 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381ce4
Debug: 5059 10788 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 5060 10788 target.c:2206 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381ce4
Debug: 5061 10789 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 5062 10789 target.c:1986 print_wa_layout():    0x40381ce4-0x40383fff (8988 bytes)
Debug: 5063 10790 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84428
Debug: 5064 10798 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84628
Debug: 5065 10805 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84828
Debug: 5066 10810 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 5067 10810 target.c:2206 target_free_working_area_restore(): freed 1300 bytes of working area at address 0x3fc84428
Debug: 5068 10811 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 5069 10811 target.c:1986 print_wa_layout():    0x3fc84428-0x3fca3fff (130008 bytes)
Debug: 5070 10814 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380000
Debug: 5071 10823 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380200
Debug: 5072 10829 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380400
Debug: 5073 10836 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380600
Debug: 5074 10843 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380800
Debug: 5075 10851 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a00
Debug: 5076 10858 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c00
Debug: 5077 10866 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e00
Debug: 5078 10872 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381000
Debug: 5079 10879 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381200
Debug: 5080 10886 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381400
Debug: 5081 10892 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381600
Debug: 5082 10900 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381800
Debug: 5083 10907 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00
Debug: 5084 10914 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00
Debug: 5085 10918 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 5086 10918 target.c:2206 target_free_working_area_restore(): freed 7396 bytes of working area at address 0x40380000
Debug: 5087 10919 target.c:1986 print_wa_layout():    0x40380000-0x40383fff (16384 bytes)
Debug: 5088 10921 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000
Debug: 5089 10927 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200
Debug: 5090 10934 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84400
Debug: 5091 10936 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 5092 10936 target.c:2206 target_free_working_area_restore(): freed 1064 bytes of working area at address 0x3fc84000
Debug: 5093 10937 target.c:1986 print_wa_layout():    0x3fc84000-0x3fca3fff (131072 bytes)
Info : 5094 10937 esp_flash.c:402 esp_flash_get_mappings(): Flash mapping 0: 0x10020 -> 0x3c030020, 50 KB
Info : 5095 10937 esp_flash.c:402 esp_flash_get_mappings(): Flash mapping 1: 0x20020 -> 0x42000020, 142 KB
Info : 5096 10937 esp_flash.c:1005 esp_flash_probe(): Using flash bank 'esp32c3.drom' size 52 KB
Debug: 5097 10938 esp_flash.c:1022 esp_flash_probe(): allocated 13 sectors
Debug: 5098 10938 gdb_server.c:1081 gdb_new_connection(): New GDB Connection: 1, Target esp32c3, state: halted
Debug: 5099 10938 gdb_server.c:401 gdb_log_incoming_packet(): [esp32c3] received packet: qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+
Debug: 5100 10939 riscv.c:1762 riscv_get_gdb_reg_list_internal(): [esp32c3] {0} reg_class=0, read=0
Debug: 5101 10939 gdb_server.c:418 gdb_log_outgoing_packet(): [esp32c3] sending packet: $PacketSize=4000;qXfer:memory-map:read+;qXfer:features:read+;qXfer:threads:read+;QStartNoAckMode+;vContSupported+#02
Debug: 5102 10940 gdb_server.c:401 gdb_log_incoming_packet(): [esp32c3] received packet: -
Warn : 5103 10940 gdb_server.c:501 gdb_put_packet_inner(): negative reply, retrying
Debug: 5104 10940 gdb_server.c:415 gdb_log_outgoing_packet(): [esp32c3] sending packet: $<binary-data-116-bytes>#02
Debug: 5105 10940 gdb_server.c:401 gdb_log_incoming_packet(): [esp32c3] received packet: -
Warn : 5106 10941 gdb_server.c:501 gdb_put_packet_inner(): negative reply, retrying
Debug: 5107 10941 gdb_server.c:415 gdb_log_outgoing_packet(): [esp32c3] sending packet: $<binary-data-120-bytes>#02
Warn : 5108 10941 gdb_server.c:369 gdb_write(): Error writing to GDB socket. Dropping the connection.
Debug: 5109 10941 gdb_server.c:401 gdb_log_incoming_packet(): [esp32c3] received packet: -
Warn : 5110 10941 gdb_server.c:710 gdb_get_packet_inner(): negative acknowledgment, but no packet pending
Debug: 5111 10941 gdb_server.c:401 gdb_log_incoming_packet(): [esp32c3] received packet: +
Debug: 5112 10941 gdb_server.c:362 gdb_write(): GDB socket marked as closed, cannot write to it.
Debug: 5113 10942 gdb_server.c:1126 gdb_connection_closed(): GDB Close, Target: esp32c3, state: halted, gdb_actual_connections=0
Debug: 5114 10942 target.c:1860 target_call_event_callbacks(): target event 8 (gdb-end) for core esp32c3
Debug: 5115 10942 esp32c3.c:188 esp32c3_handle_target_event(): 8
Debug: 5116 10942 esp_riscv.c:281 esp_riscv_handle_target_event(): 8
Debug: 5117 10942 target.c:1860 target_call_event_callbacks(): target event 23 (gdb-detach) for core esp32c3
Debug: 5118 10942 esp32c3.c:188 esp32c3_handle_target_event(): 23
Debug: 5119 10942 esp_riscv.c:281 esp_riscv_handle_target_event(): 23
Info : 5120 10942 server.c:577 server_loop(): dropped 'gdb' connection
[2023-01-05T09:55:53.663Z] SERVER CONSOLE DEBUG: onBackendConnect: gdb-server session closed
GDB server session ended. This terminal will be reused, waiting for next session to start...