Andre Przywara apritzel
apritzel
/ 0001-sunxi-allow-32-bit-builds-for-64-bit-SoCs.patch
Created
January 10, 2025 00:06
allow compiling Allwinner ARMv8 U-Boot port in 32-bit
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| From df83929ef745bcecf8235a38dd5f4dfd33a38b03 Mon Sep 17 00:00:00 2001 | |
| From: Andre Przywara <andre.przywara@arm.com> | |
| Date: Tue, 5 Feb 2019 16:06:24 +0000 | |
| Subject: [PATCH] sunxi: allow 32-bit builds for 64-bit SoCs | |
| At the moment we build the SPL and U-Boot proper for the 64-bit AArch64 | |
| instruction set. But since the cores provide an AArch32 compatibility mode | |
| and in fact the BootROM runs in 32-bit mode, it can be useful to have at | |
| least the SPL run in AArch32 as well. This has two advantages: | |
| - As AArch32 features the compact Thumb2 instruction encoding, we can |
apritzel
/ spl_a523_felret.patch
Created
January 5, 2025 18:15
hack to make U-Boot's SPL return to FEL on A523 (by re-enabling GICv3 interrupts before returning to BROM)
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| diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S | |
| index cee030e4809..42a7c93b97a 100644 | |
| --- a/arch/arm/cpu/armv8/fel_utils.S | |
| +++ b/arch/arm/cpu/armv8/fel_utils.S | |
| @@ -65,7 +65,7 @@ ENTRY(return_to_fel) | |
| /* AArch32 code to restore the state from fel_stash and return back to FEL. */ | |
| back_in_32: | |
| - .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address | |
| + .word 0xe59f0038 // ldr r0, [pc, #56] ; load fel_stash address |
apritzel
/ spl_a523_felret.patch
Created
January 5, 2025 18:14
hack to make U-Boot's SPL return to FEL on A523 (by re-enabling GICv3 interrupts before returning to BROM)
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| diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S | |
| index cee030e4809..87d3fec3c10 100644 | |
| --- a/arch/arm/cpu/armv8/fel_utils.S | |
| +++ b/arch/arm/cpu/armv8/fel_utils.S | |
| @@ -65,7 +65,7 @@ ENTRY(return_to_fel) | |
| /* AArch32 code to restore the state from fel_stash and return back to FEL. */ | |
| back_in_32: | |
| - .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address | |
| + .word 0xe59f0038 // ldr r0, [pc, #56] ; load fel_stash address |
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| #include <stdio.h> | |
| #include <stdint.h> | |
| #include <stdlib.h> | |
| #include <stdbool.h> | |
| #include <getopt.h> | |
| #include <arpa/inet.h> // for htonl | |
| struct fdt_header { | |
| uint32_t magic; | |
| uint32_t totalsize; |
apritzel
/ a133_dram_reg_dump.diff
Created
October 28, 2024 01:29
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| --- boot0_dump.txt 2024-10-28 01:24:13.359531938 +0000 | |
| +++ mainline_dump.txt 2024-10-28 01:24:47.493533236 +0000 | |
| @@ -1,3 +1,7 @@ | |
| + | |
| +U-Boot SPL 2024.10-01148-gfb3331564c68-dirty (Oct 27 2024 - 10:48:49 +0000) | |
| +DRAM:cols = 10, rows = 16, banks = 3, bankgrps = 0, ranks = 0, full_width = 1 | |
| +DRAM simple test FAIL----- address 0000000040000000 = 19070976 | |
| 04820000: c1080020 00000001 00000001 00000001 | |
| 04820010: 00000030 00001626 00000000 00000000 | |
| 04820020: 00000000 00800000 00000001 00000001 |
apritzel
/ clk_sunxi-ng_h616_cpu_notifier.patch
Created
October 24, 2024 00:44
H616 CPU clock notifier patch, to reparent CPU to PLL_PERI0 during DVFS frequency change
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| commit 5791b78a20997f5bae3e8c5fbdd444dc6a692ae9 | |
| Author: Andre Przywara <andre.przywara@arm.com> | |
| Date: Thu Oct 24 01:25:45 2024 +0100 | |
| clk: sunxi-ng: h616: Reparent CPU clock during frequency changes | |
| The H616 user manual recommends to re-parent the CPU clock during | |
| frequency changes of the PLL, and recommends PLL_PERI0(1X), which runs | |
| at 600 MHz. | |
apritzel
/ find_dtbs.c
Created
May 30, 2024 23:58
find_dtbs: scan a binary file for devicetree binary magic bytes, and allow extracting the DTBs
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| // SPDX-License-Identifier: GPL-2.0-only | |
| // Copyright (C) 2018-2024 Andre Przywara <osp@apritzel.eu> | |
| #include <stdio.h> | |
| #include <stdint.h> | |
| #include <stdlib.h> | |
| #include <stdbool.h> | |
| #include <getopt.h> | |
| #include <arpa/inet.h> // for htonl |
apritzel
/ u-boot_h616_high_boot.patch
Created
May 2, 2024 10:17
U-Boot H616 SPL at 256KB MMC offset booting support
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| commit 5e9a281c9f9b50f22fdba619ca3a0f8788224ef3 | |
| Author: Andre Przywara <andre.przywara@arm.com> | |
| Date: Thu Mar 28 16:18:12 2024 +0000 | |
| UNTESTED! H616 high location boot support | |
| Signed-off-by: Andre Przywara <andre.przywara@arm.com> | |
| diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c | |
| index 0140b07d32a..046e9fbfc67 100644 |
apritzel
/ d1_pwm_refactor_for_h616.patch
Created
April 29, 2024 15:52
Allwinner D1 PWM driver refactoring patch to accommodate H616 PWM IP
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| Author: Andre Przywara <andre.przywara@arm.com> | |
| Date: Wed Sep 6 21:04:05 2023 +0100 | |
| pwm: sun20i: Refactor channel enablement | |
| When enabling or disabling a PWM channel, we also ungate and gate the | |
| respective clock at the same time. | |
| Factor this out into a separate function, to simplify extending the | |
| driver to other SoCs, where the clock gate is located in a different |
apritzel
/ rg35xx_plus_dt_update.patch
Created
March 6, 2024 01:09
Updated DT sketch for Anbernic RG35xx Plus, partly commented
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| diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts | |
| index e2674af0c4661..dc25bfe09fac2 100644 | |
| --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts | |
| +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts | |
| @@ -8,6 +8,7 @@ | |
| #include "sun50i-h616.dtsi" | |
| #include <dt-bindings/gpio/gpio.h> | |
| +#include <dt-bindings/input/linux-event-codes.h> | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |