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commit 3a4c07b5f6db324a27b16e40d4185479752401b5
Author: Andre Przywara <[email protected]>
Date:   Wed Jan 8 00:36:38 2025 +0000

    add first Liontron-A133 board support

diff --git a/configs/liontron-h-a133l_defconfig b/configs/liontron-h-a133l_defconfig
new file mode 100644
index 00000000000..bb8a1cdfb57
--- /dev/null

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diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
index c9d075ac8..9543dbeaa 100644
--- a/plat/allwinner/common/include/platform_def.h
+++ b/plat/allwinner/common/include/platform_def.h
@@ -72,7 +72,7 @@
 #define PLATFORM_CLUSTER_COUNT		U(1)
 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER_COUNT * \
 					 PLATFORM_MAX_CPUS_PER_CLUSTER)
-#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(8)

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From df83929ef745bcecf8235a38dd5f4dfd33a38b03 Mon Sep 17 00:00:00 2001
From: Andre Przywara <[email protected]>
Date: Tue, 5 Feb 2019 16:06:24 +0000
Subject: [PATCH] sunxi: allow 32-bit builds for 64-bit SoCs

At the moment we build the SPL and U-Boot proper for the 64-bit AArch64
instruction set. But since the cores provide an AArch32 compatibility mode
and in fact the BootROM runs in 32-bit mode, it can be useful to have at
least the SPL run in AArch32 as well. This has two advantages:
- As AArch32 features the compact Thumb2 instruction encoding, we can

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diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index cee030e4809..42a7c93b97a 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -65,7 +65,7 @@ ENTRY(return_to_fel)
 
 /* AArch32 code to restore the state from fel_stash and return back to FEL. */
 back_in_32:
-	.word	0xe59f0028	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe59f0038	// ldr	r0, [pc, #56]	; load fel_stash address

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diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index cee030e4809..87d3fec3c10 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -65,7 +65,7 @@ ENTRY(return_to_fel)
 
 /* AArch32 code to restore the state from fel_stash and return back to FEL. */
 back_in_32:
-	.word	0xe59f0028	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe59f0038	// ldr	r0, [pc, #56]	; load fel_stash address

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#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <getopt.h>
#include <arpa/inet.h>		// for htonl

struct fdt_header {
	uint32_t magic;
	uint32_t totalsize;

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--- boot0_dump.txt	2024-10-28 01:24:13.359531938 +0000
+++ mainline_dump.txt	2024-10-28 01:24:47.493533236 +0000
@@ -1,3 +1,7 @@
+
+U-Boot SPL 2024.10-01148-gfb3331564c68-dirty (Oct 27 2024 - 10:48:49 +0000)
+DRAM:cols = 10, rows = 16, banks = 3, bankgrps = 0, ranks = 0, full_width = 1
+DRAM simple test FAIL----- address 0000000040000000 = 19070976
 04820000: c1080020 00000001 00000001 00000001
 04820010: 00000030 00001626 00000000 00000000
 04820020: 00000000 00800000 00000001 00000001

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commit 5791b78a20997f5bae3e8c5fbdd444dc6a692ae9
Author: Andre Przywara <[email protected]>
Date:   Thu Oct 24 01:25:45 2024 +0100

    clk: sunxi-ng: h616: Reparent CPU clock during frequency changes
    
    The H616 user manual recommends to re-parent the CPU clock during
    frequency changes of the PLL, and recommends PLL_PERI0(1X), which runs
    at 600 MHz.
    

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// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2018-2024 Andre Przywara <[email protected]>

#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <getopt.h>
#include <arpa/inet.h>		// for htonl

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commit 5e9a281c9f9b50f22fdba619ca3a0f8788224ef3
Author: Andre Przywara <[email protected]>
Date:   Thu Mar 28 16:18:12 2024 +0000

    UNTESTED! H616 high location boot support
    
    Signed-off-by: Andre Przywara <[email protected]>

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 0140b07d32a..046e9fbfc67 100644