axayjha

module datapath (eqz, LdA, LdB, LdP, clrP, decB, data_in, clk);
	input LdA, LdB, LdP, clrP, decB, clk;
	input [15:0] data_in;
	output eqz;
	wire [15:0] x, y, z, Bout, Bus;

	PIPO_R1 A (x, data_in, LdA, clk);
	PIPO_R2 P (y, z, LdP, clrP, clk);
	counter B (Bout, data_in, LdB, decB, clk);
	add AD (z, x, y);

axayjha

module counter (dout, din, ld, dec, clk);
	input [15:0] din;
	input ld, dec, clk;
	output reg [15:0] dout;

	always @(posedge clk)
		if (ld) dout <= din;
		else if (dec) dout <= dout - 1;
		
endmodule		

axayjha

module comparator (eqz, data);
	input [15:0] data;
	output eqz;
	assign eqz = (data == 0);
endmodule

axayjha

module add (out, in1, in2);
	input [15:0] in1, in2;
	output reg [15:0] out;
	always @(*)
		out = in1 + in2;
endmodule		

axayjha

module PIPO_R2 (dout, din, ld, clr, clk);
	input [15:0] din;
	input ld, clr, clk;
	output reg [15:0] dout;

	always @(posedge clk)
                // if clear signal is on, set register value to 0
		if (clr) dout <= 16'b0;
                // else if load signal is on, load new data
		else if (ld) dout <= din;

axayjha

module PIPO_R1 (dout, din, ld, clk);
	input [15:0] din;
	input ld, clk;
	output reg [15:0] dout;

	always @(posedge clk)
                // if load signal is on, load new data
		if (ld) dout <= din;
endmodule		

axayjha

module test;

  /* Make a reset that pulses once. */
  reg reset = 0;
  initial begin
     $dumpfile("test.vcd");
     $dumpvars(0,test);

     # 17 reset = 1;
     # 11 reset = 0;

axayjha

module counter(out, clk, reset);

  parameter WIDTH = 8;

  output [WIDTH-1 : 0] out;
  input            clk, reset;

  reg [WIDTH-1 : 0]   out;
  wire            clk, reset;

axayjha

module alu_tb;
	reg[3:0]a;
	reg[3:0]b;
	reg[2:0]s;
	wire[7:0]y;
	alu a1(a,b,s,y);
	

  initial begin

axayjha

module alu(a,b,s,y);
	input[3:0]a;
	input[3:0]b;
	input[2:0]s;
	output[7:0]y;
	reg[7:0]y;
	always@(a,b,s)
	begin
		case(s)
			3'b000:y=a+b;