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Nikolay Bildeyko bildeyko

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bildeyko / demux1to4.v
Created October 13, 2016 19:02
`timescale 1ns / 1ps
module demux1to4(
input Data_i,
input[1:0] sel,
output reg Data_1_o,
output reg Data_2_o,
output reg Data_3_o
);
@bildeyko
bildeyko / spi.v
Last active October 13, 2016 19:03
`timescale 1ns / 1ps
module spi(
input clk_i,
input rst_i,
input miso_i,
output mosi_o,
output sck_o,
input start_i,
input [1:0]slave_i,
@bildeyko
bildeyko / spi_test.v
Created October 13, 2016 19:01
`timescale 1ns / 1ps
module spi_test(
);
reg clk = 0, rst = 1;
reg start = 0;
reg[7:0] data_in = 8'b10101101;