spi_test.v

`timescale 1ns / 1ps


module spi_test(

    );
    
    reg clk = 0, rst = 1;
    reg start = 0;
    reg[7:0] data_in = 8'b10101101;
    wire[7:0] data_out;
    wire busy;
    wire ready;
    
    reg[1:0]  miso = 1'b1;
    wire mosi;
    wire sck;
    
    reg[1:0] slave = 2'b00;
    wire ss1_o, ss2_o, ss3_o;
    
    // dut - device under test
    spi dut ( 
        .clk_i(clk),
        .rst_i(rst),
        .miso_i(miso),
        .mosi_o(mosi),
        .sck_o(sck),
        .start_i(start),
        .slave_i(slave),
        .ss1_o(ss1_o),
        .ss2_o(ss2_o),
        .ss3_o(ss3_o),
        .data_in_bi(data_in),
        .data_out_bo(data_out),
        .busy_o(busy),
        .ready_o(ready)
    );
    
    initial begin
        $display("Running testbench");
        #100;
        rst = 1;
        slave = 2'b01;
        
        #150;
        rst = 0;
        start = 1;
        
        #200;
        start = 0;
        
        #4000;
        rst = 1;
        data_in = 8'b11100111;
        
        #4010
        rst = 0;
        start = 1;
        
        #4010
        start = 0;
        
        #4150
        miso = 1'b0;
        
        #4250
        miso = 1'b1;
        
        #8500
        rst = 1;
    end
    
    always 
        #50 clk = !clk;
    
endmodule