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buttercutter / LNA1.asc
Last active August 16, 2019 08:30
a LNA circuit from the book "Design of CMOS RF Integrated Circuits and Systems"
Version 4
SHEET 1 1172 852
WIRE 144 80 0 80
WIRE 256 80 144 80
WIRE 368 80 256 80
WIRE 480 80 368 80
WIRE 592 80 480 80
WIRE 0 128 0 80
WIRE 144 144 144 80
WIRE 480 144 480 80
@buttercutter
buttercutter / clock_gate.v
Last active August 14, 2019 02:07
A formally verified synchronous fifo with clock gating feature
// Credits : https://github.com/YosysHQ/yosys-bigsim/blob/master/openmsp430/rtl/omsp_clock_gate.v
module clock_gate (
// OUTPUTs
gclk, // Gated clock
// INPUTs
clk, // Clock
enable_in // Clock enable
@buttercutter
buttercutter / dff.sby
Last active September 2, 2019 10:46
D flip-flop with asynchronous reset
[tasks]
proof
cover
[options]
proof: mode prove
proof: depth 50
cover: mode cover
cover: depth 30
@buttercutter
buttercutter / mosfet_018.lib
Last active April 14, 2019 12:37
A three stage opamp from http://asco.sourceforge.net/doc/ASCO.pdf#page=40
* modified for use with LTSpice; DM 8/19/2008
*
* 0.18u CMOS process
*
* NMOS transistor model name: NM
* PMOS transistor model name: PM
*-----------------------------------------------------------------------
.subckt NM D G S B
@buttercutter
buttercutter / mosfet_018.lib
Created March 29, 2019 01:37
gilbert cell mixer circuit
* modified for use with LTSpice; DM 8/19/2008
*
* 0.18u CMOS process
*
* NMOS transistor model name: NM
* PMOS transistor model name: PM
*-----------------------------------------------------------------------
.subckt NM D G S B
@buttercutter
buttercutter / NoC.v
Last active May 9, 2020 08:15
Spidergon Networks On Chip
module NoC
#(
`ifdef FORMAL
parameter NUM_OF_NODES=8,
parameter FLIT_DATA_WIDTH=8,
parameter NODE_BUFFER_WIDTH=16,
`else
parameter NUM_OF_NODES=8,
parameter FLIT_DATA_WIDTH=16,
parameter NODE_BUFFER_WIDTH=32, // a single vc buffer can hold 2 flits at one time
@buttercutter
buttercutter / multiply.sby
Last active February 20, 2019 01:13
A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm
[tasks]
proof
cover
[options]
proof: mode prove
proof: depth 5
cover: mode cover
cover: depth 20
@buttercutter
buttercutter / CMOS_Inverter.sch
Last active January 31, 2019 07:57
CMOS inverter test circuit https://github.com/promach/frequency_trap/blob/development/test_CMOS_Inverter.sch
v 20130925 2
C 40000 40000 0 0 0 title-B.sym
C 50000 46900 1 0 0 asic-pmos-1.sym
{
T 51400 47700 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 50900 47700 5 10 1 1 0 0 1
refdes=M2
T 50900 47500 5 8 1 1 0 0 1
model-name=P1
@buttercutter
buttercutter / bimpy.v
Last active January 22, 2019 03:54
Signed Multiplier verilog code from https://github.com/ZipCPU/fwmpy
////////////////////////////////////////////////////////////////////////////////
//
// Filename: bimpy
//
// Project: A multiply core generator
//
// Purpose: An unsigned 2-bit multiply based upon the fact that LUT's allow
// 6-bits of input, but a 2x2 bit multiply will never carry more
// than one bit. While this multiply is hardware independent, it is
// really motivated by trying to optimize for a specific piece of
@buttercutter
buttercutter / circ_ring.h
Created January 9, 2019 08:27
Modified https://github.com/KastnerRG/riffa/blob/master/driver/linux/circ_queue.h using kernel built-in ptr_ring struct
/*
* Filename: circ_ring.h
* Version: 1.0
* Description: A circular buffer using API from
* https://github.com/torvalds/linux/blob/master/include/linux/ptr_ring.h
*/
// enables https://github.com/torvalds/linux/blob/master/include/linux/ptr_ring.h#L24-L32
#define __KERNEL__ 1