cfelton

import myhdl as hdl
from myhdl import Signal, ResetSignal, intbv, always_seq

@hdl.block
def test_mem_ivs_convert(clock, reset, wr, wrd, rdd, addr):
    return memory(clock, reset, wr, wrd, rdd, addr)

@hdl.block
def memory(clock, reset, wr, wrd, rdd, addr):
    mem = [Signal(intbv(0, min=wrd.min, max=wrd.max)) 

cfelton

from random import randint

import myhdl
from myhdl import Signal, intbv, always, delay, instance, StopSimulation


def bit_length(num):
    """Determine the number of bits required to represent a value 

cfelton

from random import randint

import myhdl
from myhdl import Signal, ResetSignal, intbv, always_seq, always_comb
from myhdl import instance, delay, StopSimulation
from myhdl.conversion import verify

try:
    from rhea import Signals

cfelton

from myhdl import Signal, intbv

class SomeInterface(object):
  def __init__(self, clock):
    self.clock = clock
    self.datain = Signa(intbv(0)[8:])
    self.dataout = Signal(intbv(0)[8:])
    self.data_valid = Signal(bool(0))
    

cfelton

class FIFOBus(object):
    def __init__(self, size=16, width=8):
        """
        """
        self.name = "fifobus{0}".format(_fb_num)

        # @todo: add write clock and read clock to the interface!
        # @todo: use longer names read, read_valid, read_data,
        # @todo: write, write_data, etc.!

cfelton

def ram_rom_compare1(xram, yrom, num_matches):
    assert len(xram) == len(yrom)
    numitems = len(xram)
    @always_comb
    def compare():
        count = 0
        for ii in range(numitems):
            if xram[ii] == yrom[ii]:
                count = count + 1
        num_matches.next = count

cfelton

import myhdl
from myhdl import Signal, intbv, always_comb


class Intf1(object):
    def __init__(self):
        self.a = Signal(intbv(0, min=0, max=2))
        self.b = Signal(intbv(0, min=0, max=4))
        self.c = Signal(intbv(0, min=0, max=8))

cfelton

import myhdl
from myhdl import instance, delay, now

def test():
  @instance
  def tbstim():
    yield delay(10)
    print("{:<8d} ".format(now()))
    yield delay(1000)

cfelton

@always_seq(clock.posedge, reset=reset)
def beh_sop():
    # tap update loop
    xd[0].next = x
    for ii in range(1, len(h)):
        xd[ii].next = xd[ii-1]
        
    # sum-of-products loop
    sop = 0
    for ii in range(len(h)):

cfelton

import argparse
from argparse import Namespace

from myhdl import *


class Constants(object):
    def __init__(self, **constargs):
        # the const can contain int and str convert all to int