ram_rom_compare1.py

def ram_rom_compare1(xram, yrom, num_matches):
    assert len(xram) == len(yrom)
    numitems = len(xram)
    @always_comb
    def compare():
        count = 0
        for ii in range(numitems):
            if xram[ii] == yrom[ii]:
                count = count + 1
        num_matches.next = count

    return compare

ram_rom_compare2.py

def ram_rom_compare2(xram, yrom, num_matches):
    assert len(xram) == len(yrom)
    numitems = len(xram)
    @always_comb
    def compare():
        count = 0
        for ii in range(numitems):
            romii = yrom[ii]
            if xram[ii] == romii:
                count = count + 1
        num_matches.next = count

    return compare

test_ram_rom_compare.py

def test_convert_compare():
    numitems = 12
    xram = [Signal(intbv(randint(-8, 7), min=-8, max=8)) for _ in range(numitems)]
    yrom = tuple([randint(-8, 7) for _ in range(numitems)])
    matches = len([True for x, y in zip(xram, yrom) if x == y])
    print(list(map(int, xram)))
    print(yrom)
    print(matches)
    
    num_matches1 = Signal(intbv(0, min=0, max=numitems+1))
    num_matches2 = Signal(intbv(0, min=0, max=numitems+1))
    
    tbdut1 = ram_rom_compare1(xram, yrom, num_matches1)
    tbdut2 = ram_rom_compare2(xram, yrom, num_matches2)
    
    @instance
    def tbstim():
        yield delay(10)
        assert matches == num_matches1 == num_matches2
        raise StopSimulation
        
    Simulation((tbdut1, tbdut2, tbstim)).run()
    
    def top_wrapper(mod=1):
        xram = [Signal(intbv(randint(-8, 7), min=-8, max=8)) for _ in range(numitems)]
        yrom = tuple([randint(-8, 7) for _ in range(numitems)])
        if mod == 1:
            g = ram_rom_compare1(xram, yrom, num_matches1)
        elif mod == 2:
            g = ram_rom_compare2(xram, yrom, num_matches2)
        return g
        
    del xram, yrom  
    # the direct access to rom will fail to convert  
    try:
        toVerilog(top_wrapper, 1)
    except:
        print("module 1 failed")
        
    # accessing separately will convert
    toVerilog(top_wrapper, 2)