Example of a convertible testbench with an instantiation

button_debouncer.py

from __future__ import division
from __future__ import print_function

from myhdl import *

def ButtonDebouncer(clk_i, button_i, button_o):
    button_o.driven = True

    @always(clk_i.posedge)
    def rtl():
        button_o.next = button_i

    ButtonDebouncer.vhdl_instance = 'ButtonDebounder'
    return rtl

def test_button_debounce():
    """ A convertible testbnech
    """
    clk_i = Signal(bool(0))
    btn_i = Signal(bool(0))
    btn_o = Signal(bool(0))

    tbdut = ButtonDebouncer(clk_i, btn_i, btn_o)

    @instance
    def tbclk():
        clk_i.next = False
        while True:
            yield delay(3)
            clk_i.next = not clk_i

    @instance
    def tbstim():
        # @todo: add min pulses that should make it through
        #    the debouncer

        for ii in range(10):
            print("btn_i: %d, btn_o: %d" % (btn_i, btn_o,))
            btn_i.next = ii
            yield clk_i.posedge

        raise StopSimulation

    return tbdut, tbclk, tbstim

Simulation(test_button_debounce()).run()
toVHDL(test_button_debounce)

test_button_debounce.vhd

-- File: test_button_debounce.vhd
-- Generated by MyHDL 0.9.dev0
-- Date: Thu Apr  9 10:21:03 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity test_button_debounce is
end entity test_button_debounce;
-- A convertible testbnech
--     

architecture MyHDL of test_button_debounce is





signal btn_i: std_logic;
signal clk_i: std_logic;
signal btn_o: std_logic;

begin



ButtonDebounder: entity work.ButtonDebouncer(MyHDL)
    port map (
        clk_i=>clk_i,
        btn_i=>btn_i,
        btn_o=>btn_o
    );


TEST_BUTTON_DEBOUNCE_TBCLK: process is
begin
    clk_i <= '0';
    while True loop
        wait for 3 ns;
        clk_i <= stdl((not bool(clk_i)));
    end loop;
    wait;
end process TEST_BUTTON_DEBOUNCE_TBCLK;


TEST_BUTTON_DEBOUNCE_TBSTIM: process is
    variable L: line;
begin
    for ii in 0 to 10-1 loop
        write(L, string'("btn_i: "));
        write(L, to_integer(btn_i));
        write(L, string'(", btn_o: "));
        write(L, to_integer(btn_o));
        writeline(output, L);
        btn_i <= stdl(ii mod 2);
        wait until rising_edge(clk_i);
    end loop;
    assert False report "End of Simulation" severity Failure;
    wait;
end process TEST_BUTTON_DEBOUNCE_TBSTIM;

end architecture MyHDL;