A usecase (possible) for SliceSignals being passed around (unresolved issue?)

upperlower.py

from myhdl import *

def uppermod(clock, reset, x, y):
    fullstatus = Signal(intbv(0)[32:])
    substatus = fullstatus(16,0)
    z1 = Signal(intbv(0)[4:])    
    z2 = Signal(intbv(0)[4:])
        
    inst = lowermod(substatus, z1, z2)
        
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        fullstatus.next = fullstatus ^ x
        y.next = concat(substatus, z2, z1)
    return inst, rtl


def lowermod(status, z1, z2):
    subsub1 = status(4,0)    
    subsub2 = status(8,4)
    @always_comb
    def rtl():
        z1.next = subsub1 & 0x55
        z2.next = subsub2 & 0xAA
    return rtl


clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
x = Signal(intbv(0)[32:])
y = Signal(intbv(0)[32:])
toVerilog(uppermod, clock, reset, x, y)

upperlower.v

// File: uppermod.v
// Generated by MyHDL 0.9.dev0
// Date: Sun Apr  5 09:08:22 2015


`timescale 1ns/10ps

module uppermod (
    clock,
    reset,
    x,
    y
);


input clock;
input reset;
input [31:0] x;
output [31:0] y;
reg [31:0] y;

reg [31:0] fullstatus;
wire [3:0] z1;
wire [3:0] z2;


assign z1 = (0 & 85);
assign z2 = (0 & 170);


always @(posedge clock, negedge reset) begin: UPPERMOD_RTL
    if (reset == 0) begin
        y <= 0;
        fullstatus <= 0;
    end
    else begin
        fullstatus <= (fullstatus ^ x);
        y <= {fullstatus[16-1:0], z2, z1};
    end
end

endmodule