A template for MyHDL testbenchds

testbench_template.py

import myhdl
from myhdl import Signal, intbv, instance, delay, StopSimulation


def testbench_template(args=None):
    # any code to extract argument for what is desired to be tested
  
    # instantiate all signals and interface 
  
    @myhdl.block
    def bench_template():
        # use an embedded function, then all the testbench signals
        # can be traced as well as the DUT
        tbdut = design_under_test()
        
        @always(delay(5))
        def tbclk():
            clock.next = not clock
            
        @instance
        def tbstim():
            # put all the testbench stimulus here
            yeild delay(100)
            raise StopSimulation
            
        return tbdut, tbclk, tbstim
        
    # use arguments to determine if trace or not
    inst = bench_template()
    inst.sim_config(trace=True)
    inst.sim_run()