An example of creating lots of instances (large conversion file)

many_pe.py

from datetime import datetime
dtnow = datetime.now
from pprint import pprint

from myhdl import *
import gizflo as gf

def m_pe(clock, x, y, z, zu, zl, a=2, b=4):
    

    @always(clock.posedge)
    def rtl():
        # some operation
        z.next = ((x*y)+(x-b))*a

    @always_comb
    def rtlul():
        zu.next = z[32:16].signed()
        zl.next = z[16:0].signed()

    return rtl, rtlul


def m_many_pe(clock, sdi, sdo):

    # the number of PEs to instantiate
    N = 4

    xmax = 3568
    x = Signal(intbv(0, min=-xmax, max=xmax))
    y = Signal(intbv(0, min=-xmax, max=xmax))

    zmax = 2**31
    z = [Signal(intbv(0, min=-zmax, max=zmax))
         for _ in range(N)]
    
    xz = Signal(intbv(0, min=-zmax, max=zmax))

    assert len(z[0]) == 32
    zmx = 2**15  
    zl = [Signal(intbv(0, min=-zmx, max=zmx)) for _ in range(N)]
    zu = [Signal(intbv(0, min=-zmx, max=zmx)) for _ in range(N)]
    
    # processing elemetns
    glpe = [None for _ in range(N)]
    
    
    glpe[0] = m_pe(clock, x, y, z[0], zu[0], zl[0])
    for ii in range(1, N):
        glpe[ii] = m_pe(clock, zu[ii-1], zl[ii-1], 
                        z[ii], zu[ii], zl[ii])

    # something to keep the logic around
    # @todo: replace with serio
    @always(clock.posedge)
    def rtl_keep():
        if sdi:
            x.next = (x >> 1) ^ 0xD4
        else:
            x.next = x - 1
    
        y.next = (x >> 2) + (y >> 8)
        xz.next = x * y
    
        if z[N-1] > xz:
            sdo.next = True
        else:
            sdo.next = False 
    
    return rtl_keep, glpe
    

#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
clock = Signal(bool(0))
sdi,sdo = [Signal(bool(0)) for _ in range(2)]

# convert to Verilog (testing)
ts = dtnow()
toVerilog(m_many_pe, clock, sdi, sdo)
print(dtnow()-ts)

# convert to VHDL (testing)
ts = dtnow()
toVHDL(m_many_pe, clock, sdi, sdo)
print(dtnow()-ts)

def _test():
    tbdut = traceSignals(m_many_pe, clock, sdi, sdo)
    @always(delay(3))
    def tbclk():
        clock.next = not clock
    @instance
    def tbstim():
        for ii in range(1111):
            yield clock.posedge
        raise StopSimulation
    return tbdut, tbclk, tbstim

# run a quick sim
Simulation(_test()).run()

# run it through and FPGA toolchain targetted for a board
ts = dtnow()
brd = gf.get_board('xula2')
brd.add_port('sdi', pins=('R7',))
brd.add_port('sdo', pins=('R15',))
flo = brd.get_flow(top=m_many_pe)
flo.run()

info = flo.get_utilization()
pprint(info)
print(dtnow()-ts)

output.txt

tbd