example of large bit-vector concats

largeconcat.py

from myhdl import *

def largeconcat(clock, reset, addr, oldest_addr, newest_addr):
    addr_array = Signal(intbv(0)[459:0])
    wrapaddr = modbv(0)[23:0]
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        wrapaddr[:] = addr-1
        addr_array.next = concat(addr_array[436:0], wrapaddr)
        
        # this example has a mismatch in size, the left-hand
        # side is 23bits and the right 22bits
        oldest_addr.next = addr_array[459:437]
        newest_addr.next = addr_array[22:0]
    return rtl

clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
addr = Signal(intbv(0)[23:])
oldest_addr = Signal(intbv(0)[23:])
newest_addr = Signal(intbv(0)[23:])
toVerilog(largeconcat, clock, reset, addr, oldest_addr, newest_addr)
toVHDL(largeconcat, clock, reset, addr, oldest_addr, newest_addr)

largeconcat.v

 
        wrapaddr = (addr - 1);
        addr_array <= {addr_array[436-1:0], wrapaddr};
        oldest_addr <= addr_array[459-1:437];
        newest_addr <= addr_array[22-1:0];

largeconcat.vhd

        wrapaddr := (addr - 1);
        addr_array <= unsigned'(addr_array(436-1 downto 0) & wrapaddr);
        oldest_addr <= resize(addr_array(459-1 downto 437), 23);
        newest_addr <= resize(addr_array(22-1 downto 0), 23);