bug_github44.py

def m_int_case(clock, reset, x, y):

    @always_seq(clock.posedge, reset=reset)
    def rtl():
        z = (x >> 16) & 0x3
        if z == 0:
            y.next = y - 0xDECAFBAD
        elif z == 1:
            y.next = x + 0xC0FFEE
        elif z == 2:
            y.next = y + 2
        else:
            y.next = 299792458
    return rtl


clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=False)
x = Signal(intbv(0, min=0, max=444356))
y = Signal(intbv(0)[32:])
toVerilog(m_int_case, clock, reset, x, y)

test_bug_github44.py

reset = ResetSignal(0, active=0, async=False)
x = Signal(intbv(0, min=0, max=444356))
y = Signal(intbv(0)[32:])

def test():
    tbdut = m_int_case(clock, reset, x, y)
    @always(delay(3))
    def tbclk():
        clock.next = not clock
    @instance
    def tbstim():
        reset.next = reset.active
        yield delay(33)
        reset.next = not reset.active
        yield clock.posedge
        for ii in range(13):
            x.next = randint(0, 444355)
            yield clock.posedge
            print("{:08X} {:08X}".format(int(x), int(y)))
        raise StopSimulation
    return tbdut, tbclk, tbstim
Simulation(traceSignals(test)).run()