myhdl_issue43.py

from __future__ import print_function

from random import randint
from myhdl import *

def m_top_const(clock, reset, x, y, a, b, N=10):
    # a tuple of constant ints
    coef = tuple([(randint(-19,23), randint(0,127),) 
                 for _ in range(N)])

    v = [Signal(x.val) for _ in range(N-1)]
    glist = [None for _ in range(N)]

    # create multiple instances
    glist[0] = m_constants(clock, reset, x, a, b, coef[0])
    for ii in range(1,N):
        # append the constant module to the list of generators
        glist[ii] = m_constants(clock, reset, v[ii-1], a, b, coef[ii])
        
    # combine all the outputs into one output
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        psum = 0          # sorta declaring the variable
        psum = psum + x   # initial value of the variable
        for ii in range(1,N):
            psum = psum + v[ii-1]
        y.next = psum

    # attach for whitebox testing
    m_top_const.coef = coef

    return glist, rtl


def m_constants(clock, reset, x, a, b, coef):
    # use fixed indexes from the coef
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        x.next = a*coef[0] + b*coef[1]

    return rtl


def test_constant():
    clock = Signal(bool(0))
    reset = ResetSignal(0, active=0, async=True)
    x = Signal(intbv(0, min=-233, max=544))
    y = Signal(intbv(0, min=-2*18, max=1111*13))
    a = Signal(intbv(0, min=-19, max=17))
    b = Signal(intbv(0, min=-3, max=37))

    # a test function
    def _test():
        # instantiate the design under test
        tbdut = m_top_const(clock, reset, x, y, a, b)
        coef = m_top_const.coef

        @always(delay(3))
        def tbclk():
            clock.next = not clock

        @instance
        def tbstim():
            reset.next = reset.active
            yield delay(33)
            reset.next = not reset.active
            
            yield clock.posedge
            yield clock.posedge
            
            psum = 0
            for vals in coef:
                psum = psum + (a*vals[0] + b*vals[1]) 
    
            assert psum == y

            raise StopSimulation

        return tbdut, tbclk, tbstim

    
    Simulation(_test()).run()
    print("** Simulation Successfull **")
    toVHDL(m_top_const, clock, reset, x, y, a, b)
    toVerilog(m_top_const, clock, reset, x, y, a, b)


if __name__ == '__main__':
    test_constant()