vhdl_user_code.py

def vhdl_stub(sigi, sigo):
    vhdl_stub.id = vhdl_stub.id + 1
    this_id = vhdl_stub.id
    @always_comb
    def assign():
        sigo.next = not sigi
    return assign
vhdl_stub.vhdl_code ="""
foo_bar_$this_id: entity work.blah(myhdl)
"""
vhdl_stub.id = 0
    
def top_user_code(sigi, sigo):
    sig = Signal(bool(0))
    g1 = vhdl_stub(sigi, sig)
    g2 = vhdl_stub(sig, sigo)
    return g1, g2

sigi, sigo = [Signal(bool(0)) for _ in range(2)]
toVHDL(top_user_code, sigi, sigo)

zzz_top_user_code.vhd

-- File: top_user_code.vhd
-- Generated by MyHDL 0.9.dev0
-- Date: Mon Jun  8 07:37:39 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity top_user_code is
    port (
        sigi: in std_logic;
        sigo: in std_logic
    );
end entity top_user_code;


architecture MyHDL of top_user_code is
begin

foo_bar_1: entity work.blah(myhdl)
foo_bar_2: entity work.blah(myhdl)

end architecture MyHDL;