MyHDL shadow of shadows issue (is this intended to be a supported feature?)

shadows_user_verilog.py

import myhdl
print(myhdl.__version__)
from myhdl import *

def add_example(CLK, IN_1, IN_2, SUM_OUT):
 
     SUM_OUT.driven = 'reg'
     IN_1.read = True
     IN_2.read = True
 
     in1_part = IN_1(10,0)
     in2_part = IN_2(10,0)
 
     part_of_in1_part = in1_part(5,2)
     part_of_in2_part = in2_part(5,2)
 
     #This always block isn't exactly like the verilog code.
     @always(CLK.posedge)
     def adding():
         SUM_OUT.next = IN_1 + IN_2
 
     return adding
 
add_example.verilog_code = \
"""
 always @(posedge $CLK) begin:
     $SUM_OUT[11-1:0] <= $in1_part + $in2_part;
     $SUM_OUT[32:28] <= $part_of_in1_part + $part_of_in2_part
 end
 """
 

clk = Signal(bool(0))
in1 = Signal(intbv(0)[32:])
in2 = Signal(intbv(0)[32:])
sum_out = Signal(intbv(0)[32:])
toVerilog(add_example, clk, in1, in2, sum_out)

shadows_user_verilog.v

// File: add_example.v
// Generated by MyHDL 0.9dev
// Date: Thu Apr  2 13:30:37 2015


`timescale 1ns/10ps

module add_example (
    CLK,
    IN_1,
    IN_2,
    SUM_OUT
);


input CLK;
input [31:0] IN_1;
input [31:0] IN_2;
output [31:0] SUM_OUT;
reg [31:0] SUM_OUT;


 always @(posedge CLK) begin:
     SUM_OUT[11-1:0] <= in1[10-1:0] + in2[10-1:0];
     SUM_OUT[32:28] <= 0 + 0
 end
 
endmodule