example_nonlocal.py

import myhdl
from myhdl import Signal
from myhdl import intbv
from myhdl import instance
from myhdl import always


def example_instance(clock, rx_bit_cnt, restart, tomax=111):

    @instance
    def rtl():
        tocnt = 0
        while True:
            yield clock.posedge
            restart.next = False
            if rx_bit_cnt == 8:
                tocnt = 0
            elif tocnt == tomax:
                restart.next = True
                tocnt = 0
            else:
                tocnt += 1

    return rtl


def example_nonlocal(clock, rx_bit_cnt, restart, tomax=111):
    
    tocnt = 0
    @always(clock.posedge)
    def rtl():
        nonlocal tocnt
        restart.next = False
        if rx_bit_cnt == 8:
            tocnt = 0
        elif tocnt == tomax:
            restart.next = True
            tocnt = 0
        else:
            tocnt += 1

    return rtl


def test():
    tomax = 16
    clock = Signal(bool(0))
    rx_bit_cnt = Signal(intbv(0, min=0, max=9))
    restart = [Signal(bool(0)) for _ in range(2)]


    def _test_stim():
        tbdut1 = example_instance(clock, rx_bit_cnt, restart[0], tomax)
        tbdut2 = example_nonlocal(clock, rx_bit_cnt, restart[1], tomax)
        
        @always(myhdl.delay(5))
        def tbclk():
            clock.next = not clock

        @instance
        def tbstim():
            for ii in range(tomax+2):
                yield clock.posedge
            assert restart[0]
            assert restart[1]
            raise myhdl.StopSimulation

        return tbdut1, tbdut2, tbclk, tbstim

    myhdl.Simulation(myhdl.traceSignals(_test_stim)).run()
    restart = Signal(bool(0))
    myhdl.toVerilog(example_instance, clock, rx_bit_cnt, restart)
    myhdl.toVerilog(example_nonlocal, clock, rx_bit_cnt, restart)


if __name__ == '__main__':
    test()