MyHDL simple counter.

counter.py

from myhdl import *

# counter with assign
def m_counter(i_clk, i_reset, o_count):
    #s_count = Signal(modbv(0, min=0, max=256))
    @always_seq(i_clk.posedge, reset=i_reset)
    def rtl_count():
        o_count.next = o_count + 1

    # following doesnt' convert with 0.8.1, sims ok
    #o_count.assign(s_count)  

    return rtl_count


# declare the signals and convert
i_clk = Signal(bool(0))
i_reset = ResetSignal(0, active=1, async=False)
o_count = Signal(modbv(0, min=0, max=256))

def _test():
    tbdut = m_counter(i_clk, i_reset, o_count)
    @always(delay(5))
    def tbclk():
        i_clk.next = not i_clk
    @instance
    def tbstim():
        i_reset.next = i_reset.active
        yield delay(100)
        i_reset.next = not i_reset.active
        yield i_clk.posedge
        ecnt = 0
        for ii in range(2000):
            assert o_count == ecnt
            #print(o_count)
            yield i_clk.posedge
            ecnt += 1
            if ecnt == 256:
                ecnt = 0
        raise StopSimulation

    return tbdut, tbclk, tbstim


Simulation(_test()).run()
toVHDL(m_counter, i_clk, i_reset, o_count)
toVerilog(m_counter, i_clk, i_reset, o_count)

m_counter.v

// File: m_counter.v
// Generated by MyHDL 0.8.1
// Date: Sun Mar 23 10:06:08 2014


`timescale 1ns/10ps

module m_counter (
    i_clk,
    i_reset,
    o_count
);


input i_clk;
input i_reset;
output [7:0] o_count;
reg [7:0] o_count;






always @(posedge i_clk) begin: M_COUNTER_RTL_COUNT
    if (i_reset == 1) begin
        o_count <= 0;
    end
    else begin
        o_count <= (o_count + 1);
    end
end

endmodule

m_counter.vhd

-- File: m_counter.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sun Mar 23 10:06:08 2014


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_081.all;

entity m_counter is
    port (
        i_clk: in std_logic;
        i_reset: in std_logic;
        o_count: inout unsigned(7 downto 0)
    );
end entity m_counter;


architecture MyHDL of m_counter is






begin




M_COUNTER_RTL_COUNT: process (i_clk) is
begin
    if rising_edge(i_clk) then
        if (i_reset = '1') then
            o_count <= to_unsigned(0, 8);
        else
            o_count <= (o_count + 1);
        end if;
    end if;
end process M_COUNTER_RTL_COUNT;

end architecture MyHDL;